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charset="utf-8" DP_GUI_MASTER_CNTL accesses the same values as DP_DATATYPE and DP_MIX. This was not reflected in how we stored register state. This meant that you could easily end up with stale state in one or the other register. This stores each field directly instead of packing them into a field named after the register. The register handlers then shift bits around if needed. This not only keeps things in sync but means less shifting and masking when using these values internally. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 41 +++++++++++++++++++++++++++++++++-------- hw/display/ati_2d.c | 12 ++++++------ hw/display/ati_int.h | 10 ++++++++-- hw/display/ati_regs.h | 33 +++++++++++++++++++++++++++++---- 4 files changed, 76 insertions(+), 20 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index e9c3ad2cd1..0bbe8915f1 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -460,7 +460,14 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) val =3D s->regs.dst_y; break; case DP_GUI_MASTER_CNTL: - val =3D s->regs.dp_gui_master_cntl; + val =3D s->regs.dp_gui_master_cntl | + (s->regs.dp_brush_datatype << 4) | + (s->regs.dp_dst_datatype << 8) | + (s->regs.dp_src_datatype << 12) | + (s->regs.byte_pix_order << 14) | + (s->regs.conversion_temp << 15) | + (s->regs.dp_rop3 << 16) | + (s->regs.dp_src_source << 24); break; case SRC_OFFSET: val =3D s->regs.src_offset; @@ -487,10 +494,15 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr= , unsigned int size) val =3D s->regs.dp_cntl; break; case DP_DATATYPE: - val =3D s->regs.dp_datatype; + val =3D (s->regs.dp_dst_datatype) | + (s->regs.dp_brush_datatype << 8) | + (s->regs.dp_src_datatype << 16) | + (s->regs.host_big_endian_en << 29) | + (s->regs.byte_pix_order << 30) | + (s->regs.conversion_temp << 31); break; case DP_MIX: - val =3D s->regs.dp_mix; + val =3D (s->regs.dp_rop3 << 16) | (s->regs.dp_src_source << 8); break; case DP_WRITE_MASK: val =3D s->regs.dp_write_mask; @@ -858,10 +870,17 @@ static void ati_mm_write(void *opaque, hwaddr addr, ati_2d_blt(s); break; case DP_GUI_MASTER_CNTL: + /* Mask out fields that are stored independently */ s->regs.dp_gui_master_cntl =3D data & 0xf800000f; - s->regs.dp_datatype =3D (data & 0x0f00) >> 8 | (data & 0x30f0) << = 4 | - (data & 0x4000) << 16; - s->regs.dp_mix =3D (data & GMC_ROP3_MASK) | (data & 0x7000000) >> = 16; + /* DP_DATATYPE fields */ + s->regs.dp_brush_datatype =3D (data & GMC_BRUSH_DATATYPE_MASK) >> = 4; + s->regs.dp_dst_datatype =3D (data & GMC_DST_DATATYPE_MASK) >> 8; + s->regs.dp_src_datatype =3D (data & GMC_SRC_DATATYPE_MASK) >> 12; + s->regs.byte_pix_order =3D (data & GMC_BYTE_PIX_ORDER) >> 14; + s->regs.conversion_temp =3D (data & GMC_CONVERSION_TEMP) >> 15; + /* DP_MIX fields */ + s->regs.dp_rop3 =3D (data & GMC_ROP3_MASK) >> 16; + s->regs.dp_src_source =3D (data & GMC_SRC_SOURCE_MASK) >> 24; break; case DST_WIDTH_X: s->regs.dst_x =3D data & 0x3fff; @@ -910,10 +929,16 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dp_cntl =3D data; break; case DP_DATATYPE: - s->regs.dp_datatype =3D data & 0xe0070f0f; + s->regs.dp_dst_datatype =3D (data & DP_DATATYPE_DST_DATATYPE_MASK); + s->regs.dp_brush_datatype =3D (data & DP_DATATYPE_BRUSH_DATATYPE_M= ASK) >> 8; + s->regs.dp_src_datatype =3D (data & DP_DATATYPE_SRC_DATATYPE_MASK)= >> 16; + s->regs.host_big_endian_en =3D (data & DP_DATATYPE_HOST_BE_EN) >> = 29; + s->regs.byte_pix_order =3D (data & DP_DATATYPE_BYTE_PIX_ORDER) >> = 30; + s->regs.conversion_temp =3D (data & DP_DATATYPE_CONVERSION_TEMP) >= > 31; break; case DP_MIX: - s->regs.dp_mix =3D data & 0x00ff0700; + s->regs.dp_src_source =3D (data & DP_MIX_SRC_SOURCE_MASK) >> 8; + s->regs.dp_rop3 =3D (data & DP_MIX_ROP3_MASK) >> 16; break; case DP_WRITE_MASK: s->regs.dp_write_mask =3D data; diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 309bb5ccb6..0531d1a526 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -26,7 +26,7 @@ =20 static int ati_bpp_from_datatype(ATIVGAState *s) { - switch (s->regs.dp_datatype & 0xf) { + switch (s->regs.dp_dst_datatype) { case 2: return 8; case 3: @@ -38,7 +38,7 @@ static int ati_bpp_from_datatype(ATIVGAState *s) return 32; default: qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n", - s->regs.dp_datatype & 0xf); + s->regs.dp_dst_datatype); return 0; } } @@ -53,7 +53,7 @@ void ati_2d_blt(ATIVGAState *s) DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), - (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); + (s->regs.dp_rop3)); unsigned dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_widt= h); unsigned dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? @@ -89,7 +89,7 @@ void ati_2d_blt(ATIVGAState *s) s->regs.dst_width, s->regs.dst_height, (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'), (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^')); - switch (s->regs.dp_mix & GMC_ROP3_MASK) { + switch (s->regs.dp_rop3) { case ROP3_SRCCOPY: { bool fallback =3D false; @@ -191,7 +191,7 @@ void ati_2d_blt(ATIVGAState *s) { uint32_t filler =3D 0; =20 - switch (s->regs.dp_mix & GMC_ROP3_MASK) { + switch (s->regs.dp_rop3) { case ROP3_PATCOPY: filler =3D s->regs.dp_brush_frgd_clr; break; @@ -239,6 +239,6 @@ void ati_2d_blt(ATIVGAState *s) } default: qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n", - (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); + s->regs.dp_rop3); } } diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index f5a47b82b0..59a1812034 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -75,13 +75,19 @@ typedef struct ATIVGARegs { uint32_t dp_src_frgd_clr; uint32_t dp_src_bkgd_clr; uint32_t dp_cntl; - uint32_t dp_datatype; - uint32_t dp_mix; uint32_t dp_write_mask; uint32_t default_offset; uint32_t default_pitch; uint32_t default_tile; uint32_t default_sc_bottom_right; + uint8_t dp_src_source; + uint8_t dp_rop3; + uint8_t dp_dst_datatype; + uint8_t dp_brush_datatype; + uint8_t dp_src_datatype; + bool host_big_endian_en; + bool byte_pix_order; + bool conversion_temp; } ATIVGARegs; =20 struct ATIVGAState { diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index d7127748ff..fce9270635 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -381,6 +381,12 @@ #define PM4_BUFFER_CNTL_NONPM4 0x00000000 =20 /* DP_DATATYPE bit constants */ +#define DP_DATATYPE_DST_DATATYPE_MASK 0x0000000f +#define DP_DATATYPE_BRUSH_DATATYPE_MASK 0x00000f00 +#define DP_DATATYPE_SRC_DATATYPE_MASK 0x00030000 +#define DP_DATATYPE_HOST_BE_EN 0x20000000 +#define DP_DATATYPE_BYTE_PIX_ORDER 0x40000000 +#define DP_DATATYPE_CONVERSION_TEMP 0x80000000 #define DST_8BPP 0x00000002 #define DST_15BPP 0x00000003 #define DST_16BPP 0x00000004 @@ -394,6 +400,11 @@ #define GMC_DST_PITCH_OFFSET_CNTL 0x00000002 #define GMC_SRC_CLIP_DEFAULT 0x00000000 #define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_BRUSH_DATATYPE_MASK 0x000000f0 +#define GMC_DST_DATATYPE_MASK 0x00000f00 +#define GMC_SRC_DATATYPE_MASK 0x00003000 +#define GMC_BYTE_PIX_ORDER 0x00004000 +#define GMC_CONVERSION_TEMP 0x00008000 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 #define GMC_SRC_DSTCOLOR 0x00003000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 @@ -404,12 +415,24 @@ #define GMC_WRITE_MASK_SET 0x40000000 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 =20 +/* DP_GUI_MASTER_CNTL DP_SRC_DATATYPE named constants */ +#define GMC_SRC_DATATYPE_MASK 0x00003000 +#define GMC_SRC_DATATYPE_MONO_FRGD_BKGD 0 +#define GMC_SRC_DATATYPE_MONO_FRGD 1 +#define GMC_SRC_DATATYPE_COLOR 3 + +/* DP_GUI_MASTER_CNTL DP_SRC_SOURCE named constants */ +#define GMC_SRC_SOURCE_MASK 0x07000000 +#define GMC_SRC_SOURCE_MEMORY 2 +#define GMC_SRC_SOURCE_HOST_DATA 3 +#define GMC_SRC_SOURCE_HOST_DATA_ALIGNED 4 + /* DP_GUI_MASTER_CNTL ROP3 named constants */ #define GMC_ROP3_MASK 0x00ff0000 -#define ROP3_BLACKNESS 0x00000000 -#define ROP3_SRCCOPY 0x00cc0000 -#define ROP3_PATCOPY 0x00f00000 -#define ROP3_WHITENESS 0x00ff0000 +#define ROP3_BLACKNESS 0 +#define ROP3_SRCCOPY 0xcc +#define ROP3_PATCOPY 0xf0 +#define ROP3_WHITENESS 0xff =20 #define SRC_DSTCOLOR 0x00030000 =20 @@ -434,6 +457,8 @@ #define DST_POLY_EDGE 0x00040000 =20 /* DP_MIX bit constants */ +#define DP_MIX_SRC_SOURCE_MASK 0x00000700 +#define DP_MIX_ROP3_MASK 0x00ff0000 #define DP_SRC_RECT 0x00000200 #define DP_SRC_HOST 0x00000300 #define DP_SRC_HOST_BYTEALIGN 0x00000400 --=20 2.51.2 From nobody Mon Feb 9 21:11:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Reading DST_PITCH and SRC_PITCH on the Rage 128 is broken. The read handlers attempt to construct the value from pitch and tile bits in the register state but mistakenly AND them instead of ORing them. This means the pitch is always zero on read. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 0bbe8915f1..2f919bcd22 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -438,7 +438,7 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, = unsigned int size) case DST_PITCH: val =3D s->regs.dst_pitch; if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - val &=3D s->regs.dst_tile << 16; + val |=3D s->regs.dst_tile << 16; } break; case DST_WIDTH: @@ -475,7 +475,7 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, = unsigned int size) case SRC_PITCH: val =3D s->regs.src_pitch; if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - val &=3D s->regs.src_tile << 16; + val |=3D s->regs.src_tile << 16; } break; case DP_BRUSH_BKGD_CLR: --=20 2.51.2 From nobody Mon Feb 9 21:11:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Implement read and write operations on SC_TOP_LEFT, SC_BOTTOM_RIGHT, and SRC_SC_BOTTOM_RIGHT registers. These registers are also updated when the src and/or dst clipping fields on DP_GUI_MASTER_CNTL are set to default clipping. Scissor clipping is used when rendering text in X.org. The r128 driver sends host data much wider than is necessary to draw a glyph and cuts it down to size using clipping before rendering. The actual clipping implementation follows in a future patch. This also includes a very minor refactor of the combined default_sc_bottom_right field in the registers struct to default_sc_bottom and default_sc_right. This was done to stay consistent with the other scissor registers and prevent repeated masking and extraction. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 71 +++++++++++++++++++++++++++++++++++++++++-- hw/display/ati_int.h | 9 +++++- hw/display/ati_regs.h | 2 ++ 3 files changed, 79 insertions(+), 3 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 2f919bcd22..bbae5455d0 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -520,7 +520,32 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) val |=3D s->regs.default_tile << 16; break; case DEFAULT_SC_BOTTOM_RIGHT: - val =3D s->regs.default_sc_bottom_right; + val =3D (s->regs.default_sc_bottom << 16) | + s->regs.default_sc_right; + break; + case SC_TOP: + val =3D s->regs.sc_top; + break; + case SC_LEFT: + val =3D s->regs.sc_left; + break; + case SC_BOTTOM: + val =3D s->regs.sc_bottom; + break; + case SC_RIGHT: + val =3D s->regs.sc_right; + break; + case SRC_SC_BOTTOM: + val =3D s->regs.src_sc_bottom; + break; + case SRC_SC_RIGHT: + val =3D s->regs.src_sc_right; + break; + case SC_TOP_LEFT: + case SC_BOTTOM_RIGHT: + case SRC_SC_BOTTOM_RIGHT: + qemu_log_mask(LOG_GUEST_ERROR, + "Read from write-only register 0x%x\n", (unsigned)ad= dr); break; default: break; @@ -881,6 +906,17 @@ static void ati_mm_write(void *opaque, hwaddr addr, /* DP_MIX fields */ s->regs.dp_rop3 =3D (data & GMC_ROP3_MASK) >> 16; s->regs.dp_src_source =3D (data & GMC_SRC_SOURCE_MASK) >> 24; + + if (!(data & GMC_SRC_CLIPPING)) { + s->regs.src_sc_right =3D s->regs.default_sc_right; + s->regs.src_sc_bottom =3D s->regs.default_sc_bottom; + } + if (!(data & GMC_DST_CLIPPING)) { + s->regs.sc_top =3D 0; + s->regs.sc_left =3D 0; + s->regs.sc_right =3D s->regs.default_sc_right; + s->regs.sc_bottom =3D s->regs.default_sc_bottom; + } break; case DST_WIDTH_X: s->regs.dst_x =3D data & 0x3fff; @@ -960,7 +996,38 @@ static void ati_mm_write(void *opaque, hwaddr addr, } break; case DEFAULT_SC_BOTTOM_RIGHT: - s->regs.default_sc_bottom_right =3D data & 0x3fff3fff; + s->regs.default_sc_right =3D data & 0x3fff; + s->regs.default_sc_bottom =3D (data >> 16) & 0x3fff; + break; + case SC_TOP_LEFT: + s->regs.sc_left =3D data & 0x3fff; + s->regs.sc_top =3D (data >> 16) & 0x3fff; + break; + case SC_LEFT: + s->regs.sc_left =3D data & 0x3fff; + break; + case SC_TOP: + s->regs.sc_top =3D data & 0x3fff; + break; + case SC_BOTTOM_RIGHT: + s->regs.sc_right =3D data & 0x3fff; + s->regs.sc_bottom =3D (data >> 16) & 0x3fff; + break; + case SC_RIGHT: + s->regs.sc_right =3D data & 0x3fff; + break; + case SC_BOTTOM: + s->regs.sc_bottom =3D data & 0x3fff; + break; + case SRC_SC_BOTTOM_RIGHT: + s->regs.src_sc_right =3D data & 0x3fff; + s->regs.src_sc_bottom =3D (data >> 16) & 0x3fff; + break; + case SRC_SC_RIGHT: + s->regs.src_sc_right =3D data & 0x3fff; + break; + case SRC_SC_BOTTOM: + s->regs.src_sc_bottom =3D data & 0x3fff; break; default: break; diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 59a1812034..d9ac8ee135 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -79,7 +79,6 @@ typedef struct ATIVGARegs { uint32_t default_offset; uint32_t default_pitch; uint32_t default_tile; - uint32_t default_sc_bottom_right; uint8_t dp_src_source; uint8_t dp_rop3; uint8_t dp_dst_datatype; @@ -88,6 +87,14 @@ typedef struct ATIVGARegs { bool host_big_endian_en; bool byte_pix_order; bool conversion_temp; + uint16_t default_sc_bottom; + uint16_t default_sc_right; + uint16_t sc_top; + uint16_t sc_left; + uint16_t sc_bottom; + uint16_t sc_right; + uint16_t src_sc_bottom; + uint16_t src_sc_right; } ATIVGARegs; =20 struct ATIVGAState { diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index fce9270635..9c638314f0 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -405,6 +405,8 @@ #define GMC_SRC_DATATYPE_MASK 0x00003000 #define GMC_BYTE_PIX_ORDER 0x00004000 #define GMC_CONVERSION_TEMP 0x00008000 +#define GMC_SRC_CLIPPING 0x00000004 +#define GMC_DST_CLIPPING 0x00000008 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 #define GMC_SRC_DSTCOLOR 0x00003000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 --=20 2.51.2 From nobody Mon Feb 9 21:11:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" These are straightforward 32-bit register write handlers. They're necessary for a future patch which will use them for color expansion from monochrome host data transfers. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index bbae5455d0..9a2c1260f7 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -964,6 +964,12 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DP_CNTL: s->regs.dp_cntl =3D data; break; + case DP_SRC_FRGD_CLR: + s->regs.dp_src_frgd_clr =3D data; + break; + case DP_SRC_BKGD_CLR: + s->regs.dp_src_bkgd_clr =3D data; + break; case DP_DATATYPE: s->regs.dp_dst_datatype =3D (data & DP_DATATYPE_DST_DATATYPE_MASK); s->regs.dp_brush_datatype =3D (data & DP_DATATYPE_BRUSH_DATATYPE_M= ASK) >> 8; --=20 2.51.2 From nobody Mon Feb 9 21:11:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=jablonski.xyz ARC-Seal: i=1; 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charset="utf-8" Hardware testing on the Rage 128 confirms that (SRC/DST)_OFFSET, and (SRC/DST)_PITCH are latched when (SRC/DST)_PITCH_OFFSET_CNTL bits in DP_GUI_MASTER_CNTL are set to "default". The earlier approach looked at the state of the (SRC/DST)_PITCH_OFFSET_CNTL bits when offset and pitch registers were used. This meant that when (SRC/DST)_PITCH_OFFSET_CNTL was reset to "leave alone" the old values stored in the registers would return. This is not how the real hardware works. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 8 ++++++++ hw/display/ati_2d.c | 13 ++++--------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 9a2c1260f7..04f1c3c790 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -907,6 +907,14 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dp_rop3 =3D (data & GMC_ROP3_MASK) >> 16; s->regs.dp_src_source =3D (data & GMC_SRC_SOURCE_MASK) >> 24; =20 + if (!(data & GMC_SRC_PITCH_OFFSET_CNTL)) { + s->regs.src_offset =3D s->regs.default_offset; + s->regs.src_pitch =3D s->regs.default_pitch; + } + if (!(data & GMC_DST_PITCH_OFFSET_CNTL)) { + s->regs.dst_offset =3D s->regs.default_offset; + s->regs.dst_pitch =3D s->regs.default_pitch; + } if (!(data & GMC_SRC_CLIPPING)) { s->regs.src_sc_right =3D s->regs.default_sc_right; s->regs.src_sc_bottom =3D s->regs.default_sc_bottom; diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 0531d1a526..b8df549474 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -43,8 +43,6 @@ static int ati_bpp_from_datatype(ATIVGAState *s) } } =20 -#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CN= TL) - void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -63,13 +61,12 @@ void ati_2d_blt(ATIVGAState *s) qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; } - int dst_stride =3D DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_= pitch; + int dst_stride =3D s->regs.dst_pitch; if (!dst_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); return; } - uint8_t *dst_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? - s->regs.dst_offset : s->regs.default_offset); + uint8_t *dst_bits =3D s->vga.vram_ptr + s->regs.dst_offset; =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; @@ -97,14 +94,12 @@ void ati_2d_blt(ATIVGAState *s) s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_wid= th); unsigned src_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_hei= ght); - int src_stride =3D DEFAULT_CNTL ? - s->regs.src_pitch : s->regs.default_pitch; + int src_stride =3D s->regs.src_pitch; if (!src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); return; } - uint8_t *src_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? - s->regs.src_offset : s->regs.default_offset); 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charset="utf-8" Use scissor registers to clip blit operations. This is required for text rendering in X using the r128 driver. Without it overly-wide glyphs are drawn and create all sorts of chaos. Use QemuRect helpers for calculating the intersection of the destination and scissor rectangles. Source coordinates are also updated to reflect clipping. The original destination dimensions are stored in 'dst' while the clipped rectangle is in 'visible' for clear distinction between the two. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 110 +++++++++++++++++++++++++++----------------- 1 file changed, 68 insertions(+), 42 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index b8df549474..145eb487c4 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -13,6 +13,7 @@ #include "qemu/log.h" #include "ui/pixel_ops.h" #include "ui/console.h" +#include "ui/rect.h" =20 /* * NOTE: @@ -43,6 +44,19 @@ static int ati_bpp_from_datatype(ATIVGAState *s) } } =20 +static QemuRect dst_rect(ATIVGAState *s) +{ + QemuRect dst; + unsigned dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? + s->regs.dst_x : + s->regs.dst_x + 1 - s->regs.dst_width); + unsigned dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? + s->regs.dst_y : + s->regs.dst_y + 1 - s->regs.dst_height); + qemu_rect_init(&dst, dst_x, dst_y, s->regs.dst_width, s->regs.dst_heig= ht); + return dst; +} + void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -51,11 +65,21 @@ void ati_2d_blt(ATIVGAState *s) DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), - (s->regs.dp_rop3)); - unsigned dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? - s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_widt= h); - unsigned dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_heig= ht); + s->regs.dp_rop3); + + QemuRect dst =3D dst_rect(s); + QemuRect scissor; + qemu_rect_init(&scissor, + s->regs.sc_left, s->regs.sc_top, + s->regs.sc_right - s->regs.sc_left + 1, + s->regs.sc_bottom - s->regs.sc_top + 1); + QemuRect visible; + if (!qemu_rect_intersect(&dst, &scissor, &visible)) { + return; + } + uint32_t src_left_offset =3D visible.x - dst.x; + uint32_t src_top_offset =3D visible.y - dst.y; + int bpp =3D ati_bpp_from_datatype(s); if (!bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); @@ -73,17 +97,16 @@ void ati_2d_blt(ATIVGAState *s) dst_stride *=3D bpp; } uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; - if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >=3D end - || dst_bits + dst_x - + (dst_y + s->regs.dst_height) * dst_stride >=3D end) { + if (visible.x > 0x3fff || visible.y > 0x3fff || dst_bits >=3D end + || dst_bits + visible.x + + (visible.y + visible.height) * dst_stride >=3D end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, - s->regs.src_x, s->regs.src_y, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_height, + s->regs.src_x, s->regs.src_y, dst.x, dst.y, dst.width, dst.hei= ght, (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'), (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^')); switch (s->regs.dp_rop3) { @@ -91,9 +114,11 @@ void ati_2d_blt(ATIVGAState *s) { bool fallback =3D false; unsigned src_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? - s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_wid= th); + s->regs.src_x + src_left_offset : + s->regs.src_x + 1 - dst.width + src_left_offset); unsigned src_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_hei= ght); + s->regs.src_y + src_top_offset : + s->regs.src_y + 1 - dst.height + src_top_offset); int src_stride =3D s->regs.src_pitch; if (!src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); @@ -107,7 +132,7 @@ void ati_2d_blt(ATIVGAState *s) } if (src_x > 0x3fff || src_y > 0x3fff || src_bits >=3D end || src_bits + src_x - + (src_y + s->regs.dst_height) * src_stride >=3D end) { + + (src_y + visible.height) * src_stride >=3D end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } @@ -116,31 +141,31 @@ void ati_2d_blt(ATIVGAState *s) dst_stride /=3D sizeof(uint32_t); DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, - src_x, src_y, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_height); + src_x, src_y, visible.x, visible.y, + visible.width, visible.height); #ifdef CONFIG_PIXMAN if ((s->use_pixman & BIT(1)) && s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT && s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { fallback =3D !pixman_blt((uint32_t *)src_bits, (uint32_t *)dst= _bits, src_stride, dst_stride, bpp, bpp, - src_x, src_y, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_height); + src_x, src_y, visible.x, visible.y, + visible.width, visible.height); } else if (s->use_pixman & BIT(1)) { /* FIXME: We only really need a temporary if src and dst overl= ap */ - int llb =3D s->regs.dst_width * (bpp / 8); + int llb =3D visible.width * (bpp / 8); int tmp_stride =3D DIV_ROUND_UP(llb, sizeof(uint32_t)); uint32_t *tmp =3D g_malloc(tmp_stride * sizeof(uint32_t) * - s->regs.dst_height); + visible.height); fallback =3D !pixman_blt((uint32_t *)src_bits, tmp, src_stride, tmp_stride, bpp, bpp, src_x, src_y, 0, 0, - s->regs.dst_width, s->regs.dst_height); + visible.width, visible.height); if (!fallback) { fallback =3D !pixman_blt(tmp, (uint32_t *)dst_bits, tmp_stride, dst_stride, bpp, bpp, - 0, 0, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_heig= ht); + 0, 0, visible.x, visible.y, + visible.width, visible.height); } g_free(tmp); } else @@ -153,17 +178,17 @@ void ati_2d_blt(ATIVGAState *s) unsigned int src_pitch =3D src_stride * sizeof(uint32_t); unsigned int dst_pitch =3D dst_stride * sizeof(uint32_t); =20 - for (y =3D 0; y < s->regs.dst_height; y++) { - i =3D dst_x * bypp; + for (y =3D 0; y < visible.height; y++) { + i =3D visible.x * bypp; j =3D src_x * bypp; if (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { - i +=3D (dst_y + y) * dst_pitch; + i +=3D (visible.y + y) * dst_pitch; j +=3D (src_y + y) * src_pitch; } else { - i +=3D (dst_y + s->regs.dst_height - 1 - y) * dst_pitc= h; - j +=3D (src_y + s->regs.dst_height - 1 - y) * src_pitc= h; + i +=3D (visible.y + visible.height - 1 - y) * dst_pitc= h; + j +=3D (src_y + visible.height - 1 - y) * src_pitch; } - memmove(&dst_bits[i], &src_bits[j], s->regs.dst_width * by= pp); + memmove(&dst_bits[i], &src_bits[j], visible.width * bypp); } } if (dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && @@ -171,13 +196,13 @@ void ati_2d_blt(ATIVGAState *s) s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + s->regs.dst_offset + - dst_y * surface_stride(ds), - s->regs.dst_height * surface_stride(ds= )); + visible.y * surface_stride(ds), + visible.height * surface_stride(ds)); } s->regs.dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? - dst_x + s->regs.dst_width : dst_x); + visible.x + visible.width : visible.x); s->regs.dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - dst_y + s->regs.dst_height : dst_y); + visible.y + visible.height : visible.y); break; } case ROP3_PATCOPY: @@ -202,20 +227,21 @@ void ati_2d_blt(ATIVGAState *s) =20 dst_stride /=3D sizeof(uint32_t); DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", - dst_bits, dst_stride, bpp, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_height, filler); + dst_bits, dst_stride, bpp, visible.x, visible.y, + visible.width, visible.height, filler); #ifdef CONFIG_PIXMAN if (!(s->use_pixman & BIT(0)) || - !pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, dst_x, dst= _y, - s->regs.dst_width, s->regs.dst_height, filler)) + !pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, + visible.x, visible.y, visible.width, visible.heig= ht, + filler)) #endif { /* fallback when pixman failed or we don't want to call it */ unsigned int x, y, i, bypp =3D bpp / 8; unsigned int dst_pitch =3D dst_stride * sizeof(uint32_t); - for (y =3D 0; y < s->regs.dst_height; y++) { - i =3D dst_x * bypp + (dst_y + y) * dst_pitch; - for (x =3D 0; x < s->regs.dst_width; x++, i +=3D bypp) { + for (y =3D 0; y < visible.height; y++) { + i =3D visible.x * bypp + (visible.y + y) * dst_pitch; + for (x =3D 0; x < visible.width; x++, i +=3D bypp) { stn_he_p(&dst_bits[i], bypp, filler); } } @@ -225,11 +251,11 @@ void ati_2d_blt(ATIVGAState *s) s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + s->regs.dst_offset + - dst_y * surface_stride(ds), - s->regs.dst_height * surface_stride(ds= )); + visible.y * surface_stride(ds), + visible.height * surface_stride(ds)); } s->regs.dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - dst_y + s->regs.dst_height : dst_y); + visible.y + visible.height : visible.y); break; } default: --=20 2.51.2 From nobody Mon Feb 9 21:11:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=jablonski.xyz ARC-Seal: i=1; a=rsa-sha256; t=1767725938; cv=none; d=zohomail.com; s=zohoarc; b=THpFjx6CMiMbKSSaNc2c1kwhGTagv46Vrb5GS1rXlB61+fI4MEOwTbjLMFn9l4t2R/66htEQJ9JgX+huVm7MHUWI/q23IyMZ24nBxTwBWcISISFRaQWbEgKdVob20HCy8Vb9ptTrEhzs3dChGM91MuxfXjYaNS9Dy23wqs5lkF4= ARC-Message-Signature: i=1; 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charset="utf-8" A large amount of the common setup involved in a blit deals with the destination. This moves that setup to a helper function returning a struct (ATIBlitDest) holding all of that state. The idea here is that this setup will be shared between blits from memory as well as from HOST_DATA and maybe others in the future. Otherwise this is a pure refactor of the ati_2d_blt function to make use of the setup_2d_blt_dst helper and the struct it returns. There should be no changes in behavior in this patch. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 218 +++++++++++++++++++++++++------------------- 1 file changed, 124 insertions(+), 94 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 145eb487c4..6c36e55412 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -57,68 +57,96 @@ static QemuRect dst_rect(ATIVGAState *s) return dst; } =20 -void ati_2d_blt(ATIVGAState *s) -{ - /* FIXME it is probably more complex than this and may need to be */ - /* rewritten but for now as a start just to get some output: */ - DisplaySurface *ds =3D qemu_console_surface(s->vga.con); - DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, - s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), - surface_bits_per_pixel(ds), - s->regs.dp_rop3); +typedef struct { + QemuRect rect; + QemuRect visible; + uint32_t src_left_offset; + uint32_t src_top_offset; + int bpp; + int stride; + bool top_to_bottom; + bool left_to_right; + bool valid; + uint8_t *bits; +} ATIBlitDest; =20 - QemuRect dst =3D dst_rect(s); +static ATIBlitDest setup_2d_blt_dst(ATIVGAState *s) +{ + ATIBlitDest dst =3D { .valid =3D false }; + uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; QemuRect scissor; qemu_rect_init(&scissor, s->regs.sc_left, s->regs.sc_top, s->regs.sc_right - s->regs.sc_left + 1, s->regs.sc_bottom - s->regs.sc_top + 1); - QemuRect visible; - if (!qemu_rect_intersect(&dst, &scissor, &visible)) { - return; - } - uint32_t src_left_offset =3D visible.x - dst.x; - uint32_t src_top_offset =3D visible.y - dst.y; =20 - int bpp =3D ati_bpp_from_datatype(s); - if (!bpp) { + dst.rect =3D dst_rect(s); + if (!qemu_rect_intersect(&dst.rect, &scissor, &dst.visible)) { + /* Destination is completely clipped, nothing to draw */ + return dst; + } + dst.bpp =3D ati_bpp_from_datatype(s); + if (!dst.bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); - return; + return dst; } - int dst_stride =3D s->regs.dst_pitch; - if (!dst_stride) { + dst.stride =3D s->regs.dst_pitch; + if (!dst.stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); - return; + return dst; } - uint8_t *dst_bits =3D s->vga.vram_ptr + s->regs.dst_offset; - + dst.bits =3D s->vga.vram_ptr + s->regs.dst_offset; if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; - dst_stride *=3D bpp; + dst.bits +=3D s->regs.crtc_offset & 0x07ffffff; + dst.stride *=3D dst.bpp; } - uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; - if (visible.x > 0x3fff || visible.y > 0x3fff || dst_bits >=3D end - || dst_bits + visible.x - + (visible.y + visible.height) * dst_stride >=3D end) { + if (dst.visible.x > 0x3fff || dst.visible.y > 0x3fff || dst.bits >=3D = end + || dst.bits + dst.visible.x + + (dst.visible.y + dst.visible.height) * dst.stride >=3D end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); - return; + return dst; } + dst.src_left_offset =3D dst.visible.x - dst.rect.x; + dst.src_top_offset =3D dst.visible.y - dst.rect.y; + dst.left_to_right =3D s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT; + dst.top_to_bottom =3D s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM; + dst.valid =3D true; + + return dst; +} + +void ati_2d_blt(ATIVGAState *s) +{ + /* FIXME it is probably more complex than this and may need to be */ + /* rewritten but for now as a start just to get some output: */ + DisplaySurface *ds =3D qemu_console_surface(s->vga.con); + DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, + s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), + surface_bits_per_pixel(ds), + s->regs.dp_rop3); + ATIBlitDest dst =3D setup_2d_blt_dst(s); + uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; + DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, - s->regs.src_x, s->regs.src_y, dst.x, dst.y, dst.width, dst.hei= ght, - (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'), - (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^')); + s->regs.src_x, s->regs.src_y, + dst.rect.x, dst.rect.y, dst.rect.width, dst.rect.height, + (dst.left_to_right ? '>' : '<'), + (dst.top_to_bottom ? 'v' : '^')); + switch (s->regs.dp_rop3) { case ROP3_SRCCOPY: { bool fallback =3D false; - unsigned src_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? - s->regs.src_x + src_left_offset : - s->regs.src_x + 1 - dst.width + src_left_offset); - unsigned src_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - s->regs.src_y + src_top_offset : - s->regs.src_y + 1 - dst.height + src_top_offset); + unsigned src_x =3D (dst.left_to_right ? + s->regs.src_x + dst.src_left_offset : + s->regs.src_x + 1 - + dst.rect.width + dst.src_left_offset); + unsigned src_y =3D (dst.top_to_bottom ? + s->regs.src_y + dst.src_top_offset : + s->regs.src_y + 1 - + dst.rect.height + dst.src_top_offset); int src_stride =3D s->regs.src_pitch; if (!src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); @@ -128,44 +156,44 @@ void ati_2d_blt(ATIVGAState *s) =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { src_bits +=3D s->regs.crtc_offset & 0x07ffffff; - src_stride *=3D bpp; + src_stride *=3D dst.bpp; } if (src_x > 0x3fff || src_y > 0x3fff || src_bits >=3D end || src_bits + src_x - + (src_y + visible.height) * src_stride >=3D end) { + + (src_y + dst.visible.height) * src_stride >=3D end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } =20 src_stride /=3D sizeof(uint32_t); - dst_stride /=3D sizeof(uint32_t); + dst.stride /=3D sizeof(uint32_t); DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", - src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, - src_x, src_y, visible.x, visible.y, - visible.width, visible.height); + src_bits, dst.bits, src_stride, dst.stride, dst.bpp, dst.b= pp, + src_x, src_y, dst.visible.x, dst.visible.y, + dst.visible.width, dst.visible.height); #ifdef CONFIG_PIXMAN if ((s->use_pixman & BIT(1)) && - s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT && - s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { - fallback =3D !pixman_blt((uint32_t *)src_bits, (uint32_t *)dst= _bits, - src_stride, dst_stride, bpp, bpp, - src_x, src_y, visible.x, visible.y, - visible.width, visible.height); + dst.left_to_right && + dst.top_to_bottom) { + fallback =3D !pixman_blt((uint32_t *)src_bits, (uint32_t *)dst= .bits, + src_stride, dst.stride, dst.bpp, dst.bp= p, + src_x, src_y, dst.visible.x, dst.visibl= e.y, + dst.visible.width, dst.visible.height); } else if (s->use_pixman & BIT(1)) { /* FIXME: We only really need a temporary if src and dst overl= ap */ - int llb =3D visible.width * (bpp / 8); + int llb =3D dst.visible.width * (dst.bpp / 8); int tmp_stride =3D DIV_ROUND_UP(llb, sizeof(uint32_t)); uint32_t *tmp =3D g_malloc(tmp_stride * sizeof(uint32_t) * - visible.height); + dst.visible.height); fallback =3D !pixman_blt((uint32_t *)src_bits, tmp, - src_stride, tmp_stride, bpp, bpp, + src_stride, tmp_stride, dst.bpp, dst.bp= p, src_x, src_y, 0, 0, - visible.width, visible.height); + dst.visible.width, dst.visible.height); if (!fallback) { - fallback =3D !pixman_blt(tmp, (uint32_t *)dst_bits, - tmp_stride, dst_stride, bpp, bpp, - 0, 0, visible.x, visible.y, - visible.width, visible.height); + fallback =3D !pixman_blt(tmp, (uint32_t *)dst.bits, + tmp_stride, dst.stride, dst.bpp, ds= t.bpp, + 0, 0, dst.visible.x, dst.visible.y, + dst.visible.width, dst.visible.heig= ht); } g_free(tmp); } else @@ -174,35 +202,36 @@ void ati_2d_blt(ATIVGAState *s) fallback =3D true; } if (fallback) { - unsigned int y, i, j, bypp =3D bpp / 8; + unsigned int y, i, j, bypp =3D dst.bpp / 8; unsigned int src_pitch =3D src_stride * sizeof(uint32_t); - unsigned int dst_pitch =3D dst_stride * sizeof(uint32_t); + unsigned int dst_pitch =3D dst.stride * sizeof(uint32_t); =20 - for (y =3D 0; y < visible.height; y++) { - i =3D visible.x * bypp; + for (y =3D 0; y < dst.visible.height; y++) { + i =3D dst.visible.x * bypp; j =3D src_x * bypp; - if (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { - i +=3D (visible.y + y) * dst_pitch; + if (dst.top_to_bottom) { + i +=3D (dst.visible.y + y) * dst_pitch; j +=3D (src_y + y) * src_pitch; } else { - i +=3D (visible.y + visible.height - 1 - y) * dst_pitc= h; - j +=3D (src_y + visible.height - 1 - y) * src_pitch; + i +=3D (dst.visible.y + dst.visible.height - 1 - y) * + dst_pitch; + j +=3D (src_y + dst.visible.height - 1 - y) * src_pitc= h; } - memmove(&dst_bits[i], &src_bits[j], visible.width * bypp); + memmove(&dst.bits[i], &src_bits[j], dst.visible.width * by= pp); } } - if (dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && - dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + + if (dst.bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && + dst.bits < s->vga.vram_ptr + s->vga.vbe_start_addr + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + s->regs.dst_offset + - visible.y * surface_stride(ds), - visible.height * surface_stride(ds)); + dst.visible.y * surface_stride(ds), + dst.visible.height * surface_stride(ds= )); } - s->regs.dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? - visible.x + visible.width : visible.x); - s->regs.dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - visible.y + visible.height : visible.y); + s->regs.dst_x =3D (dst.left_to_right ? + dst.visible.x + dst.visible.width : dst.visible.x= ); + s->regs.dst_y =3D (dst.top_to_bottom ? + dst.visible.y + dst.visible.height : dst.visible.= y); break; } case ROP3_PATCOPY: @@ -225,37 +254,38 @@ void ati_2d_blt(ATIVGAState *s) break; } =20 - dst_stride /=3D sizeof(uint32_t); + dst.stride /=3D sizeof(uint32_t); DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", - dst_bits, dst_stride, bpp, visible.x, visible.y, - visible.width, visible.height, filler); + dst.bits, dst.stride, dst.bpp, dst.visible.x, dst.visible.= y, + dst.visible.width, dst.visible.height, filler); #ifdef CONFIG_PIXMAN if (!(s->use_pixman & BIT(0)) || - !pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, - visible.x, visible.y, visible.width, visible.heig= ht, + !pixman_fill((uint32_t *)dst.bits, dst.stride, dst.bpp, + dst.visible.x, dst.visible.y, + dst.visible.width, dst.visible.height, filler)) #endif { /* fallback when pixman failed or we don't want to call it */ - unsigned int x, y, i, bypp =3D bpp / 8; - unsigned int dst_pitch =3D dst_stride * sizeof(uint32_t); - for (y =3D 0; y < visible.height; y++) { - i =3D visible.x * bypp + (visible.y + y) * dst_pitch; - for (x =3D 0; x < visible.width; x++, i +=3D bypp) { - stn_he_p(&dst_bits[i], bypp, filler); + unsigned int x, y, i, bypp =3D dst.bpp / 8; + unsigned int dst_pitch =3D dst.stride * sizeof(uint32_t); + for (y =3D 0; y < dst.visible.height; y++) { + i =3D dst.visible.x * bypp + (dst.visible.y + y) * dst_pit= ch; + for (x =3D 0; x < dst.visible.width; x++, i +=3D bypp) { + stn_he_p(&dst.bits[i], bypp, filler); } } } - if (dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && - dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + + if (dst.bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && + dst.bits < s->vga.vram_ptr + s->vga.vbe_start_addr + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + s->regs.dst_offset + - visible.y * surface_stride(ds), - visible.height * surface_stride(ds)); + dst.visible.y * surface_stride(ds), + dst.visible.height * surface_stride(ds= )); } - s->regs.dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - visible.y + visible.height : visible.y); + s->regs.dst_y =3D (dst.top_to_bottom ? + dst.visible.y + dst.visible.height : dst.visible.= y); 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charset="utf-8" Writing to any of the HOST_DATA0-7 registers pushes the written data into a 128-bit accumulator. When the accumulator is full a flush is triggered to copy it to the framebuffer. A final write to HOST_DATA_LAST will also initiate a flush. The flush itself is left for the next patch. Unaligned HOST_DATA* writes result in, from what I can tell, undefined behavior on real hardware. A well-behaved driver shouldn't be doing this anyway. For that reason they are not handled here at all. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 32 ++++++++++++++++++++++++++++++++ hw/display/ati_dbg.c | 9 +++++++++ hw/display/ati_int.h | 9 +++++++++ hw/display/ati_regs.h | 9 +++++++++ 4 files changed, 59 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index 04f1c3c790..88d30bf532 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -567,6 +567,13 @@ static inline void ati_reg_write_offs(uint32_t *reg, i= nt offs, } } =20 +static void ati_host_data_reset(ATIHostDataState *hd) +{ + hd->next =3D 0; + hd->row =3D 0; + hd->col =3D 0; +} + static void ati_mm_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { @@ -842,6 +849,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, break; case DST_WIDTH: s->regs.dst_width =3D data & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case DST_HEIGHT: @@ -892,6 +900,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DST_HEIGHT_WIDTH: s->regs.dst_width =3D data & 0x3fff; s->regs.dst_height =3D (data >> 16) & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case DP_GUI_MASTER_CNTL: @@ -929,6 +938,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DST_WIDTH_X: s->regs.dst_x =3D data & 0x3fff; s->regs.dst_width =3D (data >> 16) & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case SRC_X_Y: @@ -942,6 +952,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DST_WIDTH_HEIGHT: s->regs.dst_height =3D data & 0x3fff; s->regs.dst_width =3D (data >> 16) & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case DST_HEIGHT_Y: @@ -1043,6 +1054,25 @@ static void ati_mm_write(void *opaque, hwaddr addr, case SRC_SC_BOTTOM: s->regs.src_sc_bottom =3D data & 0x3fff; break; + case HOST_DATA0: + case HOST_DATA1: + case HOST_DATA2: + case HOST_DATA3: + case HOST_DATA4: + case HOST_DATA5: + case HOST_DATA6: + case HOST_DATA7: + s->host_data.acc[s->host_data.next++] =3D data; + if (s->host_data.next >=3D 4) { + qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\= n"); + s->host_data.next =3D 0; + } + break; + case HOST_DATA_LAST: + s->host_data.acc[s->host_data.next] =3D data; + qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\n"); + ati_host_data_reset(&s->host_data); + break; default: break; } @@ -1136,6 +1166,8 @@ static void ati_vga_reset(DeviceState *dev) /* reset vga */ vga_common_reset(&s->vga); s->mode =3D VGA_MODE; + + ati_host_data_reset(&s->host_data); } =20 static void ati_vga_exit(PCIDevice *dev) diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c index 3ffa7f35df..5c799d540a 100644 --- a/hw/display/ati_dbg.c +++ b/hw/display/ati_dbg.c @@ -252,6 +252,15 @@ static struct ati_regdesc ati_reg_names[] =3D { {"MC_SRC1_CNTL", 0x19D8}, {"TEX_CNTL", 0x1800}, {"RAGE128_MPP_TB_CONFIG", 0x01c0}, + {"HOST_DATA0", 0x17c0}, + {"HOST_DATA1", 0x17c4}, + {"HOST_DATA2", 0x17c8}, + {"HOST_DATA3", 0x17cc}, + {"HOST_DATA4", 0x17d0}, + {"HOST_DATA5", 0x17d4}, + {"HOST_DATA6", 0x17d8}, + {"HOST_DATA7", 0x17dc}, + {"HOST_DATA_LAST", 0x17e0}, {NULL, -1} }; =20 diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index d9ac8ee135..3029dc7e3c 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -14,6 +14,7 @@ #include "hw/i2c/bitbang_i2c.h" #include "vga_int.h" #include "qom/object.h" +#include "qemu/units.h" =20 /*#define DEBUG_ATI*/ =20 @@ -97,6 +98,13 @@ typedef struct ATIVGARegs { uint16_t src_sc_right; } ATIVGARegs; =20 +typedef struct ATIHostDataState { + uint32_t row; + uint32_t col; + uint32_t next; + uint32_t acc[4]; +} ATIHostDataState; + struct ATIVGAState { PCIDevice dev; VGACommonState vga; @@ -113,6 +121,7 @@ struct ATIVGAState { MemoryRegion io; MemoryRegion mm; ATIVGARegs regs; + ATIHostDataState host_data; }; =20 const char *ati_reg_name(int num); diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 9c638314f0..c8bbafe1c6 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -252,6 +252,15 @@ #define DP_T12_CNTL 0x178c #define DST_BRES_T1_LNTH 0x1790 #define DST_BRES_T2_LNTH 0x1794 +#define HOST_DATA0 0x17c0 +#define HOST_DATA1 0x17c4 +#define HOST_DATA2 0x17c8 +#define HOST_DATA3 0x17cc +#define HOST_DATA4 0x17d0 +#define HOST_DATA5 0x17d4 +#define HOST_DATA6 0x17d8 +#define HOST_DATA7 0x17dc +#define HOST_DATA_LAST 0x17e0 #define SCALE_SRC_HEIGHT_WIDTH 0x1994 #define SCALE_OFFSET_0 0x1998 #define SCALE_PITCH 0x199c --=20 2.51.2 From nobody Mon Feb 9 21:11:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Implement flushing the 128-bit HOST_DATA accumulator to VRAM to enable text rendering in X. Currently supports only the monochrome foreground/background datatype with the SRCCOPY ROP. The flush is broken up into two steps for clarity. First, expansion of the monochrome bits to the destination color depth. Then the expanded pixels are clipped and copied into VRAM. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 4 +- hw/display/ati_2d.c | 124 +++++++++++++++++++++++++++++++++++++++++++ hw/display/ati_int.h | 3 ++ 3 files changed, 129 insertions(+), 2 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 88d30bf532..cc5899981b 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -1064,13 +1064,13 @@ static void ati_mm_write(void *opaque, hwaddr addr, case HOST_DATA7: s->host_data.acc[s->host_data.next++] =3D data; if (s->host_data.next >=3D 4) { - qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\= n"); + ati_flush_host_data(s); s->host_data.next =3D 0; } break; case HOST_DATA_LAST: s->host_data.acc[s->host_data.next] =3D data; - qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\n"); + ati_flush_host_data(s); ati_host_data_reset(&s->host_data); break; default: diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 6c36e55412..19130ed291 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -117,6 +117,11 @@ static ATIBlitDest setup_2d_blt_dst(ATIVGAState *s) =20 void ati_2d_blt(ATIVGAState *s) { + if (s->regs.dp_src_source =3D=3D GMC_SRC_SOURCE_HOST_DATA) { + /* HOST_DATA blits are handled separately by ati_flush_host_data()= */ + return; + } + /* FIXME it is probably more complex than this and may need to be */ /* rewritten but for now as a start just to get some output: */ DisplaySurface *ds =3D qemu_console_surface(s->vga.con); @@ -293,3 +298,122 @@ void ati_2d_blt(ATIVGAState *s) s->regs.dp_rop3); } } + +void ati_flush_host_data(ATIVGAState *s) +{ + DisplaySurface *ds; + ATIBlitDest dst; + uint32_t fg, bg; + unsigned bypp, row, col, idx; + uint8_t pix_buf[ATI_HOST_DATA_ACC_BITS * sizeof(uint32_t)]; + + if (s->regs.dp_src_source !=3D GMC_SRC_SOURCE_HOST_DATA) { + qemu_log_mask(LOG_UNIMP, + "host_data_blt: only GMC_SRC_SOURCE_HOST_DATA " + "supported\n"); + return; + } + + if (s->regs.dp_src_datatype !=3D GMC_SRC_DATATYPE_MONO_FRGD_BKGD) { + qemu_log_mask(LOG_UNIMP, + "host_data_blt: only GMC_SRC_DATATYPE_MONO_FRGD_BKGD= " + "supported\n"); + return; + } + + if (s->regs.dp_rop3 !=3D ROP3_SRCCOPY) { + qemu_log_mask(LOG_UNIMP, + "host_data_blt: only ROP3_SRCCOPY supported. rop: %x= \n", + s->regs.dp_rop3); + return; + } + + dst =3D setup_2d_blt_dst(s); + if (!dst.valid) { + return; + } + + if (!dst.left_to_right || !dst.top_to_bottom) { + qemu_log_mask(LOG_UNIMP, "host_data_blt: only L->R, T->B supported= \n"); + return; + } + + fg =3D s->regs.dp_src_frgd_clr; + bg =3D s->regs.dp_src_bkgd_clr; + bypp =3D dst.bpp / 8; + + /* Expand monochrome bits to color pixels */ + idx =3D 0; + for (int word =3D 0; word < 4; word++) { + for (int byte =3D 0; byte < 4; byte++) { + uint8_t byte_val =3D s->host_data.acc[word] >> (byte * 8); + for (int i =3D 0; i < 8; i++) { + int bit =3D s->regs.byte_pix_order ? i : (7 - i); + bool is_fg =3D extract8(byte_val, bit, 1); + uint32_t color =3D is_fg ? fg : bg; + stn_he_p(&pix_buf[idx * bypp], bypp, color); + idx +=3D 1; + } + } + } + + /* Copy to VRAM one scanline at a time */ + row =3D s->host_data.row; + col =3D s->host_data.col; + idx =3D 0; + while (idx < ATI_HOST_DATA_ACC_BITS && row < dst.rect.height) { + uint8_t *vram_dst; + unsigned start_col, end_col, vis_row, num_pix, pix_idx; + unsigned pix_in_scanline =3D MIN(ATI_HOST_DATA_ACC_BITS - + idx, dst.rect.width - col); + + /* Row-based clipping */ + if (row < dst.src_top_offset || + row >=3D dst.src_top_offset + dst.visible.height) { + goto skip_pix; + } + + /* Column-based clipping */ + start_col =3D MAX(col, dst.src_left_offset); + end_col =3D MIN(col + pix_in_scanline, + dst.src_left_offset + dst.visible.width); + if (end_col <=3D start_col) { + goto skip_pix; + } + + /* Copy expanded bits/pixels to VRAM */ + vis_row =3D row - dst.src_top_offset; + num_pix =3D end_col - start_col; + vram_dst =3D dst.bits + + (dst.visible.y + vis_row) * dst.stride + + (dst.visible.x + (start_col - dst.src_left_offset)) * b= ypp; + + pix_idx =3D (idx + (start_col - col)) * bypp; + memcpy(vram_dst, &pix_buf[pix_idx], num_pix * bypp); + + skip_pix: + idx +=3D pix_in_scanline; + col +=3D pix_in_scanline; + if (col >=3D dst.rect.width) { + col =3D 0; + row +=3D 1; + } + } + /* Track state of the overall blit for use by the next flush */ + s->host_data.row =3D row; + s->host_data.col =3D col; + + /* + * TODO: This is setting the entire blit region to dirty. + * We maybe just need this tiny section? + */ + ds =3D qemu_console_surface(s->vga.con); + if (dst.bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && + dst.bits < s->vga.vram_ptr + s->vga.vbe_start_addr + + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { + memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + + s->regs.dst_offset + + dst.visible.y * surface_stride(ds), + dst.visible.height * surface_stride(ds)); + } +} diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 3029dc7e3c..448daf44a9 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -30,6 +30,8 @@ /* Radeon RV100 (VE) */ #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 =20 +#define ATI_HOST_DATA_ACC_BITS 128 + #define TYPE_ATI_VGA "ati-vga" OBJECT_DECLARE_SIMPLE_TYPE(ATIVGAState, ATI_VGA) =20 @@ -127,5 +129,6 @@ struct ATIVGAState { const char *ati_reg_name(int num); =20 void ati_2d_blt(ATIVGAState *s); +void ati_flush_host_data(ATIVGAState *s); =20 #endif /* ATI_INT_H */ --=20 2.51.2