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a="69087544" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69087544" X-CSE-ConnectionGUID: I3PTbNLVTYayBcrfiPemrA== X-CSE-MsgGUID: 27O1sOsoR6+a7qSzW0fx3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588681" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 01/19] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Date: Tue, 6 Jan 2026 01:12:43 -0500 Message-ID: <20260106061304.314546-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1767680224033158500 In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry of rid2pasid, then it was extended to get any pasid entry. So a new name vtd_ce_get_pasid_entry is better to match what it actually does. No functional change intended. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif Reviewed-by: Yi Liu Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Michael S. Tsirkin --- hw/i386/intel_iommu.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 224b7b9479..436a30288b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -954,10 +954,8 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState= *s, return 0; } =20 -static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, - VTDContextEntry *ce, - VTDPASIDEntry *pe, - uint32_t pasid) +static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, + VTDPASIDEntry *pe, uint32_t pasid) { dma_addr_t pasid_dir_base; int ret =3D 0; @@ -1035,7 +1033,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return VTD_PE_GET_FL_LEVEL(&pe); } else { @@ -1058,7 +1056,7 @@ static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; } =20 @@ -1126,7 +1124,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; } else { @@ -1532,7 +1530,7 @@ static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, * has valid rid2pasid setting, which includes valid * rid2pasid field and corresponding pasid entry setting */ - return vtd_ce_get_rid2pasid_entry(s, ce, &pe, PCI_NO_PASID); + return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID); } =20 /* Map a device to its corresponding domain (context-entry) */ @@ -1621,7 +1619,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return VTD_SM_PASID_ENTRY_DID(pe.val[1]); } =20 @@ -1697,7 +1695,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, int ret; =20 if (s->root_scalable) { - ret =3D vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + ret =3D vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (ret) { /* * This error is guest triggerable. We should assumt PT @@ -3083,7 +3081,7 @@ static inline int vtd_dev_get_pe_from_pasid(VTDAddres= sSpace *vtd_as, return ret; } =20 - return vtd_ce_get_rid2pasid_entry(s, &ce, pe, vtd_as->pasid); + return vtd_ce_get_pasid_entry(s, &ce, pe, vtd_as->pasid); } =20 static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) @@ -5161,7 +5159,7 @@ static int vtd_pri_perform_implicit_invalidation(VTDA= ddressSpace *vtd_as, if (ret) { return -EINVAL; } - ret =3D vtd_ce_get_rid2pasid_entry(s, &ce, &pe, vtd_as->pasid); + ret =3D vtd_ce_get_pasid_entry(s, &ce, &pe, vtd_as->pasid); if (ret) { return -EINVAL; } --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; 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d="scan'208";a="202588695" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 02/19] intel_iommu: Delete RPS capability related supporting code Date: Tue, 6 Jan 2026 01:12:44 -0500 Message-ID: <20260106061304.314546-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" RID-PASID Support(RPS) is not set in vIOMMU ECAP register, the supporting code is there but never takes effect. Meanwhile, according to VTD spec section 3.4.3: "Implementations not supporting RID_PASID capability (ECAP_REG.RPS is 0b), use a PASID value of 0 to perform address translation for requests without PASID." We should delete the supporting code which fetches RID_PASID field from scalable context entry and use 0 as RID_PASID directly, because RID_PASID field is ignored if no RPS support according to spec. This simplifies the code and doesn't bring any penalty. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 2 +- hw/i386/intel_iommu.c | 89 +++++++++++----------------------- 2 files changed, 28 insertions(+), 63 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 75bafdf0cd..36d04427dd 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -609,7 +609,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CTX_ENTRY_LEGACY_SIZE 16 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 =20 -#define VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK 0xfffff +#define PASID_0 0 #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 436a30288b..2d3673db37 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -41,8 +41,6 @@ #include "trace.h" =20 /* context entry operations */ -#define VTD_CE_GET_RID2PASID(ce) \ - ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK) #define VTD_CE_GET_PASID_DIR_TABLE(ce) \ ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) #define VTD_CE_GET_PRE(ce) \ @@ -958,15 +956,12 @@ static int vtd_ce_get_pasid_entry(IntelIOMMUState *s,= VTDContextEntry *ce, VTDPASIDEntry *pe, uint32_t pasid) { dma_addr_t pasid_dir_base; - int ret =3D 0; =20 if (pasid =3D=3D PCI_NO_PASID) { - pasid =3D VTD_CE_GET_RID2PASID(ce); + pasid =3D PASID_0; } pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); - ret =3D vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe); - - return ret; + return vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe); } =20 static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, @@ -980,7 +975,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (pasid =3D=3D PCI_NO_PASID) { - pasid =3D VTD_CE_GET_RID2PASID(ce); + pasid =3D PASID_0; } pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); =20 @@ -1520,17 +1515,15 @@ static inline int vtd_context_entry_rsvd_bits_check= (IntelIOMMUState *s, return 0; } =20 -static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, - VTDContextEntry *ce) +static int vtd_ce_pasid_0_check(IntelIOMMUState *s, VTDContextEntry *ce) { VTDPASIDEntry pe; =20 /* * Make sure in Scalable Mode, a present context entry - * has valid rid2pasid setting, which includes valid - * rid2pasid field and corresponding pasid entry setting + * has valid pasid entry setting at PASID_0. */ - return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID); + return vtd_ce_get_pasid_entry(s, ce, &pe, PASID_0); } =20 /* Map a device to its corresponding domain (context-entry) */ @@ -1591,15 +1584,11 @@ static int vtd_dev_to_context_entry(IntelIOMMUState= *s, uint8_t bus_num, } } else { /* - * Check if the programming of context-entry.rid2pasid - * and corresponding pasid setting is valid, and thus - * avoids to check pasid entry fetching result in future - * helper function calling. + * Check if the programming of pasid setting of PASID_0 + * is valid, and thus avoids to check pasid entry fetching + * result in future helper function calling. */ - ret_fr =3D vtd_ce_rid2pasid_check(s, ce); - if (ret_fr) { - return ret_fr; - } + return vtd_ce_pasid_0_check(s, ce); } =20 return 0; @@ -2108,7 +2097,6 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, bool reads =3D true; bool writes =3D true; uint8_t access_flags, pgtt; - bool rid2pasid =3D (pasid =3D=3D PCI_NO_PASID) && s->root_scalable; VTDIOTLBEntry *iotlb_entry; uint64_t xlat, size; =20 @@ -2120,21 +2108,23 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, =20 vtd_iommu_lock(s); =20 - cc_entry =3D &vtd_as->context_cache_entry; + if (pasid =3D=3D PCI_NO_PASID && s->root_scalable) { + pasid =3D PASID_0; + } =20 - /* Try to fetch pte from IOTLB, we don't need RID2PASID logic */ - if (!rid2pasid) { - iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); - if (iotlb_entry) { - trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte, - iotlb_entry->domain_id); - pte =3D iotlb_entry->pte; - access_flags =3D iotlb_entry->access_flags; - page_mask =3D iotlb_entry->mask; - goto out; - } + /* Try to fetch pte from IOTLB */ + iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); + if (iotlb_entry) { + trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte, + iotlb_entry->domain_id); + pte =3D iotlb_entry->pte; + access_flags =3D iotlb_entry->access_flags; + page_mask =3D iotlb_entry->mask; + goto out; } =20 + cc_entry =3D &vtd_as->context_cache_entry; + /* Try to fetch context-entry from cache first */ if (cc_entry->context_cache_gen =3D=3D s->context_cache_gen) { trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi, @@ -2171,10 +2161,6 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, cc_entry->context_cache_gen =3D s->context_cache_gen; } =20 - if (rid2pasid) { - pasid =3D VTD_CE_GET_RID2PASID(&ce); - } - /* * We don't need to translate for pass-through context entries. * Also, let's ignore IOTLB caching as well for PT devices. @@ -2200,19 +2186,6 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, return true; } =20 - /* Try to fetch pte from IOTLB for RID2PASID slow path */ - if (rid2pasid) { - iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); - if (iotlb_entry) { - trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte, - iotlb_entry->domain_id); - pte =3D iotlb_entry->pte; - access_flags =3D iotlb_entry->access_flags; - page_mask =3D iotlb_entry->mask; - goto out; - } - } - if (s->flts && s->root_scalable) { ret_fr =3D vtd_iova_to_flpte(s, &ce, addr, is_write, &pte, &level, &reads, &writes, s->aw_bits, pasid); @@ -2475,20 +2448,14 @@ static void vtd_iotlb_page_invalidate_notify(IntelI= OMMUState *s, ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->devfn, &ce); if (!ret && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pas= id)) { - uint32_t rid2pasid =3D PCI_NO_PASID; - - if (s->root_scalable) { - rid2pasid =3D VTD_CE_GET_RID2PASID(&ce); - } - /* * In legacy mode, vtd_as->pasid =3D=3D pasid is always true. * In scalable mode, for vtd address space backing a PCI * device without pasid, needs to compare pasid with - * rid2pasid of this device. + * PASID_0 of this device. */ if (!(vtd_as->pasid =3D=3D pasid || - (vtd_as->pasid =3D=3D PCI_NO_PASID && pasid =3D=3D rid2p= asid))) { + (vtd_as->pasid =3D=3D PCI_NO_PASID && pasid =3D=3D PASID= _0))) { continue; } =20 @@ -2993,9 +2960,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->devfn, &ce) && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { - uint32_t rid2pasid =3D VTD_CE_GET_RID2PASID(&ce); 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X-CSE-ConnectionGUID: dWSOUD64TVqMC6PeIwRS+Q== X-CSE-MsgGUID: xjh4r2olQmeeYg6tYLBAxQ== X-IronPort-AV: E=McAfee;i="6800,10657,11662"; a="69087566" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69087566" X-CSE-ConnectionGUID: iGYoRePUTw6coCW+T3OVfA== X-CSE-MsgGUID: 9dcOR0EUQI68bwbRYulIdw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588701" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini Subject: [PATCH v10 03/19] intel_iommu: Update terminology to match VTD spec Date: Tue, 6 Jan 2026 01:12:45 -0500 Message-ID: <20260106061304.314546-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" VTD spec revision 3.4 released in December 2021 renamed "First-level" to "First-stage" and "Second-level" to "Second-stage". Do the same in intel_iommu code to match spec, change all existing "fl/sl/FL/SL/first level/second level/stage-1/stage-2" terminology to "fs/ss/FS/SS/first stage/second stage". Opportunistically fix a error print of "flts=3Don" with "x-flts=3Don". No functional changes intended. Suggested-by: Yi Liu Suggested-by: Eric Auger Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Yi Liu Reviewed-by: Michael S. Tsirkin --- hw/i386/intel_iommu_internal.h | 85 ++++++------ include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 247 +++++++++++++++++---------------- tests/qtest/intel-iommu-test.c | 4 +- 4 files changed, 170 insertions(+), 168 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 36d04427dd..3330298884 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -196,8 +196,8 @@ #define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid= */ #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) -#define VTD_ECAP_SLTS (1ULL << 46) -#define VTD_ECAP_FLTS (1ULL << 47) +#define VTD_ECAP_SSTS (1ULL << 46) +#define VTD_ECAP_FSTS (1ULL << 47) =20 /* CAP_REG */ /* (offset >> 4) << 24 */ @@ -211,7 +211,7 @@ #define VTD_MAMV 18ULL #define VTD_CAP_MAMV (VTD_MAMV << 48) #define VTD_CAP_PSI (1ULL << 39) -#define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) +#define VTD_CAP_SSLPS ((1ULL << 34) | (1ULL << 35)) #define VTD_CAP_DRAIN_WRITE (1ULL << 54) #define VTD_CAP_DRAIN_READ (1ULL << 55) #define VTD_CAP_FS1GP (1ULL << 56) @@ -284,7 +284,7 @@ typedef enum VTDFaultReason { VTD_FR_ADDR_BEYOND_MGAW, /* Input-address above (2^x-1) */ VTD_FR_WRITE, /* No write permission */ VTD_FR_READ, /* No read permission */ - /* Fail to access a second-level paging entry (not SL_PML4E) */ + /* Fail to access a second-stage paging entry (not SS_PML4E) */ VTD_FR_PAGING_ENTRY_INV, VTD_FR_ROOT_TABLE_INV, /* Fail to access a root-entry */ VTD_FR_CONTEXT_TABLE_INV, /* Fail to access a context-entry */ @@ -292,7 +292,8 @@ typedef enum VTDFaultReason { VTD_FR_ROOT_ENTRY_RSVD, /* Non-zero reserved field in a present context-entry */ VTD_FR_CONTEXT_ENTRY_RSVD, - /* Non-zero reserved field in a second-level paging entry with at leas= e one + /* + * Non-zero reserved field in a second-stage paging entry with at leas= e one * Read(R) and Write(W) or Execute(E) field is Set. */ VTD_FR_PAGING_ENTRY_RSVD, @@ -329,7 +330,7 @@ typedef enum VTDFaultReason { VTD_FR_PASID_ENTRY_P =3D 0x59, VTD_FR_PASID_TABLE_ENTRY_INV =3D 0x5b, /*Invalid PASID table entry */ =20 - /* Fail to access a first-level paging entry (not FS_PML4E) */ + /* Fail to access a first-stage paging entry (not FS_PML4E) */ VTD_FR_FS_PAGING_ENTRY_INV =3D 0x70, VTD_FR_FS_PAGING_ENTRY_P =3D 0x71, /* Non-zero reserved field in present first-stage paging entry */ @@ -473,23 +474,23 @@ typedef union VTDPRDesc VTDPRDesc; =20 #define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, stale_tm) \ stale_tm ? \ - (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ - (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM | VTD_SS_TM)) : \ + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM)) #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ - (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM)) #define VTD_SPTE_PAGE_L3_RSVD_MASK(aw) \ - (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM)) #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ - (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) + (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM)) =20 #define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, stale_tm) \ stale_tm ? \ - (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) := \ - (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM | VTD_SS_TM)) := \ + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM)) #define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, stale_tm) \ stale_tm ? \ - (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM))= : \ - (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM | VTD_SS_TM))= : \ + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SS_IGN_COM)) =20 /* Rsvd field masks for fpte */ #define VTD_FS_UPPER_IGNORED 0xfff0000000000000ULL @@ -596,8 +597,8 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CONTEXT_TT_MULTI_LEVEL 0 #define VTD_CONTEXT_TT_DEV_IOTLB (1ULL << 2) #define VTD_CONTEXT_TT_PASS_THROUGH (2ULL << 2) -/* Second Level Page Translation Pointer*/ -#define VTD_CONTEXT_ENTRY_SLPTPTR (~0xfffULL) +/* Second Stage Page Translation Pointer*/ +#define VTD_CONTEXT_ENTRY_SSPTPTR (~0xfffULL) #define VTD_CONTEXT_ENTRY_RSVD_LO(aw) (0xff0ULL | ~VTD_HAW_MASK(aw)) /* hi */ #define VTD_CONTEXT_ENTRY_AW 7ULL /* Adjusted guest-address-width */ @@ -635,37 +636,37 @@ typedef struct VTDPASIDCacheInfo { /* PASID Granular Translation Type Mask */ #define VTD_PASID_ENTRY_P 1ULL #define VTD_SM_PASID_ENTRY_PGTT (7ULL << 6) -#define VTD_SM_PASID_ENTRY_FLT (1ULL << 6) -#define VTD_SM_PASID_ENTRY_SLT (2ULL << 6) +#define VTD_SM_PASID_ENTRY_FST (1ULL << 6) +#define VTD_SM_PASID_ENTRY_SST (2ULL << 6) #define VTD_SM_PASID_ENTRY_NESTED (3ULL << 6) #define VTD_SM_PASID_ENTRY_PT (4ULL << 6) =20 #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-widt= h */ #define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK) =20 -#define VTD_SM_PASID_ENTRY_FLPM 3ULL -#define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) - -/* First Level Paging Structure */ -/* Masks for First Level Paging Entry */ -#define VTD_FL_P 1ULL -#define VTD_FL_RW (1ULL << 1) -#define VTD_FL_US (1ULL << 2) -#define VTD_FL_A (1ULL << 5) -#define VTD_FL_D (1ULL << 6) - -/* Second Level Page Translation Pointer*/ -#define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL) - -/* Second Level Paging Structure */ -/* Masks for Second Level Paging Entry */ -#define VTD_SL_RW_MASK 3ULL -#define VTD_SL_R 1ULL -#define VTD_SL_W (1ULL << 1) -#define VTD_SL_IGN_COM 0xbff0000000000000ULL -#define VTD_SL_TM (1ULL << 62) - -/* Common for both First Level and Second Level */ +#define VTD_SM_PASID_ENTRY_FSPM 3ULL +#define VTD_SM_PASID_ENTRY_FSPTPTR (~0xfffULL) + +/* First Stage Paging Structure */ +/* Masks for First Stage Paging Entry */ +#define VTD_FS_P 1ULL +#define VTD_FS_RW (1ULL << 1) +#define VTD_FS_US (1ULL << 2) +#define VTD_FS_A (1ULL << 5) +#define VTD_FS_D (1ULL << 6) + +/* Second Stage Page Translation Pointer*/ +#define VTD_SM_PASID_ENTRY_SSPTPTR (~0xfffULL) + +/* Second Stage Paging Structure */ +/* Masks for Second Stage Paging Entry */ +#define VTD_SS_RW_MASK 3ULL +#define VTD_SS_R 1ULL +#define VTD_SS_W (1ULL << 1) +#define VTD_SS_IGN_COM 0xbff0000000000000ULL +#define VTD_SS_TM (1ULL << 62) + +/* Common for both First Stage and Second Stage */ #define VTD_PML4_LEVEL 4 #define VTD_PDP_LEVEL 3 #define VTD_PD_LEVEL 2 diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index ca7f7bb661..0b7832d25d 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -271,7 +271,7 @@ struct IntelIOMMUState { =20 bool caching_mode; /* RO - is cap CM enabled? */ bool scalable_mode; /* RO - is Scalable Mode supported? */ - bool flts; /* RO - is stage-1 translation support= ed? */ + bool fsts; /* RO - is first stage translation sup= ported? */ bool snoop_control; /* RO - is SNP filed supported? */ =20 dma_addr_t root; /* Current root table pointer */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2d3673db37..7bec53a587 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -48,9 +48,9 @@ =20 /* pe operations */ #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) -#define VTD_PE_GET_FL_LEVEL(pe) \ - (4 + (((pe)->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM)) -#define VTD_PE_GET_SL_LEVEL(pe) \ +#define VTD_PE_GET_FS_LEVEL(pe) \ + (4 + (((pe)->val[2] >> 2) & VTD_SM_PASID_ENTRY_FSPM)) +#define VTD_PE_GET_SS_LEVEL(pe) \ (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) =20 /* @@ -327,7 +327,7 @@ static gboolean vtd_hash_remove_by_page(gpointer key, g= pointer value, * nested (PGTT=3D011b) mapping associated with specified domain-id are * invalidated. Nested isn't supported yet, so only need to check 001b. */ - if (entry->pgtt =3D=3D VTD_SM_PASID_ENTRY_FLT) { + if (entry->pgtt =3D=3D VTD_SM_PASID_ENTRY_FST) { return true; } =20 @@ -348,7 +348,7 @@ static gboolean vtd_hash_remove_by_page_piotlb(gpointer= key, gpointer value, * or pass-through (PGTT=3D100b) mappings. Nested isn't supported yet, * so only need to check first-stage (PGTT=3D001b) mappings. */ - if (entry->pgtt !=3D VTD_SM_PASID_ENTRY_FLT) { + if (entry->pgtt !=3D VTD_SM_PASID_ENTRY_FST) { return false; } =20 @@ -756,9 +756,9 @@ static int vtd_get_context_entry_from_root(IntelIOMMUSt= ate *s, return 0; } =20 -static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce) +static inline dma_addr_t vtd_ce_get_sspt_base(VTDContextEntry *ce) { - return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR; + return ce->lo & VTD_CONTEXT_ENTRY_SSPTPTR; } =20 static inline uint64_t vtd_get_pte_addr(uint64_t pte, uint8_t aw) @@ -799,13 +799,13 @@ static inline uint32_t vtd_iova_level_offset(uint64_t= iova, uint32_t level) } =20 /* Check Capability Register to see if the @level of page-table is support= ed */ -static inline bool vtd_is_sl_level_supported(IntelIOMMUState *s, uint32_t = level) +static inline bool vtd_is_ss_level_supported(IntelIOMMUState *s, uint32_t = level) { return VTD_CAP_SAGAW_MASK & s->cap & (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT)); } =20 -static inline bool vtd_is_fl_level_supported(IntelIOMMUState *s, uint32_t = level) +static inline bool vtd_is_fs_level_supported(IntelIOMMUState *s, uint32_t = level) { return level =3D=3D VTD_PML4_LEVEL; } @@ -814,10 +814,10 @@ static inline bool vtd_is_fl_level_supported(IntelIOM= MUState *s, uint32_t level) static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe) { switch (VTD_PE_GET_TYPE(pe)) { - case VTD_SM_PASID_ENTRY_FLT: - return !!(s->ecap & VTD_ECAP_FLTS); - case VTD_SM_PASID_ENTRY_SLT: - return !!(s->ecap & VTD_ECAP_SLTS); + case VTD_SM_PASID_ENTRY_FST: + return !!(s->ecap & VTD_ECAP_FSTS); + case VTD_SM_PASID_ENTRY_SST: + return !!(s->ecap & VTD_ECAP_SSTS); case VTD_SM_PASID_ENTRY_NESTED: /* Not support NESTED page table type yet */ return false; @@ -889,13 +889,13 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUS= tate *s, } =20 pgtt =3D VTD_PE_GET_TYPE(pe); - if (pgtt =3D=3D VTD_SM_PASID_ENTRY_SLT && - !vtd_is_sl_level_supported(s, VTD_PE_GET_SL_LEVEL(pe))) { + if (pgtt =3D=3D VTD_SM_PASID_ENTRY_SST && + !vtd_is_ss_level_supported(s, VTD_PE_GET_SS_LEVEL(pe))) { return -VTD_FR_PASID_TABLE_ENTRY_INV; } =20 - if (pgtt =3D=3D VTD_SM_PASID_ENTRY_FLT && - !vtd_is_fl_level_supported(s, VTD_PE_GET_FL_LEVEL(pe))) { + if (pgtt =3D=3D VTD_SM_PASID_ENTRY_FST && + !vtd_is_fs_level_supported(s, VTD_PE_GET_FS_LEVEL(pe))) { return -VTD_FR_PASID_TABLE_ENTRY_INV; } =20 @@ -1013,7 +1013,8 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, return 0; } =20 -/* Get the page-table level that hardware should use for the second-level +/* + * Get the page-table level that hardware should use for the second-stage * page-table walk from the Address Width field of context-entry. */ static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce) @@ -1029,10 +1030,10 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState = *s, =20 if (s->root_scalable) { vtd_ce_get_pasid_entry(s, ce, &pe, pasid); - if (s->flts) { - return VTD_PE_GET_FL_LEVEL(&pe); + if (s->fsts) { + return VTD_PE_GET_FS_LEVEL(&pe); } else { - return VTD_PE_GET_SL_LEVEL(&pe); + return VTD_PE_GET_SS_LEVEL(&pe); } } =20 @@ -1101,7 +1102,7 @@ static inline uint64_t vtd_iova_limit(IntelIOMMUState= *s, } =20 /* Return true if IOVA passes range check, otherwise false. */ -static inline bool vtd_iova_sl_range_check(IntelIOMMUState *s, +static inline bool vtd_iova_ss_range_check(IntelIOMMUState *s, uint64_t iova, VTDContextEntry = *ce, uint8_t aw, uint32_t pasid) { @@ -1120,14 +1121,14 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMM= UState *s, =20 if (s->root_scalable) { vtd_ce_get_pasid_entry(s, ce, &pe, pasid); - if (s->flts) { - return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; + if (s->fsts) { + return pe.val[2] & VTD_SM_PASID_ENTRY_FSPTPTR; } else { - return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR; + return pe.val[0] & VTD_SM_PASID_ENTRY_SSPTPTR; } } =20 - return vtd_ce_get_slpt_base(ce); + return vtd_ce_get_sspt_base(ce); } =20 /* @@ -1142,13 +1143,13 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMM= UState *s, static uint64_t vtd_spte_rsvd[VTD_SPTE_RSVD_LEN]; static uint64_t vtd_spte_rsvd_large[VTD_SPTE_RSVD_LEN]; =20 -static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) +static bool vtd_sspte_nonzero_rsvd(uint64_t sspte, uint32_t level) { uint64_t rsvd_mask; =20 /* * We should have caught a guest-mis-programmed level earlier, - * via vtd_is_sl_level_supported. + * via vtd_is_ss_level_supported. */ assert(level < VTD_SPTE_RSVD_LEN); /* @@ -1158,46 +1159,47 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, = uint32_t level) assert(level); =20 if ((level =3D=3D VTD_PD_LEVEL || level =3D=3D VTD_PDP_LEVEL) && - (slpte & VTD_PT_PAGE_SIZE_MASK)) { + (sspte & VTD_PT_PAGE_SIZE_MASK)) { /* large page */ rsvd_mask =3D vtd_spte_rsvd_large[level]; } else { rsvd_mask =3D vtd_spte_rsvd[level]; } =20 - return slpte & rsvd_mask; + return sspte & rsvd_mask; } =20 -/* Given the @iova, get relevant @slptep. @slpte_level will be the last le= vel +/* + * Given the @iova, get relevant @ssptep. @sspte_level will be the last le= vel * of the translation, can be used for deciding the size of large page. */ -static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce, +static int vtd_iova_to_sspte(IntelIOMMUState *s, VTDContextEntry *ce, uint64_t iova, bool is_write, - uint64_t *slptep, uint32_t *slpte_level, + uint64_t *ssptep, uint32_t *sspte_level, bool *reads, bool *writes, uint8_t aw_bits, uint32_t pasid) { dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); uint32_t level =3D vtd_get_iova_level(s, ce, pasid); uint32_t offset; - uint64_t slpte; + uint64_t sspte; uint64_t access_right_check; =20 - if (!vtd_iova_sl_range_check(s, iova, ce, aw_bits, pasid)) { + if (!vtd_iova_ss_range_check(s, iova, ce, aw_bits, pasid)) { error_report_once("%s: detected IOVA overflow (iova=3D0x%" PRIx64 = "," "pasid=3D0x%" PRIx32 ")", __func__, iova, pasid); return -VTD_FR_ADDR_BEYOND_MGAW; } =20 /* FIXME: what is the Atomics request here? */ - access_right_check =3D is_write ? VTD_SL_W : VTD_SL_R; + access_right_check =3D is_write ? VTD_SS_W : VTD_SS_R; =20 while (true) { offset =3D vtd_iova_level_offset(iova, level); - slpte =3D vtd_get_pte(addr, offset); + sspte =3D vtd_get_pte(addr, offset); =20 - if (slpte =3D=3D (uint64_t)-1) { - error_report_once("%s: detected read error on DMAR slpte " + if (sspte =3D=3D (uint64_t)-1) { + error_report_once("%s: detected read error on DMAR sspte " "(iova=3D0x%" PRIx64 ", pasid=3D0x%" PRIx32 = ")", __func__, iova, pasid); if (level =3D=3D vtd_get_iova_level(s, ce, pasid)) { @@ -1207,30 +1209,30 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VT= DContextEntry *ce, return -VTD_FR_PAGING_ENTRY_INV; } } - *reads =3D (*reads) && (slpte & VTD_SL_R); - *writes =3D (*writes) && (slpte & VTD_SL_W); - if (!(slpte & access_right_check)) { - error_report_once("%s: detected slpte permission error " + *reads =3D (*reads) && (sspte & VTD_SS_R); + *writes =3D (*writes) && (sspte & VTD_SS_W); + if (!(sspte & access_right_check)) { + error_report_once("%s: detected sspte permission error " "(iova=3D0x%" PRIx64 ", level=3D0x%" PRIx32 = ", " - "slpte=3D0x%" PRIx64 ", write=3D%d, pasid=3D= 0x%" + "sspte=3D0x%" PRIx64 ", write=3D%d, pasid=3D= 0x%" PRIx32 ")", __func__, iova, level, - slpte, is_write, pasid); + sspte, is_write, pasid); return is_write ? -VTD_FR_WRITE : -VTD_FR_READ; } - if (vtd_slpte_nonzero_rsvd(slpte, level)) { + if (vtd_sspte_nonzero_rsvd(sspte, level)) { error_report_once("%s: detected splte reserve non-zero " "iova=3D0x%" PRIx64 ", level=3D0x%" PRIx32 - "slpte=3D0x%" PRIx64 ", pasid=3D0x%" PRIX32 = ")", - __func__, iova, level, slpte, pasid); + "sspte=3D0x%" PRIx64 ", pasid=3D0x%" PRIX32 = ")", + __func__, iova, level, sspte, pasid); return -VTD_FR_PAGING_ENTRY_RSVD; } =20 - if (vtd_is_last_pte(slpte, level)) { - *slptep =3D slpte; - *slpte_level =3D level; + if (vtd_is_last_pte(sspte, level)) { + *ssptep =3D sspte; + *sspte_level =3D level; break; } - addr =3D vtd_get_pte_addr(slpte, aw_bits); + addr =3D vtd_get_pte_addr(sspte, aw_bits); level--; } =20 @@ -1356,7 +1358,7 @@ static int vtd_page_walk_level(dma_addr_t addr, uint6= 4_t start, { bool read_cur, write_cur, entry_valid; uint32_t offset; - uint64_t slpte; + uint64_t sspte; uint64_t subpage_size, subpage_mask; IOMMUTLBEvent event; uint64_t iova =3D start; @@ -1372,21 +1374,21 @@ static int vtd_page_walk_level(dma_addr_t addr, uin= t64_t start, iova_next =3D (iova & subpage_mask) + subpage_size; =20 offset =3D vtd_iova_level_offset(iova, level); - slpte =3D vtd_get_pte(addr, offset); + sspte =3D vtd_get_pte(addr, offset); =20 - if (slpte =3D=3D (uint64_t)-1) { + if (sspte =3D=3D (uint64_t)-1) { trace_vtd_page_walk_skip_read(iova, iova_next); goto next; } =20 - if (vtd_slpte_nonzero_rsvd(slpte, level)) { + if (vtd_sspte_nonzero_rsvd(sspte, level)) { trace_vtd_page_walk_skip_reserve(iova, iova_next); goto next; } =20 /* Permissions are stacked with parents' */ - read_cur =3D read && (slpte & VTD_SL_R); - write_cur =3D write && (slpte & VTD_SL_W); + read_cur =3D read && (sspte & VTD_SS_R); + write_cur =3D write && (sspte & VTD_SS_W); =20 /* * As long as we have either read/write permission, this is a @@ -1395,12 +1397,12 @@ static int vtd_page_walk_level(dma_addr_t addr, uin= t64_t start, */ entry_valid =3D read_cur | write_cur; =20 - if (!vtd_is_last_pte(slpte, level) && entry_valid) { + if (!vtd_is_last_pte(sspte, level) && entry_valid) { /* * This is a valid PDE (or even bigger than PDE). We need * to walk one further level. */ - ret =3D vtd_page_walk_level(vtd_get_pte_addr(slpte, info->aw), + ret =3D vtd_page_walk_level(vtd_get_pte_addr(sspte, info->aw), iova, MIN(iova_next, end), level - 1, read_cur, write_cur, info); } else { @@ -1417,7 +1419,7 @@ static int vtd_page_walk_level(dma_addr_t addr, uint6= 4_t start, event.entry.perm =3D IOMMU_ACCESS_FLAG(read_cur, write_cur); event.entry.addr_mask =3D ~subpage_mask; /* NOTE: this is only meaningful if entry_valid =3D=3D true */ - event.entry.translated_addr =3D vtd_get_pte_addr(slpte, info->= aw); + event.entry.translated_addr =3D vtd_get_pte_addr(sspte, info->= aw); event.type =3D event.entry.perm ? IOMMU_NOTIFIER_MAP : IOMMU_NOTIFIER_UNMAP; ret =3D vtd_page_walk_one(&event, info); @@ -1451,11 +1453,11 @@ static int vtd_page_walk(IntelIOMMUState *s, VTDCon= textEntry *ce, dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); uint32_t level =3D vtd_get_iova_level(s, ce, pasid); =20 - if (!vtd_iova_sl_range_check(s, start, ce, info->aw, pasid)) { + if (!vtd_iova_ss_range_check(s, start, ce, info->aw, pasid)) { return -VTD_FR_ADDR_BEYOND_MGAW; } =20 - if (!vtd_iova_sl_range_check(s, end, ce, info->aw, pasid)) { + if (!vtd_iova_ss_range_check(s, end, ce, info->aw, pasid)) { /* Fix end so that it reaches the maximum */ end =3D vtd_iova_limit(s, ce, info->aw, pasid); } @@ -1568,7 +1570,7 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *= s, uint8_t bus_num, =20 /* Check if the programming of context-entry is valid */ if (!s->root_scalable && - !vtd_is_sl_level_supported(s, vtd_ce_get_level(ce))) { + !vtd_is_ss_level_supported(s, vtd_ce_get_level(ce))) { error_report_once("%s: invalid context entry: hi=3D%"PRIx64 ", lo=3D%"PRIx64" (level %d not supported)", __func__, ce->hi, ce->lo, @@ -1672,10 +1674,9 @@ static int vtd_address_space_sync(VTDAddressSpace *v= td_as) } =20 /* - * Check if specific device is configured to bypass address - * translation for DMA requests. In Scalable Mode, bypass - * 1st-level translation or 2nd-level translation, it depends - * on PGTT setting. + * Check if specific device is configured to bypass address translation + * for DMA requests. In Scalable Mode, bypass first stage translation + * or second stage translation, it depends on PGTT setting. */ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VTDContextEntry *ce, uint32_t pasid) @@ -1913,13 +1914,13 @@ out: static uint64_t vtd_fpte_rsvd[VTD_FPTE_RSVD_LEN]; static uint64_t vtd_fpte_rsvd_large[VTD_FPTE_RSVD_LEN]; =20 -static bool vtd_flpte_nonzero_rsvd(uint64_t flpte, uint32_t level) +static bool vtd_fspte_nonzero_rsvd(uint64_t fspte, uint32_t level) { uint64_t rsvd_mask; =20 /* * We should have caught a guest-mis-programmed level earlier, - * via vtd_is_fl_level_supported. + * via vtd_is_fs_level_supported. */ assert(level < VTD_FPTE_RSVD_LEN); /* @@ -1929,23 +1930,23 @@ static bool vtd_flpte_nonzero_rsvd(uint64_t flpte, = uint32_t level) assert(level); =20 if ((level =3D=3D VTD_PD_LEVEL || level =3D=3D VTD_PDP_LEVEL) && - (flpte & VTD_PT_PAGE_SIZE_MASK)) { + (fspte & VTD_PT_PAGE_SIZE_MASK)) { /* large page */ rsvd_mask =3D vtd_fpte_rsvd_large[level]; } else { rsvd_mask =3D vtd_fpte_rsvd[level]; } =20 - return flpte & rsvd_mask; + return fspte & rsvd_mask; } =20 -static inline bool vtd_flpte_present(uint64_t flpte) +static inline bool vtd_fspte_present(uint64_t fspte) { - return !!(flpte & VTD_FL_P); + return !!(fspte & VTD_FS_P); } =20 /* Return true if IOVA is canonical, otherwise false. */ -static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova, +static bool vtd_iova_fs_check_canonical(IntelIOMMUState *s, uint64_t iova, VTDContextEntry *ce, uint32_t pasi= d) { uint64_t iova_limit =3D vtd_iova_limit(s, ce, s->aw_bits, pasid); @@ -1975,32 +1976,32 @@ static MemTxResult vtd_set_flag_in_pte(dma_addr_t b= ase_addr, uint32_t index, } =20 /* - * Given the @iova, get relevant @flptep. @flpte_level will be the last le= vel + * Given the @iova, get relevant @fsptep. @fspte_level will be the last le= vel * of the translation, can be used for deciding the size of large page. */ -static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce, +static int vtd_iova_to_fspte(IntelIOMMUState *s, VTDContextEntry *ce, uint64_t iova, bool is_write, - uint64_t *flptep, uint32_t *flpte_level, + uint64_t *fsptep, uint32_t *fspte_level, bool *reads, bool *writes, uint8_t aw_bits, uint32_t pasid) { dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); uint32_t offset; - uint64_t flpte, flag_ad =3D VTD_FL_A; - *flpte_level =3D vtd_get_iova_level(s, ce, pasid); + uint64_t fspte, flag_ad =3D VTD_FS_A; + *fspte_level =3D vtd_get_iova_level(s, ce, pasid); =20 - if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) { + if (!vtd_iova_fs_check_canonical(s, iova, ce, pasid)) { error_report_once("%s: detected non canonical IOVA (iova=3D0x%" PR= Ix64 "," "pasid=3D0x%" PRIx32 ")", __func__, iova, pasid); return -VTD_FR_FS_NON_CANONICAL; } =20 while (true) { - offset =3D vtd_iova_level_offset(iova, *flpte_level); - flpte =3D vtd_get_pte(addr, offset); + offset =3D vtd_iova_level_offset(iova, *fspte_level); + fspte =3D vtd_get_pte(addr, offset); =20 - if (flpte =3D=3D (uint64_t)-1) { - if (*flpte_level =3D=3D vtd_get_iova_level(s, ce, pasid)) { + if (fspte =3D=3D (uint64_t)-1) { + if (*fspte_level =3D=3D vtd_get_iova_level(s, ce, pasid)) { /* Invalid programming of pasid-entry */ return -VTD_FR_PASID_ENTRY_FSPTPTR_INV; } else { @@ -2008,47 +2009,47 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VT= DContextEntry *ce, } } =20 - if (!vtd_flpte_present(flpte)) { + if (!vtd_fspte_present(fspte)) { *reads =3D false; *writes =3D false; return -VTD_FR_FS_PAGING_ENTRY_P; } =20 /* No emulated device supports supervisor privilege request yet */ - if (!(flpte & VTD_FL_US)) { + if (!(fspte & VTD_FS_US)) { *reads =3D false; *writes =3D false; return -VTD_FR_FS_PAGING_ENTRY_US; } =20 *reads =3D true; - *writes =3D (*writes) && (flpte & VTD_FL_RW); - if (is_write && !(flpte & VTD_FL_RW)) { + *writes =3D (*writes) && (fspte & VTD_FS_RW); + if (is_write && !(fspte & VTD_FS_RW)) { return -VTD_FR_SM_WRITE; } - if (vtd_flpte_nonzero_rsvd(flpte, *flpte_level)) { - error_report_once("%s: detected flpte reserved non-zero " + if (vtd_fspte_nonzero_rsvd(fspte, *fspte_level)) { + error_report_once("%s: detected fspte reserved non-zero " "iova=3D0x%" PRIx64 ", level=3D0x%" PRIx32 - "flpte=3D0x%" PRIx64 ", pasid=3D0x%" PRIX32 = ")", - __func__, iova, *flpte_level, flpte, pasid); + "fspte=3D0x%" PRIx64 ", pasid=3D0x%" PRIX32 = ")", + __func__, iova, *fspte_level, fspte, pasid); return -VTD_FR_FS_PAGING_ENTRY_RSVD; } =20 - if (vtd_is_last_pte(flpte, *flpte_level) && is_write) { - flag_ad |=3D VTD_FL_D; + if (vtd_is_last_pte(fspte, *fspte_level) && is_write) { + flag_ad |=3D VTD_FS_D; } =20 - if (vtd_set_flag_in_pte(addr, offset, flpte, flag_ad) !=3D MEMTX_O= K) { + if (vtd_set_flag_in_pte(addr, offset, fspte, flag_ad) !=3D MEMTX_O= K) { return -VTD_FR_FS_BIT_UPDATE_FAILED; } =20 - if (vtd_is_last_pte(flpte, *flpte_level)) { - *flptep =3D flpte; + if (vtd_is_last_pte(fspte, *fspte_level)) { + *fsptep =3D fspte; return 0; } =20 - addr =3D vtd_get_pte_addr(flpte, aw_bits); - (*flpte_level)--; + addr =3D vtd_get_pte_addr(fspte, aw_bits); + (*fspte_level)--; } } =20 @@ -2186,14 +2187,14 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, return true; } =20 - if (s->flts && s->root_scalable) { - ret_fr =3D vtd_iova_to_flpte(s, &ce, addr, is_write, &pte, &level, + if (s->fsts && s->root_scalable) { + ret_fr =3D vtd_iova_to_fspte(s, &ce, addr, is_write, &pte, &level, &reads, &writes, s->aw_bits, pasid); - pgtt =3D VTD_SM_PASID_ENTRY_FLT; + pgtt =3D VTD_SM_PASID_ENTRY_FST; } else { - ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level, + ret_fr =3D vtd_iova_to_sspte(s, &ce, addr, is_write, &pte, &level, &reads, &writes, s->aw_bits, pasid); - pgtt =3D VTD_SM_PASID_ENTRY_SLT; + pgtt =3D VTD_SM_PASID_ENTRY_SST; } if (!ret_fr) { xlat =3D vtd_get_pte_addr(pte, s->aw_bits); @@ -2461,13 +2462,13 @@ static void vtd_iotlb_page_invalidate_notify(IntelI= OMMUState *s, =20 if (vtd_as_has_map_notifier(vtd_as)) { /* - * When stage-1 translation is off, as long as we have MAP + * When first stage translation is off, as long as we have= MAP * notifications registered in any of our IOMMU notifiers, * we need to sync the shadow page table. Otherwise VFIO * device attaches to nested page table instead of shadow * page table, so no need to sync. */ - if (!s->flts || !s->root_scalable) { + if (!s->fsts || !s->root_scalable) { vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, si= ze); } } else { @@ -2965,7 +2966,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, continue; } =20 - if (!s->flts || !vtd_as_has_map_notifier(vtd_as)) { + if (!s->fsts || !vtd_as_has_map_notifier(vtd_as)) { vtd_address_space_sync(vtd_as); } } @@ -4060,7 +4061,7 @@ static const Property vtd_properties[] =3D { VTD_HOST_ADDRESS_WIDTH), DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FA= LSE), - DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, flts, FALSE), + DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, fsts, FALSE), DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, fals= e), DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false), DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), @@ -4585,12 +4586,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, Host= IOMMUDevice *hiod, return false; } =20 - if (!s->flts) { - /* All checks requested by VTD stage-2 translation pass */ + if (!s->fsts) { + /* All checks requested by VTD second stage translation pass */ return true; } =20 - error_setg(errp, "host device is uncompatible with stage-1 translation= "); + error_setg(errp, + "host device is uncompatible with first stage translation"); return false; } =20 @@ -4782,7 +4784,7 @@ static void vtd_cap_init(IntelIOMMUState *s) X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); =20 s->cap =3D VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | - VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | + VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SSLPS | VTD_CAP_ESRTPS | VTD_CAP_MGAW(s->aw_bits); if (s->dma_drain) { s->cap |=3D VTD_CAP_DRAIN; @@ -4818,13 +4820,13 @@ static void vtd_cap_init(IntelIOMMUState *s) } =20 /* TODO: read cap/ecap from host to decide which cap to be exposed. */ - if (s->flts) { - s->ecap |=3D VTD_ECAP_SMTS | VTD_ECAP_FLTS; + if (s->fsts) { + s->ecap |=3D VTD_ECAP_SMTS | VTD_ECAP_FSTS; if (s->fs1gp) { s->cap |=3D VTD_CAP_FS1GP; } } else if (s->scalable_mode) { - s->ecap |=3D VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS; + s->ecap |=3D VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SSTS; } =20 if (s->snoop_control) { @@ -5132,7 +5134,7 @@ static int vtd_pri_perform_implicit_invalidation(VTDA= ddressSpace *vtd_as, domain_id =3D VTD_SM_PASID_ENTRY_DID(pe.val[1]); ret =3D 0; switch (pgtt) { - case VTD_SM_PASID_ENTRY_FLT: + case VTD_SM_PASID_ENTRY_FST: vtd_piotlb_page_invalidate(s, domain_id, vtd_as->pasid, addr, 0); break; /* Room for other pgtt values */ @@ -5334,12 +5336,12 @@ static bool vtd_decide_config(IntelIOMMUState *s, E= rror **errp) } } =20 - if (!s->scalable_mode && s->flts) { + if (!s->scalable_mode && s->fsts) { error_setg(errp, "x-flts is only available in scalable mode"); return false; } =20 - if (!s->flts && s->aw_bits !=3D VTD_HOST_AW_39BIT && + if (!s->fsts && s->aw_bits !=3D VTD_HOST_AW_39BIT && s->aw_bits !=3D VTD_HOST_AW_48BIT) { error_setg(errp, "%s: supported values for aw-bits are: %d, %d", s->scalable_mode ? "Scalable mode(flts=3Doff)" : "Legac= y mode", @@ -5347,10 +5349,9 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) return false; } =20 - if (s->flts && s->aw_bits !=3D VTD_HOST_AW_48BIT) { - error_setg(errp, - "Scalable mode(flts=3Don): supported value for aw-bits = is: %d", - VTD_HOST_AW_48BIT); + if (s->fsts && s->aw_bits !=3D VTD_HOST_AW_48BIT) { + error_setg(errp, "Scalable mode(x-flts=3Don): supported value for " + "aw-bits is: %d", VTD_HOST_AW_48BIT); return false; } =20 diff --git a/tests/qtest/intel-iommu-test.c b/tests/qtest/intel-iommu-test.c index c521b3796e..e5cc6acaf0 100644 --- a/tests/qtest/intel-iommu-test.c +++ b/tests/qtest/intel-iommu-test.c @@ -13,9 +13,9 @@ #include "hw/i386/intel_iommu_internal.h" =20 #define CAP_STAGE_1_FIXED1 (VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | \ - VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS) + VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SSLPS) #define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO |= \ - VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FLT= S) + VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FST= S) =20 static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset) { --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="69087576" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69087576" X-CSE-ConnectionGUID: jXRoJt60T1qvelmjp58S1w== X-CSE-MsgGUID: 7RYMNMV4Tt+VD9qp5SR60Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588714" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 04/19] hw/pci: Export pci_device_get_iommu_bus_devfn() and return bool Date: Tue, 6 Jan 2026 01:12:46 -0500 Message-ID: <20260106061304.314546-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Returns true if PCI device is aliased or false otherwise. This will be used in following patch to determine if a PCI device is under a PCI bridge. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Yi Liu Reviewed-by: Michael S. Tsirkin --- include/hw/pci/pci.h | 2 ++ hw/pci/pci.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index b72e484500..b22d350ba2 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -637,6 +637,8 @@ typedef struct PCIIOMMUOps { bool is_write); } PCIIOMMUOps; =20 +bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, + PCIBus **aliased_bus, int *aliased_dev= fn); AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, Error **errp); diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 5996229c81..0d4cf906f0 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2869,20 +2869,21 @@ static void pci_device_class_base_init(ObjectClass = *klass, const void *data) * For call sites which don't need aliased BDF, passing NULL to * aliased_[bus|devfn] is allowed. * + * Returns true if PCI device RID is aliased or false otherwise. + * * @piommu_bus: return root #PCIBus backed by an IOMMU for the PCI device. * * @aliased_bus: return aliased #PCIBus of the PCI device, optional. * * @aliased_devfn: return aliased devfn of the PCI device, optional. */ -static void pci_device_get_iommu_bus_devfn(PCIDevice *dev, - PCIBus **piommu_bus, - PCIBus **aliased_bus, - int *aliased_devfn) +bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, + PCIBus **aliased_bus, int *aliased_dev= fn) { PCIBus *bus =3D pci_get_bus(dev); PCIBus *iommu_bus =3D bus; int devfn =3D dev->devfn; + bool aliased =3D false; =20 while (iommu_bus && !iommu_bus->iommu_ops && iommu_bus->parent_dev) { PCIBus *parent_bus =3D pci_get_bus(iommu_bus->parent_dev); @@ -2919,6 +2920,7 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice = *dev, devfn =3D parent->devfn; bus =3D parent_bus; } + aliased =3D true; } =20 /* @@ -2953,6 +2955,8 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice = *dev, if (aliased_devfn) { *aliased_devfn =3D devfn; } + + return aliased; } =20 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1767680059; cv=none; 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d="scan'208";a="202588731" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 05/19] hw/pci: Introduce pci_device_get_viommu_flags() Date: Tue, 6 Jan 2026 01:12:47 -0500 Message-ID: <20260106061304.314546-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1767680061559158500 Introduce a new PCIIOMMUOps optional callback, get_viommu_flags() which allows to retrieve flags exposed by a vIOMMU. The first planned vIOMMU device flag is VIOMMU_FLAG_WANT_NESTING_PARENT that advertises the support of HW nested stage translation scheme and wants other sub-system like VFIO's cooperation to create nesting parent HWPT. pci_device_get_viommu_flags() is a wrapper that can be called on a PCI device potentially protected by a vIOMMU. get_viommu_flags() is designed to return 64bit bitmap of purely vIOMMU flags which are only determined by user's configuration, no host capabilities involved. Reasons are: 1. host may has heterogeneous IOMMUs, each with different capabilities 2. this is migration friendly, return value is consistent between source and target. Note that this op will be invoked at the attach_device() stage, at which point host IOMMU capabilities are not yet forwarded to the vIOMMU through the set_iommu_device() callback that will be after the attach_device(). See below sequence: vfio_device_attach(): iommufd_cdev_attach(): pci_device_get_viommu_flags() for HW nesting cap create a nesting parent HWPT attach device to the HWPT vfio_device_hiod_create_and_realize() creating hiod ... pci_device_set_iommu_device(hiod) Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Reviewed-by: Yi Liu Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Michael S. Tsirkin --- MAINTAINERS | 1 + include/hw/core/iommu.h | 25 +++++++++++++++++++++++++ include/hw/pci/pci.h | 22 ++++++++++++++++++++++ hw/pci/pci.c | 11 +++++++++++ 4 files changed, 59 insertions(+) create mode 100644 include/hw/core/iommu.h diff --git a/MAINTAINERS b/MAINTAINERS index cca9b57c02..3ff0d3a4da 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2346,6 +2346,7 @@ F: include/system/iommufd.h F: backends/host_iommu_device.c F: include/system/host_iommu_device.h F: include/qemu/chardev_open.h +F: include/hw/core/iommu.h F: util/chardev_open.c F: docs/devel/vfio-iommufd.rst =20 diff --git a/include/hw/core/iommu.h b/include/hw/core/iommu.h new file mode 100644 index 0000000000..9b8bb94fc2 --- /dev/null +++ b/include/hw/core/iommu.h @@ -0,0 +1,25 @@ +/* + * General vIOMMU flags + * + * Copyright (C) 2025 Intel Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_IOMMU_H +#define HW_IOMMU_H + +#include "qemu/bitops.h" + +/* + * Theoretical vIOMMU flags. Only determined by the vIOMMU device properti= es and + * independent on the actual host IOMMU capabilities they may depend on. E= ach + * flag can be an expectation or request to other sub-system or just a pure + * vIOMMU capability. vIOMMU can choose which flags to expose. + */ +enum viommu_flags { + /* vIOMMU needs nesting parent HWPT to create nested HWPT */ + VIOMMU_FLAG_WANT_NESTING_PARENT =3D BIT_ULL(0), +}; + +#endif /* HW_IOMMU_H */ diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index b22d350ba2..868817cc05 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -462,6 +462,18 @@ typedef struct PCIIOMMUOps { * @devfn: device and function number of the PCI device. */ void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); + /** + * @get_viommu_flags: get vIOMMU flags + * + * Optional callback, if not implemented, then vIOMMU doesn't support + * exposing flags to other sub-system, e.g., VFIO. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * Returns: bitmap with each bit representing a vIOMMU flag defined in + * enum viommu_flags. + */ + uint64_t (*get_viommu_flags)(void *opaque); /** * @get_iotlb_info: get properties required to initialize a device IOT= LB. * @@ -644,6 +656,16 @@ bool pci_device_set_iommu_device(PCIDevice *dev, HostI= OMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); =20 +/** + * pci_device_get_viommu_flags: get vIOMMU flags. + * + * Returns: bitmap with each bit representing a vIOMMU flag defined in + * enum viommu_flags. Or 0 if vIOMMU doesn't report any. + * + * @dev: PCI device pointer. + */ +uint64_t pci_device_get_viommu_flags(PCIDevice *dev); + /** * pci_iommu_get_iotlb_info: get properties required to initialize a * device IOTLB. diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 0d4cf906f0..a136e772a3 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -3021,6 +3021,17 @@ void pci_device_unset_iommu_device(PCIDevice *dev) } } =20 +uint64_t pci_device_get_viommu_flags(PCIDevice *dev) +{ + PCIBus *iommu_bus; + + pci_device_get_iommu_bus_devfn(dev, &iommu_bus, NULL, NULL); + if (iommu_bus && iommu_bus->iommu_ops->get_viommu_flags) { + return iommu_bus->iommu_ops->get_viommu_flags(iommu_bus->iommu_opa= que); + } + return 0; +} + int pci_pri_request_page(PCIDevice *dev, uint32_t pasid, bool priv_req, bool exec_req, hwaddr addr, bool lpig, uint16_t prgi, bool is_read, bool is_write) --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; 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a="69087594" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69087594" X-CSE-ConnectionGUID: xVaClvrWRAS0Yl5QZDfdfw== X-CSE-MsgGUID: rbjYEgDAQ1+mc5XbUBQSNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588748" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 06/19] intel_iommu: Implement get_viommu_flags() callback Date: Tue, 6 Jan 2026 01:12:48 -0500 Message-ID: <20260106061304.314546-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Implement get_viommu_flags() callback and expose a request for nesting parent HWPT for now. VFIO uses it to create nesting parent HWPT which is further used to create nested HWPT in vIOMMU. All these will be implemented in following patches. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Yi Liu Reviewed-by: Michael S. Tsirkin --- hw/i386/intel_iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 7bec53a587..9ce1bab93c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -24,6 +24,7 @@ #include "qemu/main-loop.h" #include "qapi/error.h" #include "hw/core/sysbus.h" +#include "hw/core/iommu.h" #include "intel_iommu_internal.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -4659,6 +4660,16 @@ static void vtd_dev_unset_iommu_device(PCIBus *bus, = void *opaque, int devfn) vtd_iommu_unlock(s); } =20 +static uint64_t vtd_get_viommu_flags(void *opaque) +{ + IntelIOMMUState *s =3D opaque; + uint64_t flags; + + flags =3D s->fsts ? VIOMMU_FLAG_WANT_NESTING_PARENT : 0; + + return flags; +} + /* Unmap the whole range in the notifier's scope. */ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n) { @@ -5312,6 +5323,7 @@ static PCIIOMMUOps vtd_iommu_ops =3D { .pri_register_notifier =3D vtd_pri_register_notifier, .pri_unregister_notifier =3D vtd_pri_unregister_notifier, .pri_request_page =3D vtd_pri_request_page, + .get_viommu_flags =3D vtd_get_viommu_flags, }; =20 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1767680114; cv=none; d=zohomail.com; s=zohoarc; b=mAbBQvgwmcGjI8bktYiLw+FMPDLOpc1deVRMtrJC1d6ySx4cDcy9fk1O2HgrYZtU5itBShhLEAMBknwNyimImG3jimEf2frLnveVeHMrOkRMl1mc9BfmftbKq7KkKXwhZ//ITEqYVFfv8wGZkqQwvqVonCEuJYm+OA6sWd6uvaE= ARC-Message-Signature: i=1; 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charset="utf-8" Introduce a new structure VTDHostIOMMUDevice which replaces HostIOMMUDevice to be stored in hash table. It includes a reference to HostIOMMUDevice and IntelIOMMUState, also includes BDF information which will be used in future patches. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Yi Liu Reviewed-by: Michael S. Tsirkin --- hw/i386/intel_iommu_internal.h | 7 +++++++ include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 15 +++++++++++++-- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 3330298884..02522f64e0 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -28,6 +28,7 @@ #ifndef HW_I386_INTEL_IOMMU_INTERNAL_H #define HW_I386_INTEL_IOMMU_INTERNAL_H #include "hw/i386/intel_iommu.h" +#include "system/host_iommu_device.h" =20 /* * Intel IOMMU register specification @@ -678,4 +679,10 @@ typedef struct VTDPASIDCacheInfo { /* Bits to decide the offset for each level */ #define VTD_LEVEL_BITS 9 =20 +typedef struct VTDHostIOMMUDevice { + IntelIOMMUState *iommu_state; + PCIBus *bus; + uint8_t devfn; + HostIOMMUDevice *hiod; +} VTDHostIOMMUDevice; #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 0b7832d25d..401322665a 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -302,7 +302,7 @@ struct IntelIOMMUState { /* list of registered notifiers */ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; =20 - GHashTable *vtd_host_iommu_dev; /* HostIOMMUDevice */ + GHashTable *vtd_host_iommu_dev; /* VTDHostIOMMUDevice */ =20 /* interrupt remapping */ bool intr_enabled; /* Whether guest enabled IR */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9ce1bab93c..3a3725e489 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -288,7 +288,10 @@ static gboolean vtd_hiod_equal(gconstpointer v1, gcons= tpointer v2) =20 static void vtd_hiod_destroy(gpointer v) { - object_unref(v); + VTDHostIOMMUDevice *vtd_hiod =3D v; + + object_unref(vtd_hiod->hiod); + g_free(vtd_hiod); } =20 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, @@ -4601,6 +4604,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, HostIOMMUDevice *hiod, Error **errp) { IntelIOMMUState *s =3D opaque; + VTDHostIOMMUDevice *vtd_hiod; struct vtd_as_key key =3D { .bus =3D bus, .devfn =3D devfn, @@ -4623,7 +4627,14 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, vo= id *opaque, int devfn, return false; } =20 + vtd_hiod =3D g_malloc0(sizeof(VTDHostIOMMUDevice)); + vtd_hiod->bus =3D bus; + vtd_hiod->devfn =3D (uint8_t)devfn; + vtd_hiod->iommu_state =3D s; + vtd_hiod->hiod =3D hiod; + if (!vtd_check_hiod(s, hiod, errp)) { + g_free(vtd_hiod); vtd_iommu_unlock(s); return false; } @@ -4633,7 +4644,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, new_key->devfn =3D devfn; =20 object_ref(hiod); - g_hash_table_insert(s->vtd_host_iommu_dev, new_key, hiod); + g_hash_table_insert(s->vtd_host_iommu_dev, new_key, vtd_hiod); =20 vtd_iommu_unlock(s); =20 --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1767680180; cv=none; d=zohomail.com; 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charset="utf-8" Call pci_device_get_viommu_flags() to get if vIOMMU supports VIOMMU_FLAG_WANT_NESTING_PARENT. If yes, create a nesting parent HWPT and add it to the container's hwpt_lis= t, letting this parent HWPT cover the entire second stage mappings (GPA=3D>HPA= ). This allows a VFIO passthrough device to directly attach to this default HW= PT and then to use the system address space and its listener. Introduce a vfio_device_get_viommu_flags_want_nesting() helper to facilitate this implementation. It is safe to do so because a vIOMMU will be able to fail in set_iommu_devi= ce() call, if something else related to the VFIO device or vIOMMU isn't compatib= le. Suggested-by: Nicolin Chen Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Reviewed-by: Yi Liu Reviewed-by: Michael S. Tsirkin --- include/hw/vfio/vfio-device.h | 2 ++ hw/vfio/device.c | 12 ++++++++++++ hw/vfio/iommufd.c | 9 +++++++++ 3 files changed, 23 insertions(+) diff --git a/include/hw/vfio/vfio-device.h b/include/hw/vfio/vfio-device.h index 0fe6c60ba2..0bc877ff62 100644 --- a/include/hw/vfio/vfio-device.h +++ b/include/hw/vfio/vfio-device.h @@ -257,6 +257,8 @@ void vfio_device_prepare(VFIODevice *vbasedev, VFIOCont= ainer *bcontainer, =20 void vfio_device_unprepare(VFIODevice *vbasedev); =20 +bool vfio_device_get_viommu_flags_want_nesting(VFIODevice *vbasedev); + int vfio_device_get_region_info(VFIODevice *vbasedev, int index, struct vfio_region_info **info); int vfio_device_get_region_info_type(VFIODevice *vbasedev, uint32_t type, diff --git a/hw/vfio/device.c b/hw/vfio/device.c index 19d1236ed7..100532f35d 100644 --- a/hw/vfio/device.c +++ b/hw/vfio/device.c @@ -23,6 +23,7 @@ =20 #include "hw/vfio/vfio-device.h" #include "hw/vfio/pci.h" +#include "hw/core/iommu.h" #include "hw/core/hw-error.h" #include "trace.h" #include "qapi/error.h" @@ -515,6 +516,17 @@ void vfio_device_unprepare(VFIODevice *vbasedev) vbasedev->bcontainer =3D NULL; } =20 +bool vfio_device_get_viommu_flags_want_nesting(VFIODevice *vbasedev) +{ + VFIOPCIDevice *vdev =3D vfio_pci_from_vfio_device(vbasedev); + + if (vdev) { + return !!(pci_device_get_viommu_flags(PCI_DEVICE(vdev)) & + VIOMMU_FLAG_WANT_NESTING_PARENT); + } + return false; +} + /* * Traditional ioctl() based io */ diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 32e8615ad3..e5328c63a3 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -361,6 +361,15 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *v= basedev, flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING; } =20 + /* + * If vIOMMU requests VFIO's cooperation to create nesting parent HWPT, + * force to create it so that it could be reused by vIOMMU to create + * nested HWPT. + */ + if (vfio_device_get_viommu_flags_want_nesting(vbasedev)) { + flags |=3D IOMMU_HWPT_ALLOC_NEST_PARENT; + } + if (cpr_is_incoming()) { hwpt_id =3D vbasedev->cpr.hwpt_id; goto skip_alloc; --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="69087621" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69087621" X-CSE-ConnectionGUID: 9qVrivNhRze9hHMs/PpNYQ== X-CSE-MsgGUID: M73d/AkeSiKbZYyA/p15vA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588800" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 09/19] intel_iommu_accel: Check for compatibility with IOMMUFD backed device when x-flts=on Date: Tue, 6 Jan 2026 01:12:51 -0500 Message-ID: <20260106061304.314546-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1767680173848158500 When vIOMMU is configured x-flts=3Don in scalable mode, first stage page ta= ble is passed to host to construct nested page table for passthrough devices. We need to check compatibility of some critical IOMMU capabilities between vIOMMU and host IOMMU to ensure guest first stage page table could be used = by host. For instance, vIOMMU supports first stage 1GB large page mapping, but host = does not, then this IOMMUFD backed device should fail. Even of the checks pass, for now we willingly reject the association because all the bits are not there yet, it will be relaxed in the end of this serie= s. Note vIOMMU has exposed IOMMU_HWPT_ALLOC_NEST_PARENT flag to force VFIO cor= e to create nesting parent HWPT, if host doesn't support nested translation, the creation will fail. So no need to check nested capability here. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- MAINTAINERS | 1 + hw/i386/intel_iommu_accel.h | 28 +++++++++++++++++++++++++ hw/i386/intel_iommu.c | 5 ++--- hw/i386/intel_iommu_accel.c | 42 +++++++++++++++++++++++++++++++++++++ hw/i386/Kconfig | 5 +++++ hw/i386/meson.build | 1 + 6 files changed, 79 insertions(+), 3 deletions(-) create mode 100644 hw/i386/intel_iommu_accel.h create mode 100644 hw/i386/intel_iommu_accel.c diff --git a/MAINTAINERS b/MAINTAINERS index 3ff0d3a4da..a00539e650 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3931,6 +3931,7 @@ R: Cl=C3=A9ment Mathieu--Drif S: Supported F: hw/i386/intel_iommu.c F: hw/i386/intel_iommu_internal.h +F: hw/i386/intel_iommu_accel.* F: include/hw/i386/intel_iommu.h F: tests/functional/x86_64/test_intel_iommu.py F: tests/qtest/intel-iommu-test.c diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h new file mode 100644 index 0000000000..472ae109e2 --- /dev/null +++ b/hw/i386/intel_iommu_accel.h @@ -0,0 +1,28 @@ +/* + * Intel IOMMU acceleration with nested translation + * + * Copyright (C) 2025 Intel Corporation. + * + * Authors: Zhenzhong Duan + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_I386_INTEL_IOMMU_ACCEL_H +#define HW_I386_INTEL_IOMMU_ACCEL_H +#include CONFIG_DEVICES + +#ifdef CONFIG_VTD_ACCEL +bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, + Error **errp); +#else +static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, + HostIOMMUDevice *hiod, + Error **errp) +{ + error_setg(errp, "host IOMMU cannot be checked!"); + error_append_hint(errp, "CONFIG_VTD_ACCEL is not enabled"); + return false; +} +#endif +#endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3a3725e489..b11798d4b7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -26,6 +26,7 @@ #include "hw/core/sysbus.h" #include "hw/core/iommu.h" #include "intel_iommu_internal.h" +#include "intel_iommu_accel.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/core/qdev-properties.h" @@ -4595,9 +4596,7 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, return true; } =20 - error_setg(errp, - "host device is uncompatible with first stage translation"); - return false; + return vtd_check_hiod_accel(s, hiod, errp); } =20 static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c new file mode 100644 index 0000000000..6846c6ec4d --- /dev/null +++ b/hw/i386/intel_iommu_accel.c @@ -0,0 +1,42 @@ +/* + * Intel IOMMU acceleration with nested translation + * + * Copyright (C) 2025 Intel Corporation. + * + * Authors: Zhenzhong Duan + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "system/iommufd.h" +#include "intel_iommu_internal.h" +#include "intel_iommu_accel.h" + +bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, + Error **errp) +{ + struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; + struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + + if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { + error_setg(errp, "Need IOMMUFD backend when x-flts=3Don"); + return false; + } + + if (caps->type !=3D IOMMU_HW_INFO_TYPE_INTEL_VTD) { + error_setg(errp, "Incompatible host platform IOMMU type %d", + caps->type); + return false; + } + + if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) { + error_setg(errp, + "First stage 1GB large page is unsupported by host IOMM= U"); + return false; + } + + error_setg(errp, + "host IOMMU is incompatible with guest first stage translat= ion"); + return false; +} diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 6a0ab54bea..12473acaa7 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -150,8 +150,13 @@ config X86_IOMMU =20 config VTD bool + imply VTD_ACCEL select X86_IOMMU =20 +config VTD_ACCEL + bool + depends on VTD && IOMMUFD + config AMD_IOMMU bool select X86_IOMMU diff --git a/hw/i386/meson.build b/hw/i386/meson.build index 436b3ce52d..63ae57baa5 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -21,6 +21,7 @@ i386_ss.add(when: 'CONFIG_Q35', if_true: files('pc_q35.c'= )) i386_ss.add(when: 'CONFIG_VMMOUSE', if_true: files('vmmouse.c')) i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport.c')) i386_ss.add(when: 'CONFIG_VTD', if_true: files('intel_iommu.c')) +i386_ss.add(when: 'CONFIG_VTD_ACCEL', if_true: files('intel_iommu_accel.c'= )) i386_ss.add(when: 'CONFIG_SGX', if_true: files('sgx-epc.c','sgx.c'), if_false: files('sgx-stub.c')) =20 --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="69094017" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69094017" X-CSE-ConnectionGUID: kU7FO+TWQIyNRJU74FskIQ== X-CSE-MsgGUID: o9QGi8+TRqae2R0+B81Y0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588828" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 10/19] intel_iommu_accel: Fail passthrough device under PCI bridge if x-flts=on Date: Tue, 6 Jan 2026 01:12:52 -0500 Message-ID: <20260106061304.314546-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.18; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1767680117535158500 Content-Type: text/plain; charset="utf-8" Currently we don't support nested translation for passthrough device with emulated device under same PCI bridge, because they require different addre= ss space when x-flts=3Don. In theory, we do support if devices under same PCI bridge are all passthrou= gh devices. But emulated device can be hotplugged under same bridge. To simpli= fy, just forbid passthrough device under PCI bridge no matter if there is, or w= ill be emulated devices under same bridge. This is acceptable because PCIE brid= ge is more popular than PCI bridge now. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu_accel.h | 4 ++-- hw/i386/intel_iommu.c | 7 ++++--- hw/i386/intel_iommu_accel.c | 12 +++++++++++- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 472ae109e2..76e0d26942 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -13,11 +13,11 @@ #include CONFIG_DEVICES =20 #ifdef CONFIG_VTD_ACCEL -bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, +bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, - HostIOMMUDevice *hiod, + VTDHostIOMMUDevice *vtd_hiod, Error **errp) { error_setg(errp, "host IOMMU cannot be checked!"); diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index b11798d4b7..0817b17772 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4570,9 +4570,10 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, return vtd_dev_as; } =20 -static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, +static bool vtd_check_hiod(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hio= d, Error **errp) { + HostIOMMUDevice *hiod =3D vtd_hiod->hiod; HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); int ret; =20 @@ -4596,7 +4597,7 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, return true; } =20 - return vtd_check_hiod_accel(s, hiod, errp); + return vtd_check_hiod_accel(s, vtd_hiod, errp); } =20 static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, @@ -4632,7 +4633,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hiod->iommu_state =3D s; vtd_hiod->hiod =3D hiod; =20 - if (!vtd_check_hiod(s, hiod, errp)) { + if (!vtd_check_hiod(s, vtd_hiod, errp)) { g_free(vtd_hiod); vtd_iommu_unlock(s); return false; diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 6846c6ec4d..ead6c42879 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -12,12 +12,16 @@ #include "system/iommufd.h" #include "intel_iommu_internal.h" #include "intel_iommu_accel.h" +#include "hw/pci/pci_bus.h" =20 -bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, +bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp) { + HostIOMMUDevice *hiod =3D vtd_hiod->hiod; struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + PCIBus *bus =3D vtd_hiod->bus; + PCIDevice *pdev =3D bus->devices[vtd_hiod->devfn]; =20 if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { error_setg(errp, "Need IOMMUFD backend when x-flts=3Don"); @@ -36,6 +40,12 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUD= evice *hiod, return false; } =20 + if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) { + error_setg(errp, "Host device downstream to a PCI bridge is " + "unsupported when x-flts=3Don"); + return false; + } + error_setg(errp, "host IOMMU is incompatible with guest first stage translat= ion"); return false; --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="202588847" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 11/19] intel_iommu_accel: Stick to system MR for IOMMUFD backed host device when x-flts=on Date: Tue, 6 Jan 2026 01:12:53 -0500 Message-ID: <20260106061304.314546-12-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" When guest enables scalable mode and setup first stage page table, we don't want to use IOMMU MR but rather continue using the system MR for IOMMUFD backed host device. Then default HWPT in VFIO contains GPA->HPA mappings which could be reused as nesting parent HWPT to construct nested HWPT in vIOMMU. Move vtd_as_key into intel_iommu_internal.h as it's also used by accel code. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu_accel.h | 6 ++++++ hw/i386/intel_iommu_internal.h | 11 +++++++++++ hw/i386/intel_iommu.c | 28 +++++++++++++++------------- hw/i386/intel_iommu_accel.c | 18 ++++++++++++++++++ 4 files changed, 50 insertions(+), 13 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 76e0d26942..d049cab3e1 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -15,6 +15,7 @@ #ifdef CONFIG_VTD_ACCEL bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); +VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, @@ -24,5 +25,10 @@ static inline bool vtd_check_hiod_accel(IntelIOMMUState = *s, error_append_hint(errp, "CONFIG_VTD_ACCEL is not enabled"); return false; } + +static inline VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *a= s) +{ + return NULL; +} #endif #endif diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 02522f64e0..d8dad18304 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -685,4 +685,15 @@ typedef struct VTDHostIOMMUDevice { uint8_t devfn; HostIOMMUDevice *hiod; } VTDHostIOMMUDevice; + +/* + * PCI bus number (or SID) is not reliable since the device is usaully + * initialized before guest can configure the PCI bridge + * (SECONDARY_BUS_NUMBER). + */ +struct vtd_as_key { + PCIBus *bus; + uint8_t devfn; + uint32_t pasid; +}; #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0817b17772..d5a4e02fa1 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -55,17 +55,6 @@ #define VTD_PE_GET_SS_LEVEL(pe) \ (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) =20 -/* - * PCI bus number (or SID) is not reliable since the device is usaully - * initialized before guest can configure the PCI bridge - * (SECONDARY_BUS_NUMBER). - */ -struct vtd_as_key { - PCIBus *bus; - uint8_t devfn; - uint32_t pasid; -}; - /* bus/devfn is PCI device's real BDF not the aliased one */ struct vtd_hiod_key { PCIBus *bus; @@ -1730,12 +1719,25 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as) /* Return whether the device is using IOMMU translation. */ static bool vtd_switch_address_space(VTDAddressSpace *as) { + IntelIOMMUState *s; bool use_iommu, pt; =20 assert(as); =20 - use_iommu =3D as->iommu_state->dmar_enabled && !vtd_as_pt_enabled(as); - pt =3D as->iommu_state->dmar_enabled && vtd_as_pt_enabled(as); + s =3D as->iommu_state; + use_iommu =3D s->dmar_enabled && !vtd_as_pt_enabled(as); + pt =3D s->dmar_enabled && vtd_as_pt_enabled(as); + + /* + * When guest enables scalable mode and sets up first stage page table, + * we stick to system MR for IOMMUFD backed host device. Then its + * default hwpt contains GPA->HPA mappings which is used directly if + * PGTT=3DPT and used as nesting parent if PGTT=3DFST. Otherwise fall = back + * to original processing. + */ + if (s->root_scalable && s->fsts && vtd_find_hiod_iommufd(as)) { + use_iommu =3D false; + } =20 trace_vtd_switch_address_space(pci_bus_num(as->bus), VTD_PCI_SLOT(as->devfn), diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index ead6c42879..ebfc503d64 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -50,3 +50,21 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOM= MUDevice *vtd_hiod, "host IOMMU is incompatible with guest first stage translat= ion"); return false; } + +VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as) +{ + IntelIOMMUState *s =3D as->iommu_state; + struct vtd_as_key key =3D { + .bus =3D as->bus, + .devfn =3D as->devfn, + }; + VTDHostIOMMUDevice *vtd_hiod =3D g_hash_table_lookup(s->vtd_host_iommu= _dev, + &key); + + if (vtd_hiod && vtd_hiod->hiod && + object_dynamic_cast(OBJECT(vtd_hiod->hiod), + TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { + return vtd_hiod; + } + return NULL; +} --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1767680171; cv=none; d=zohomail.com; s=zohoarc; b=KyDcH58AnGrjkKvpKAEHlS2LPYF9EuYJWZTVkc1Ds5YgJAjOGROq5pQeTnUxofO5ot17DaHc/xRdLm/BA+AByqoOIdYpWt6ZJVlbWPQ5uN+DQwcWBzZ3udH2OvKzAXAdbbP8uE4k4G3B1cvHpouwOpZWHkMJLYt+9NT9q3VY4k8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767680171; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BxswiZ59GpUpxI4xVfRHZs5eHE9UW38ZKBbX2omACSU=; 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a="69094030" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69094030" X-CSE-ConnectionGUID: fr4pWdNnTWq4v3NeM96WfA== X-CSE-MsgGUID: 0se/v8XaRoSmtXXPecksgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588863" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 12/19] intel_iommu: Add some macros and inline functions Date: Tue, 6 Jan 2026 01:12:54 -0500 Message-ID: <20260106061304.314546-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add some macros and inline functions that will be used by following patch. This patch also make a cleanup to change below macros to use extract64() just like what smmu does, because they are either used in following patches or used indirectly by new introduced inline functions. VTD_INV_DESC_PIOTLB_IH VTD_SM_PASID_ENTRY_PGTT VTD_SM_PASID_ENTRY_DID VTD_SM_PASID_ENTRY_FSPM VTD_SM_PASID_ENTRY_FSPTPTR But we doesn't aim to change the huge amount of bit mask style macro definitions in this patch, that should be in a separate patch. Suggested-by: Eric Auger Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin --- hw/i386/intel_iommu_internal.h | 50 ++++++++++++++++++++++++++++------ hw/i386/intel_iommu.c | 27 +++++++++--------- 2 files changed, 55 insertions(+), 22 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index d8dad18304..e987322e93 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -516,7 +516,7 @@ typedef union VTDPRDesc VTDPRDesc; #define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_M= ASK) #define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) #define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL) -#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1) +#define VTD_INV_DESC_PIOTLB_IH(x) extract64((x)->val[1], 6, 1) #define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL) #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL @@ -636,17 +636,20 @@ typedef struct VTDPASIDCacheInfo { =20 /* PASID Granular Translation Type Mask */ #define VTD_PASID_ENTRY_P 1ULL -#define VTD_SM_PASID_ENTRY_PGTT (7ULL << 6) -#define VTD_SM_PASID_ENTRY_FST (1ULL << 6) -#define VTD_SM_PASID_ENTRY_SST (2ULL << 6) -#define VTD_SM_PASID_ENTRY_NESTED (3ULL << 6) -#define VTD_SM_PASID_ENTRY_PT (4ULL << 6) +#define VTD_SM_PASID_ENTRY_PGTT(x) extract64((x)->val[0], 6, 3) +#define VTD_SM_PASID_ENTRY_FST 1 +#define VTD_SM_PASID_ENTRY_SST 2 +#define VTD_SM_PASID_ENTRY_NESTED 3 +#define VTD_SM_PASID_ENTRY_PT 4 =20 #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-widt= h */ -#define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK) +#define VTD_SM_PASID_ENTRY_DID(x) extract64((x)->val[1], 0, 16) =20 -#define VTD_SM_PASID_ENTRY_FSPM 3ULL -#define VTD_SM_PASID_ENTRY_FSPTPTR (~0xfffULL) +#define VTD_SM_PASID_ENTRY_SRE(x) extract64((x)->val[2], 0, 1) +#define VTD_SM_PASID_ENTRY_FSPM(x) extract64((x)->val[2], 2, 2) +#define VTD_SM_PASID_ENTRY_WPE(x) extract64((x)->val[2], 4, 1) +#define VTD_SM_PASID_ENTRY_EAFE(x) extract64((x)->val[2], 7, 1) +#define VTD_SM_PASID_ENTRY_FSPTPFN(x) extract64((x)->val[2], 12, 52) =20 /* First Stage Paging Structure */ /* Masks for First Stage Paging Entry */ @@ -696,4 +699,33 @@ struct vtd_as_key { uint8_t devfn; uint32_t pasid; }; + +static inline dma_addr_t vtd_pe_get_fspt_base(VTDPASIDEntry *pe) +{ + return VTD_SM_PASID_ENTRY_FSPTPFN(pe) << VTD_PAGE_SHIFT; +} + +/* + * First stage IOVA address width: 48 bits for 4-level paging(FSPM=3D00) + * 57 bits for 5-level paging(FSPM=3D01) + */ +static inline uint32_t vtd_pe_get_fs_aw(VTDPASIDEntry *pe) +{ + /* + * Paging mode for first-stage translation (VTD spec Figure 9-6) + * 00: 4-level paging, 01: 5-level paging + */ + return VTD_HOST_AW_48BIT + VTD_SM_PASID_ENTRY_FSPM(pe) * 9; +} + +static inline bool vtd_pe_pgtt_is_pt(VTDPASIDEntry *pe) +{ + return (VTD_SM_PASID_ENTRY_PGTT(pe) =3D=3D VTD_SM_PASID_ENTRY_PT); +} + +/* check if PGTT is first stage translation */ +static inline bool vtd_pe_pgtt_is_fst(VTDPASIDEntry *pe) +{ + return (VTD_SM_PASID_ENTRY_PGTT(pe) =3D=3D VTD_SM_PASID_ENTRY_FST); +} #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index d5a4e02fa1..9edd625b1a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -48,10 +48,11 @@ #define VTD_CE_GET_PRE(ce) \ ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE) =20 -/* pe operations */ -#define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) -#define VTD_PE_GET_FS_LEVEL(pe) \ - (4 + (((pe)->val[2] >> 2) & VTD_SM_PASID_ENTRY_FSPM)) +/* + * Paging mode for first-stage translation (VTD spec Figure 9-6) + * 00: 4-level paging, 01: 5-level paging + */ +#define VTD_PE_GET_FS_LEVEL(pe) (VTD_SM_PASID_ENTRY_FSPM(pe) + 4) #define VTD_PE_GET_SS_LEVEL(pe) \ (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) =20 @@ -807,7 +808,7 @@ static inline bool vtd_is_fs_level_supported(IntelIOMMU= State *s, uint32_t level) /* Return true if check passed, otherwise false */ static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe) { - switch (VTD_PE_GET_TYPE(pe)) { + switch (VTD_SM_PASID_ENTRY_PGTT(pe)) { case VTD_SM_PASID_ENTRY_FST: return !!(s->ecap & VTD_ECAP_FSTS); case VTD_SM_PASID_ENTRY_SST: @@ -882,7 +883,7 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUSta= te *s, return -VTD_FR_PASID_TABLE_ENTRY_INV; } =20 - pgtt =3D VTD_PE_GET_TYPE(pe); + pgtt =3D VTD_SM_PASID_ENTRY_PGTT(pe); if (pgtt =3D=3D VTD_SM_PASID_ENTRY_SST && !vtd_is_ss_level_supported(s, VTD_PE_GET_SS_LEVEL(pe))) { return -VTD_FR_PASID_TABLE_ENTRY_INV; @@ -1116,7 +1117,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, if (s->root_scalable) { vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->fsts) { - return pe.val[2] & VTD_SM_PASID_ENTRY_FSPTPTR; + return vtd_pe_get_fspt_base(&pe); } else { return pe.val[0] & VTD_SM_PASID_ENTRY_SSPTPTR; } @@ -1605,7 +1606,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, =20 if (s->root_scalable) { vtd_ce_get_pasid_entry(s, ce, &pe, pasid); - return VTD_SM_PASID_ENTRY_DID(pe.val[1]); + return VTD_SM_PASID_ENTRY_DID(&pe); } =20 return VTD_CONTEXT_ENTRY_DID(ce->hi); @@ -1687,7 +1688,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, */ return false; } - return (VTD_PE_GET_TYPE(&pe) =3D=3D VTD_SM_PASID_ENTRY_PT); + return vtd_pe_pgtt_is_pt(&pe); } =20 return (vtd_ce_get_type(ce) =3D=3D VTD_CONTEXT_TT_PASS_THROUGH); @@ -3108,9 +3109,9 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, /* Fall through */ case VTD_INV_DESC_PASIDC_G_DSI: if (pc_entry->valid) { - did =3D VTD_SM_PASID_ENTRY_DID(pc_entry->pasid_entry.val[1]); + did =3D VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); } else { - did =3D VTD_SM_PASID_ENTRY_DID(pe.val[1]); + did =3D VTD_SM_PASID_ENTRY_DID(&pe); } if (pc_info->did !=3D did) { return; @@ -5154,8 +5155,8 @@ static int vtd_pri_perform_implicit_invalidation(VTDA= ddressSpace *vtd_as, if (ret) { return -EINVAL; } - pgtt =3D VTD_PE_GET_TYPE(&pe); - domain_id =3D VTD_SM_PASID_ENTRY_DID(pe.val[1]); + pgtt =3D VTD_SM_PASID_ENTRY_PGTT(&pe); + domain_id =3D VTD_SM_PASID_ENTRY_DID(&pe); ret =3D 0; switch (pgtt) { case VTD_SM_PASID_ENTRY_FST: --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" This captures the guest PASID table entry modifications and propagates the changes to host to attach a hwpt with type determined per guest IOMMU PGTT configuration. When PGTT=3DPT, attach PASID_0 to a second stage HWPT(GPA->HPA). When PGTT=3DFST, attach PASID_0 to nested HWPT with nesting parent HWPT coming from VFIO. Co-Authored-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Thanks Eric Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu_accel.h | 7 +++ include/hw/i386/intel_iommu.h | 2 + hw/i386/intel_iommu.c | 22 ++++++- hw/i386/intel_iommu_accel.c | 114 ++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 3 + 5 files changed, 145 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index d049cab3e1..82821ec0ef 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -16,6 +16,7 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); +bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, @@ -30,5 +31,11 @@ static inline VTDHostIOMMUDevice *vtd_find_hiod_iommufd(= VTDAddressSpace *as) { return NULL; } + +static inline bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, + Error **errp) +{ + return true; +} #endif #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 401322665a..6c61fd39c7 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -154,6 +154,8 @@ struct VTDAddressSpace { * with the guest IOMMU pgtables for a device. */ IOVATree *iova_tree; + + uint32_t fs_hwpt_id; }; =20 struct VTDIOTLBEntry { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9edd625b1a..f9b80e3257 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -87,7 +87,11 @@ static void vtd_pasid_cache_reset_locked(IntelIOMMUState= *s) g_hash_table_iter_init(&as_it, s->vtd_address_spaces); while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_as)) { VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; - pc_entry->valid =3D false; + if (pc_entry->valid) { + pc_entry->valid =3D false; + /* It's fatal to get failure during reset */ + vtd_propagate_guest_pasid(vtd_as, &error_fatal); + } } } =20 @@ -3073,6 +3077,8 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, VTDPASIDEntry pe; IOMMUNotifier *n; uint16_t did; + const char *err_prefix =3D "Attaching to HWPT failed: "; + Error *local_err =3D NULL; =20 if (vtd_dev_get_pe_from_pasid(vtd_as, &pe)) { if (!pc_entry->valid) { @@ -3093,7 +3099,9 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, vtd_address_space_unmap(vtd_as, n); } vtd_switch_address_space(vtd_as); - return; + + err_prefix =3D "Detaching from HWPT failed: "; + goto do_bind_unbind; } =20 /* @@ -3121,12 +3129,20 @@ static void vtd_pasid_cache_sync_locked(gpointer ke= y, gpointer value, if (!pc_entry->valid) { pc_entry->pasid_entry =3D pe; pc_entry->valid =3D true; - } else if (!vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { + } else if (vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { + err_prefix =3D "Replacing HWPT attachment failed: "; + } else { return; } =20 vtd_switch_address_space(vtd_as); vtd_address_space_sync(vtd_as); + +do_bind_unbind: + /* TODO: Fault event injection into guest, report error to QEMU for no= w */ + if (!vtd_propagate_guest_pasid(vtd_as, &local_err)) { + error_reportf_err(local_err, "%s", err_prefix); + } } =20 static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index ebfc503d64..748a6c7e1c 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -13,6 +13,7 @@ #include "intel_iommu_internal.h" #include "intel_iommu_accel.h" #include "hw/pci/pci_bus.h" +#include "trace.h" =20 bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp) @@ -68,3 +69,116 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpa= ce *as) } return NULL; } + +static bool vtd_create_fs_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDPASIDEntry *pe, uint32_t *fs_hwpt_id, + Error **errp) +{ + struct iommu_hwpt_vtd_s1 vtd =3D {}; + + vtd.flags =3D (VTD_SM_PASID_ENTRY_SRE(pe) ? IOMMU_VTD_S1_SRE : 0) | + (VTD_SM_PASID_ENTRY_WPE(pe) ? IOMMU_VTD_S1_WPE : 0) | + (VTD_SM_PASID_ENTRY_EAFE(pe) ? IOMMU_VTD_S1_EAFE : 0); + vtd.addr_width =3D vtd_pe_get_fs_aw(pe); + vtd.pgtbl_addr =3D (uint64_t)vtd_pe_get_fspt_base(pe); + + return iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, idev->hw= pt_id, + 0, IOMMU_HWPT_DATA_VTD_S1, sizeof(vt= d), + &vtd, fs_hwpt_id, errp); +} + +static void vtd_destroy_old_fs_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDAddressSpace *vtd_as) +{ + if (!vtd_as->fs_hwpt_id) { + return; + } + iommufd_backend_free_id(idev->iommufd, vtd_as->fs_hwpt_id); + vtd_as->fs_hwpt_id =3D 0; +} + +static bool vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **err= p) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + VTDPASIDEntry *pe =3D &vtd_as->pasid_cache_entry.pasid_entry; + uint32_t hwpt_id =3D idev->hwpt_id; + bool ret; + + /* + * We can get here only if flts=3Don, the supported PGTT is FST or PT. + * Catch invalid PGTT when processing invalidation request to avoid + * attaching to wrong hwpt. + */ + if (!vtd_pe_pgtt_is_fst(pe) && !vtd_pe_pgtt_is_pt(pe)) { + error_setg(errp, "Invalid PGTT type %d", + (uint8_t)VTD_SM_PASID_ENTRY_PGTT(pe)); + return false; + } + + if (vtd_pe_pgtt_is_fst(pe)) { + if (!vtd_create_fs_hwpt(idev, pe, &hwpt_id, errp)) { + return false; + } + } + + ret =3D host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp); + trace_vtd_device_attach_hwpt(idev->devid, vtd_as->pasid, hwpt_id, ret); + if (ret) { + /* Destroy old fs_hwpt if it's a replacement */ + vtd_destroy_old_fs_hwpt(idev, vtd_as); + if (vtd_pe_pgtt_is_fst(pe)) { + vtd_as->fs_hwpt_id =3D hwpt_id; + } + } else if (vtd_pe_pgtt_is_fst(pe)) { + iommufd_backend_free_id(idev->iommufd, hwpt_id); + } + + return ret; +} + +static bool vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **err= p) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint32_t pasid =3D vtd_as->pasid; + bool ret; + + if (s->dmar_enabled && s->root_scalable) { + ret =3D host_iommu_device_iommufd_detach_hwpt(idev, errp); + trace_vtd_device_detach_hwpt(idev->devid, pasid, ret); + } else { + /* + * If DMAR remapping is disabled or guest switches to legacy mode, + * we fallback to the default HWPT which contains shadow page tabl= e. + * So guest DMA could still work. + */ + ret =3D host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id,= errp); + trace_vtd_device_reattach_def_hwpt(idev->devid, pasid, idev->hwpt_= id, + ret); + } + + if (ret) { + vtd_destroy_old_fs_hwpt(idev, vtd_as); + } + + return ret; +} + +bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp) +{ + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); + + /* Ignore emulated device or legacy VFIO backed device */ + if (!vtd_as->iommu_state->fsts || !vtd_hiod) { + return true; + } + + if (pc_entry->valid) { + return vtd_device_attach_iommufd(vtd_hiod, vtd_as, errp); + } + + return vtd_device_detach_iommufd(vtd_hiod, vtd_as, errp); +} diff --git a/hw/i386/trace-events b/hw/i386/trace-events index b704f4f90c..5a3ee1cf64 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -73,6 +73,9 @@ vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"= PRIx16" index %d vec %d (should be: %d)" vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x= %"PRIx16" index %d trigger %d (should be: %d)" vtd_reset_exit(void) "" +vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" +vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="69094051" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69094051" X-CSE-ConnectionGUID: EQfbKtuaT/m8/ilE8FLGqA== X-CSE-MsgGUID: 5uaZIdxDRkCvWPhLGTQwuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588891" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan Subject: [PATCH v10 14/19] intel_iommu_accel: Propagate PASID-based iotlb invalidation to host Date: Tue, 6 Jan 2026 01:12:56 -0500 Message-ID: <20260106061304.314546-15-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Yi Liu This traps the guest PASID-based iotlb invalidation request and propagate it to host. Intel VT-d 3.0 supports nested translation in PASID granularity. Guest SVA support could be implemented by configuring nested translation on specific pasid. This is also known as dual stage DMA translation. Under such configuration, guest owns the GVA->GPA translation which is configured as first stage page table on host side for a specific pasid, and host owns GPA->HPA translation. As guest owns first stage translation table, piotlb invalidation should be propagated to host since host IOMMU will cache first level page table related mappings during DMA address translation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu_accel.h | 10 +++++ hw/i386/intel_iommu_internal.h | 6 +++ hw/i386/intel_iommu.c | 11 ++++-- hw/i386/intel_iommu_accel.c | 69 ++++++++++++++++++++++++++++++++++ 4 files changed, 93 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 82821ec0ef..3b0ecc7e22 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -17,6 +17,9 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMM= UDevice *vtd_hiod, Error **errp); VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp); +void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_= id, + uint32_t pasid, hwaddr addr, + uint64_t npages, bool ih); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, @@ -37,5 +40,12 @@ static inline bool vtd_propagate_guest_pasid(VTDAddressS= pace *vtd_as, { return true; } + +static inline void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, + uint16_t domain_id, + uint32_t pasid, hwaddr= addr, + uint64_t npages, bool = ih) +{ +} #endif #endif diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e987322e93..a2ca79f925 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -622,6 +622,12 @@ typedef struct VTDPASIDCacheInfo { uint32_t pasid; } VTDPASIDCacheInfo; =20 +typedef struct VTDPIOTLBInvInfo { + uint16_t domain_id; + uint32_t pasid; + struct iommu_hwpt_vtd_s1_invalidate *inv_data; +} VTDPIOTLBInvInfo; + /* PASID Table Related Definitions */ #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f9b80e3257..2889c29102 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2967,6 +2967,8 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, &info); + vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, 0, (uint64_t)-1, + false); vtd_iommu_unlock(s); =20 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { @@ -2986,7 +2988,8 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, } =20 static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain= _id, - uint32_t pasid, hwaddr addr, uint8_= t am) + uint32_t pasid, hwaddr addr, uint8_= t am, + bool ih) { VTDIOTLBPageInvInfo info; =20 @@ -2998,6 +3001,7 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUStat= e *s, uint16_t domain_id, vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page_piotlb, &info); + vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, addr, 1 << am, i= h); vtd_iommu_unlock(s); =20 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, pasid); @@ -3029,7 +3033,8 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *= s, case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: am =3D VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]); addr =3D (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]); - vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am); + vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am, + VTD_INV_DESC_PIOTLB_IH(inv_desc)); break; =20 default: @@ -5176,7 +5181,7 @@ static int vtd_pri_perform_implicit_invalidation(VTDA= ddressSpace *vtd_as, ret =3D 0; switch (pgtt) { case VTD_SM_PASID_ENTRY_FST: - vtd_piotlb_page_invalidate(s, domain_id, vtd_as->pasid, addr, 0); + vtd_piotlb_page_invalidate(s, domain_id, vtd_as->pasid, addr, 0, f= alse); break; /* Room for other pgtt values */ default: diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 748a6c7e1c..2996e4b640 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -182,3 +182,72 @@ bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as= , Error **errp) =20 return vtd_device_detach_iommufd(vtd_hiod, vtd_as, errp); } + +/* + * This function is a loop function for the s->vtd_address_spaces + * list with VTDPIOTLBInvInfo as execution filter. It propagates + * the piotlb invalidation to host. + */ +static void vtd_flush_host_piotlb_locked(gpointer key, gpointer value, + gpointer user_data) +{ + VTDPIOTLBInvInfo *piotlb_info =3D user_data; + VTDAddressSpace *vtd_as =3D value; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + uint16_t did; + + if (!vtd_hiod) { + return; + } + + assert(vtd_as->pasid =3D=3D PCI_NO_PASID); + + /* Nothing to do if there is no first stage HWPT attached */ + if (!pc_entry->valid || + !vtd_pe_pgtt_is_fst(&pc_entry->pasid_entry)) { + return; + } + + did =3D VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); + + if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D PAS= ID_0) { + HostIOMMUDeviceIOMMUFD *idev =3D + HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod); + uint32_t entry_num =3D 1; /* Only implement one request for simpli= city */ + Error *local_err =3D NULL; + struct iommu_hwpt_vtd_s1_invalidate *cache =3D piotlb_info->inv_da= ta; + + if (!iommufd_backend_invalidate_cache(idev->iommufd, vtd_as->fs_hw= pt_id, + IOMMU_HWPT_INVALIDATE_DATA_V= TD_S1, + sizeof(*cache), &entry_num, = cache, + &local_err)) { + /* Something wrong in kernel, but trying to continue */ + error_report_err(local_err); + } + } +} + +void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_= id, + uint32_t pasid, hwaddr addr, + uint64_t npages, bool ih) +{ + struct iommu_hwpt_vtd_s1_invalidate cache_info =3D { 0 }; + VTDPIOTLBInvInfo piotlb_info; + + cache_info.addr =3D addr; + cache_info.npages =3D npages; + cache_info.flags =3D ih ? IOMMU_VTD_INV_FLAGS_LEAF : 0; + + piotlb_info.domain_id =3D domain_id; + piotlb_info.pasid =3D pasid; + piotlb_info.inv_data =3D &cache_info; + + /* + * Go through each vtd_as instance in s->vtd_address_spaces, find out + * affected host devices which need host piotlb invalidation. Piotlb + * invalidation should check pasid cache per architecture point of vie= w. + */ + g_hash_table_foreach(s->vtd_address_spaces, + vtd_flush_host_piotlb_locked, &piotlb_info); +} --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1767680117; cv=none; d=zohomail.com; s=zohoarc; b=JDqwnf2EBVxT1tQrviO3jUPZdcktOZ80sNKtDrVtocVpDMzEaKAhlCk6/C1JXrH9s/yHPzYNjsK2FAHQNhpSAtS13slOL3msU1BA3h1jaobPmLQpYbbWmT6lziCm6LKPfaBukSSmuuUko03uclcBQN+GykEOhjBoUL+hC39UpOc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767680117; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: rcNSgTLeSpaL18Jg9qrsbw== X-CSE-MsgGUID: vHzIFNuFSVOeUJwSe1BGJw== X-IronPort-AV: E=McAfee;i="6800,10657,11662"; a="69094064" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69094064" X-CSE-ConnectionGUID: mHMlmKKuQeOSeRmnxkJoIA== X-CSE-MsgGUID: Wq8zODl0RPOwA3IOAWxm7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588900" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 15/19] intel_iommu: Replay all pasid bindings when either SRTP or TE bit is changed Date: Tue, 6 Jan 2026 01:12:57 -0500 Message-ID: <20260106061304.314546-16-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Yi Liu When either 'Set Root Table Pointer' or 'Translation Enable' bit is changed, all pasid bindings on host side become stale and need to be updated. Introduce a helper function vtd_replay_pasid_bindings_all() to go through a= ll pasid entries in all passthrough devices to update host side bindings. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2889c29102..3241af811c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -76,6 +76,7 @@ struct vtd_iotlb_key { =20 static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); +static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) { @@ -2629,6 +2630,7 @@ static void vtd_handle_gcmd_srtp(IntelIOMMUState *s) vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS); vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_replay_pasid_bindings_all(s); } =20 /* Set Interrupt Remap Table Pointer */ @@ -2663,6 +2665,7 @@ static void vtd_handle_gcmd_te(IntelIOMMUState *s, bo= ol en) =20 vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_replay_pasid_bindings_all(s); } =20 /* Handle Interrupt Remap Enable/Disable */ @@ -3162,6 +3165,13 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s,= VTDPASIDCacheInfo *pc_info) vtd_iommu_unlock(s); } =20 +static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info =3D { .type =3D VTD_INV_DESC_PASIDC_G_GLOBAL= }; + + vtd_pasid_cache_sync(s, &pc_info); +} + static bool vtd_process_pasid_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1767680220; cv=none; d=zohomail.com; s=zohoarc; b=Jx5WQp0GW40W7Fu2xNuidMYgw/Qh0bTjF8Dpn1BDAzrD/CXuSOXOXDmpO8QVrqD6Oqr10n0ldV97x/9Iu5qqVFMmhqMRCt9N4qpVYntEuiHbym0X+TBDkjYKt7kmBcYuBTeqMBTO/HoGQIaiIshMBfzV2aVWz/e9U3wGkoZyMvs= ARC-Message-Signature: i=1; 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charset="utf-8" From: Yi Liu This replays guest pasid bindings after context cache invalidation. Actually, programmer should issue pasid cache invalidation with proper granularity after issuing context cache invalidation. We see old linux such as 6.7.0-rc2 not following the spec, it sends pasid cache invalidation before context cache invalidation, then QEMU depends on context cache invalidation to get pasid entry and setup binding. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 42 ++++++++++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 1 + 2 files changed, 43 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3241af811c..08236b85ee 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -77,6 +77,8 @@ struct vtd_iotlb_key { static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s); +static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value, + gpointer user_data); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) { @@ -2322,6 +2324,37 @@ static void vtd_context_global_invalidate(IntelIOMMU= State *s) * VT-d emulation codes. */ vtd_iommu_replay_all(s); + /* + * Same for pasid cache invalidation, per VT-d spec 6.5.2.1, a global + * context cache invalidation should be followed by global PASID cache + * invalidation. In order to work with guest not following spec, + * handle global PASID cache invalidation here. + */ + vtd_replay_pasid_bindings_all(s); +} + +static void vtd_pasid_cache_devsi(VTDAddressSpace *vtd_as) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + PCIBus *bus =3D vtd_as->bus; + uint8_t devfn =3D vtd_as->devfn; + struct vtd_as_key key =3D { + .bus =3D bus, + .devfn =3D devfn, + .pasid =3D vtd_as->pasid, + }; + VTDPASIDCacheInfo pc_info; + + if (!s->fsts || !s->root_scalable || !s->dmar_enabled) { + return; + } + + trace_vtd_pasid_cache_devsi(pci_bus_num(bus), + VTD_PCI_SLOT(devfn), VTD_PCI_FUNC(devfn)); + + /* We fake to be global invalidation just to bypass all checks */ + pc_info.type =3D VTD_INV_DESC_PASIDC_G_GLOBAL; + vtd_pasid_cache_sync_locked(&key, vtd_as, &pc_info); } =20 /* Do a context-cache device-selective invalidation. @@ -2382,6 +2415,15 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, * happened. */ vtd_address_space_sync(vtd_as); + /* + * Per spec 6.5.2.1, context flush should be followed by PASID + * cache and iotlb flush. In order to work with a guest which = does + * not follow spec and missed PASID cache flush, e.g., linux + * 6.7.0-rc2, we have vtd_pasid_cache_devsi() to invalidate PA= SID + * cache of passthrough device. Host iommu driver would flush + * piotlb when a pasid unbind is passed down to it. + */ + vtd_pasid_cache_devsi(vtd_as); } } } diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 5a3ee1cf64..5fa5e93b68 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -28,6 +28,7 @@ vtd_pasid_cache_reset(void) "" vtd_inv_desc_pasid_cache_gsi(void) "" vtd_inv_desc_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalid= ation domain 0x%"PRIx16 vtd_inv_desc_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selec= tive PC invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 +vtd_pasid_cache_devsi(uint8_t bus, uint8_t dev, uint8_t fn) "Dev selective= PC invalidation dev: %02"PRIx8":%02"PRIx8".%02"PRIx8 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="69094082" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69094082" X-CSE-ConnectionGUID: 9WQBuvz8QzCsOMW/4hjrfw== X-CSE-MsgGUID: Myj8NlxkRNWUmf1XEtV8pw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588928" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 17/19] intel_iommu: Add migration support with x-flts=on Date: Tue, 6 Jan 2026 01:12:59 -0500 Message-ID: <20260106061304.314546-18-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" When x-flts=3Don, we set up bindings to nested HWPT in host, after migration, VFIO device binds to nesting parent HWPT by default. We need to re-establish the bindings to nested HWPT, or else device DMA will break. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 08236b85ee..f971cdd14c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4090,6 +4090,13 @@ static int vtd_post_load(void *opaque, int version_i= d) */ vtd_switch_address_space_all(iommu); =20 + /* + * Bindings to nested HWPT in host is set up dynamically depending + * on pasid entry configuration from guest. After migration, we + * need to re-establish the bindings before restoring device's DMA. + */ + vtd_replay_pasid_bindings_all(iommu); + return 0; } =20 --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1767680115; cv=none; d=zohomail.com; s=zohoarc; b=GfcGHHIsCmK59gjUZyim+HAFJdylrgbl2nt0CcjuH2/V5kRQ34md8wUUYg/pO/Uk/JsNu0mJBHWKs47K8CaYtg09YWkH+LeAAWBVfEjpvX9fOvXroREeXPrCChB1DOG3GXa89TOhE+idVU0SEHflk9xGzUy/CCfDY7DNQ73PWvo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767680115; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: TnYN8sJYTA+IV3w6q5NU4Q== X-CSE-MsgGUID: hrwV3iy5TJ6z34ba0KpXPg== X-IronPort-AV: E=McAfee;i="6800,10657,11662"; a="69094097" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69094097" X-CSE-ConnectionGUID: HQtMe5EdRf+dOmj3dyseUg== X-CSE-MsgGUID: xVDuFPqGTLWETy9y6tN4sw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202588947" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 18/19] intel_iommu: Enable host device when x-flts=on in scalable mode Date: Tue, 6 Jan 2026 01:13:00 -0500 Message-ID: <20260106061304.314546-19-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Now that all infrastructures of supporting passthrough device running with first stage translation are there, enable it now. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Yi Liu Reviewed-by: Michael S. Tsirkin --- hw/i386/intel_iommu_accel.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 2996e4b640..89f3d55f6f 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -47,9 +47,7 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMM= UDevice *vtd_hiod, return false; } =20 - error_setg(errp, - "host IOMMU is incompatible with guest first stage translat= ion"); - return false; + return true; } =20 VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as) --=20 2.47.1 From nobody Mon Feb 9 12:44:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1767680172; cv=none; d=zohomail.com; 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a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767680088; x=1799216088; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Bgi2daNKrnU1uskTe90+7gs2wScsxhhyHbewx3ITebg=; b=O5ukluYklNyXFfSf2oc5PZaS8CbdsExVPz25HqO/eO3GAEGlY4Xbw8r9 xFntdYGIy5BfJZB0xlotO5+EmfTH57cf5fcP9B3UL60GqjE/3qtg4tr7f VgzY3nf5sP1mCzUDbv5Y2OX2V7Q48y6fVT5HTPVdWbhu8jO93FRc8ugoq WRwOL6817Xww4Chfz3aAAKnfcF3Ln7qpV5e8LZx9M1OsdMaJAOAMMAONn 558yFoUj1x8eeFo5LYIN7bpYrMOmSX5V5V61Bk3megRtx8i/kojDIS1AH 61RjmOrmkUFGI9buf1yG3y6wQmir2XPjBAeeS8+DElL4+PF0ro3Hw8uC9 w==; X-CSE-ConnectionGUID: DvSuCgjTTEyRsd2Cv82xgA== X-CSE-MsgGUID: 4MU3FU+EQB2HofvBCvtWkg== X-IronPort-AV: E=McAfee;i="6800,10657,11662"; a="69094115" X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="69094115" X-CSE-ConnectionGUID: SfHT7wt5SyS48Mn6Z3X05A== X-CSE-MsgGUID: jKxWHSzBTjq63iyzKmjZSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,204,1763452800"; d="scan'208";a="202589115" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v10 19/19] docs/devel: Add IOMMUFD nesting documentation Date: Tue, 6 Jan 2026 01:13:01 -0500 Message-ID: <20260106061304.314546-20-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260106061304.314546-1-zhenzhong.duan@intel.com> References: <20260106061304.314546-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add documentation about using IOMMUFD backed VFIO device with intel_iommu w= ith x-flts=3Don. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- docs/devel/vfio-iommufd.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/docs/devel/vfio-iommufd.rst b/docs/devel/vfio-iommufd.rst index 3d1c11f175..cbf59924ba 100644 --- a/docs/devel/vfio-iommufd.rst +++ b/docs/devel/vfio-iommufd.rst @@ -164,3 +164,20 @@ RAM discarding for mdev. =20 ``vfio-ap`` and ``vfio-ccw`` devices don't have same issue as their backend devices are always mdev and RAM discarding is force enabled. + +Usage with intel_iommu featuring x-flts=3Don +------------------------------------------ + +Only IOMMUFD backed VFIO device is supported when intel_iommu is configured +with x-flts=3Don, for legacy container backed VFIO device, below error sho= ws: + +.. code-block:: none + + qemu-system-x86_64: -device vfio-pci,host=3D0000:02:00.0: vfio 0000:02= :00.0: Failed to set vIOMMU: Need IOMMUFD backend when x-flts=3Don + +VFIO device under PCI bridge is unsupported, use PCIE bridge if necessary, +otherwise below error shows: + +.. code-block:: none + + qemu-system-x86_64: -device vfio-pci,host=3D0000:02:00.0,bus=3Dbridge1= ,iommufd=3Diommufd0: vfio 0000:02:00.0: Failed to set vIOMMU: Host device d= ownstream to a PCI bridge is unsupported when x-flts=3Don --=20 2.47.1