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If no kernel payload is provided to QEMU, the next stage address is NULL, and the riscv virt machine memory map ends up covering the 0 address with the catch all S-mode RWX region and so OpenSBI prints console messages and does not hang until the next stage boot. The TT Atlantis address map has RAM starting at 0 and it loads OpenSBI there, so it is M-mode and not accessible by S-mode, tripping the early check and hang. Add a helper to set up a simple payload that gets OpenSBI messages to console. Signed-off-by: Nicholas Piggin Signed-off-by: Joel Stanley --- include/hw/riscv/boot.h | 2 ++ hw/riscv/boot.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index e025162a77b1..d26302d3e987 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -78,6 +78,8 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RIS= CVHartArrayState *harts hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, uint64_t fdt_load_addr); +void riscv_setup_halting_payload(MachineState *machine, + RISCVBootInfo *info, hwaddr addr); void riscv_rom_copy_firmware_info(MachineState *machine, RISCVHartArrayState *harts, hwaddr rom_base, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 9f940c915620..3913bb1183f4 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -518,6 +518,27 @@ void riscv_setup_rom_reset_vec(MachineState *machine, = RISCVHartArrayState *harts kernel_entry); } =20 +/* Simple payload so OpenSBI does not hang early with no output */ +void riscv_setup_halting_payload(MachineState *machine, + RISCVBootInfo *info, hwaddr addr) +{ + int i; + uint32_t payload_vec[] =3D { + 0x10500073, /* 1: wfi */ + 0xffdff06f, /* j 1b */ + }; + /* copy in the payload vector in little_endian byte order */ + for (i =3D 0; i < ARRAY_SIZE(payload_vec); i++) { + payload_vec[i] =3D cpu_to_le32(payload_vec[i]); + } + rom_add_blob_fixed_as("mrom.payload", payload_vec, sizeof(payload_vec), + addr, &address_space_memory); + + info->kernel_size =3D sizeof(payload_vec); + info->image_low_addr =3D addr; + info->image_high_addr =3D info->image_low_addr + info->kernel_size; +} + void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) { CPUState *cs; --=20 2.47.3