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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617794; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VubRcQ92hC2orf+/hvxD67znU0vMNup3DnROyTxFHaw=; b=Bo0RGI3bcOkZED5xZ/CzUggbDshS4P/sqx6QdG9IaF7jegzDNBimd2wxga3x6plZpRhPop BUylsj08yWAeiv6OmJuXJ0wpBp0lBQrhgai20TujniXq4kHKIDasMV3JDzMN5U0qR08yEd N+LJZ0Wj8U/N2WVI5v+yJR474Inl5kc= X-MC-Unique: vnGpVYs9Mc6jKB3AwawyLQ-1 X-Mimecast-MFC-AGG-ID: vnGpVYs9Mc6jKB3AwawyLQ_1767617791 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 07/36] hw/arm/aspeed_ast10x0: Add AST1060 SoC support Date: Mon, 5 Jan 2026 13:55:44 +0100 Message-ID: <20260105125613.622667-8-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617958770154100 From: Jamin Lin Add initial support for the Aspeed AST1060 SoC. The AST1060 reuses most of the AST1030 peripheral device models, as the two SoCs share nearly the same controllers including WDT, SCU, TIMER, HACE, ADC, I2C, FMC, and SPI. A new common initialization and realization framework (ast10x0_init and ast10x0_realize) is leveraged so AST1060 can instantiate the existing AST1030 models without redefining duplicate device types. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-9-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 59 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 4ed6649e5546..44e1d59ddb3c 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -185,6 +185,23 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); } =20 +static void aspeed_soc_ast1060_init(Object *obj) +{ + /* + * The AST1060 SoC reuses the AST1030 device models. Since all periphe= ral + * models (e.g. WDT, SCU, TIMER, HACE, ADC, I2C, FMC, SPI) defined for + * AST1030 are compatible with AST1060, we simply reuse the existing + * AST1030 models for AST1060. + * + * To simplify the implementation, AST1060 sets its socname to that of + * AST1030, avoiding the need to create a full set of new + * TYPE_ASPEED_1060_XXX device definitions. This allows the same + * TYPE_ASPEED_1030_WDT and other models to be instantiated for both + * SoCs. + */ + aspeed_soc_ast10x0_init(obj, "ast1030"); +} + static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp) { AspeedSoCState *s =3D ASPEED_SOC(a); @@ -451,6 +468,15 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); } =20 +static void aspeed_soc_ast1060_realize(DeviceState *dev_soc, Error **errp) +{ + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); + + if (!aspeed_soc_ast10x0_realize(a, errp)) { + return; + } +} + static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *= data) { static const char * const valid_cpu_types[] =3D { @@ -479,6 +505,32 @@ static void aspeed_soc_ast1030_class_init(ObjectClass = *klass, const void *data) sc->num_cpus =3D 1; } =20 +static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *= data) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); + + /* Reason: The Aspeed SoC can only be instantiated from a board */ + dc->user_creatable =3D false; + dc->realize =3D aspeed_soc_ast1060_realize; + + sc->valid_cpu_types =3D valid_cpu_types; + sc->silicon_rev =3D AST1060_A2_SILICON_REV; + sc->sram_size =3D 0xc0000; + sc->secsram_size =3D 0x40000; /* 256 * KiB */ + sc->spis_num =3D 2; + sc->wdts_num =3D 4; + sc->uarts_num =3D 1; + sc->uarts_base =3D ASPEED_DEV_UART5; + sc->irqmap =3D aspeed_soc_ast1030_irqmap; + sc->memmap =3D aspeed_soc_ast1030_memmap; + sc->num_cpus =3D 1; +} + static const TypeInfo aspeed_soc_ast10x0_types[] =3D { { .name =3D TYPE_ASPEED10X0_SOC, @@ -490,7 +542,12 @@ static const TypeInfo aspeed_soc_ast10x0_types[] =3D { .parent =3D TYPE_ASPEED10X0_SOC, .instance_init =3D aspeed_soc_ast1030_init, .class_init =3D aspeed_soc_ast1030_class_init, - }, + }, { + .name =3D "ast1060-a2", + .parent =3D TYPE_ASPEED10X0_SOC, + .instance_init =3D aspeed_soc_ast1060_init, + .class_init =3D aspeed_soc_ast1060_class_init, + } }; =20 DEFINE_TYPES(aspeed_soc_ast10x0_types) --=20 2.52.0