From nobody Mon Feb 9 19:06:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767617985; cv=none; d=zohomail.com; s=zohoarc; b=mnVaCwDLjy7w1re1FF1xAt3gMOoYM3jLS1b3FUDs72cXHVkKUduxlMe7xM+MI/ZfcjgLLuF38KbxLdQXAzHDC4jNc8DxVW9yz8jIPhBjRsUU4Oxw+Y2vTTyrhlEeO1wf4yL1Tv6vgjLzG6zSx16mrXVawotmzk+R6+CnQ2mxLgk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767617985; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JCqeB5q4nk1qZZKh3AiuHmU774j78tSilI9/XgQofrQ=; b=Ro2lSbkuF4NXrcBppv15pp2kjJbHfQOBttC5slgnLBv2q1Jsx67xXgt+nd/Z2oQ+SHBDDAZoFMrAcyPUnRqfJHWQatSOkBufNbjIvq8IOgMGg4XQqdkdqoU0tK4wJE+F4wyIVhJ/Sm2sxGHaCo0yiWwQS8dm1wpS6xI5+s0Zp5A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767617985493223.78241927029023; Mon, 5 Jan 2026 04:59:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vck8i-0003uD-3E; Mon, 05 Jan 2026 07:56:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vck8Q-0003mL-Hj for qemu-devel@nongnu.org; Mon, 05 Jan 2026 07:56:34 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vck8O-0007w2-Dh for qemu-devel@nongnu.org; Mon, 05 Jan 2026 07:56:34 -0500 Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-510-voe8wOatMe6uHFnH72c_Uw-1; Mon, 05 Jan 2026 07:56:28 -0500 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id AA1011800610; Mon, 5 Jan 2026 12:56:27 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 200BB19560A7; Mon, 5 Jan 2026 12:56:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617791; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JCqeB5q4nk1qZZKh3AiuHmU774j78tSilI9/XgQofrQ=; b=AfzKWjEHwCxH9hgVB2VYsotZhx3I3TgB1NZMxC1aHKaIlSPn0xme1aGz/dTklYKRvns6S+ 8LX3rxTH8Bw3iWu3ZGapJCMhDUK23r+y87dGIQbMcn7uKxPvvqiw46pCi97+7qqlVSvzSm 5GSqIp9FrzwITluM5fTgef8yBO5MMTw= X-MC-Unique: voe8wOatMe6uHFnH72c_Uw-1 X-Mimecast-MFC-AGG-ID: voe8wOatMe6uHFnH72c_Uw_1767617787 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 05/36] hw/arm/aspeed_ast10x0: Add common realize function for AST10x0 SoCs Date: Mon, 5 Jan 2026 13:55:42 +0100 Message-ID: <20260105125613.622667-6-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617987133154100 From: Jamin Lin Introduce a new common realize function aspeed_soc_ast10x0_realize() for AST10x0 series SoCs. The shared initialization and realization logic is now placed in this common function to improve code reuse and reduce duplication between different SoCs in the same family. The AST1030 realization function aspeed_soc_ast1030_realize() is updated to call the new common routine and then perform realization of its own specific devices such as LPC and PECI, which are not present on future SoCs like AST1060. This refactor simplifies maintenance and prepares the framework for adding AST1060 support. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-7-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 128 ++++++++++++++++++++++------------------ 1 file changed, 70 insertions(+), 58 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 1dd1a95ea5bd..72a8c78ff890 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -190,10 +190,9 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); } =20 -static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) +static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp) { - Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); - AspeedSoCState *s =3D ASPEED_SOC(dev_soc); + AspeedSoCState *s =3D ASPEED_SOC(a); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; Error *err =3D NULL; @@ -203,7 +202,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 if (!clock_has_source(s->sysclk)) { error_setg(errp, "sysclk clock must be wired up by the board code"= ); - return; + return false; } =20 /* General I/O memory space to catch all unimplemented device */ @@ -216,7 +215,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC], 0x40000); =20 - /* AST1030 CPU Core */ + /* AST10x0 CPU Core */ armv7m =3D DEVICE(&a->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 256); qdev_prop_set_string(armv7m, "cpu-type", @@ -232,7 +231,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, = &err); if (err !=3D NULL) { error_propagate(errp, err); - return; + return false; } memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], @@ -241,14 +240,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) sc->secsram_size, &err); if (err !=3D NULL) { error_propagate(errp, err); - return; + return false; } memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM], &s->secsram); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); @@ -258,7 +257,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); @@ -271,7 +270,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* I3C */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); @@ -282,50 +281,11 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); } =20 - /* PECI */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, - sc->memmap[ASPEED_DEV_PECI]); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, - aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI)); - - /* LPC */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, - sc->memmap[ASPEED_DEV_LPC]); - - /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, - aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC)); - - /* - * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. - */ - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_1)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_2)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_3)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); - /* UART */ for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], sc->memmap[uart], errp)) { - return; + return false; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, aspeed_soc_ast1030_get_irq(s, uart)); @@ -335,7 +295,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); @@ -346,7 +306,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* ADC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); @@ -357,7 +317,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); @@ -371,7 +331,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->spi[i]), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0, sc->memmap[ASPEED_DEV_SPI1 + i]); @@ -383,7 +343,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* Secure Boot Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); @@ -392,7 +352,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); @@ -407,14 +367,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offs= et); } =20 /* GPIO */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); @@ -442,6 +402,58 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag", sc->memmap[ASPEED_DEV_JTAG1], 0x20); + + return true; +} + +static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) +{ + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); + AspeedSoCState *s =3D ASPEED_SOC(dev_soc); + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + + if (!aspeed_soc_ast10x0_realize(a, errp)) { + return; + } + + /* PECI */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, + sc->memmap[ASPEED_DEV_PECI]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI)); + + /* LPC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, + sc->memmap[ASPEED_DEV_LPC]); + + /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC)); + + /* + * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. + */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_1)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_2)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_3)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); } =20 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *= data) --=20 2.52.0