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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617788; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yJv6P0qh9N/6zxyMRpI9aJZHDQPwnl5DoZNIDIl/Wqw=; b=GT751VG7m5T2SrzAp62NOmDufvMuU5Wird0qw1JHSX90ZMfBLlQ03lGhCRQeMpsLNVoR9r TMEEgoHOZhKS9efxymF+SdotR31I+e2TSM7Vz2kJEDceT5RZ8mtT2Ia2A2bsJKy7Q34kBm YfkmrBbGq0MPiv49pXHhVYMvdbuGABs= X-MC-Unique: JEWB8uXyOgmswZoA3vYyFg-1 X-Mimecast-MFC-AGG-ID: JEWB8uXyOgmswZoA3vYyFg_1767617783 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/36] hhw/misc/aspeed_scu: Add AST1060 A2 silicon revision definition Date: Mon, 5 Jan 2026 13:55:40 +0100 Message-ID: <20260105125613.622667-4-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617853176154100 From: Jamin Lin Add a new silicon revision constant AST1060_A2_SILICON_REV for the AST1060 SoC. This allows the SCU model and related SoC layers to identify and handle AST1060 A2 revision properly in the same way as other Aspeed SoC families. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-5-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/misc/aspeed_scu.h | 1 + hw/misc/aspeed_scu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 35b841960af0..9e28bd4d2e1a 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -51,6 +51,7 @@ struct AspeedSCUState { #define AST2600_A3_SILICON_REV 0x05030303U #define AST1030_A0_SILICON_REV 0x80000000U #define AST1030_A1_SILICON_REV 0x80010000U +#define AST1060_A2_SILICON_REV 0xA0030000U #define AST2700_A0_SILICON_REV 0x06000103U #define AST2720_A0_SILICON_REV 0x06000203U #define AST2750_A0_SILICON_REV 0x06000003U diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 5bc0b3536f28..6829efa2dcd4 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -565,6 +565,7 @@ static uint32_t aspeed_silicon_revs[] =3D { AST2600_A3_SILICON_REV, AST1030_A0_SILICON_REV, AST1030_A1_SILICON_REV, + AST1060_A2_SILICON_REV, AST2700_A0_SILICON_REV, AST2720_A0_SILICON_REV, AST2750_A0_SILICON_REV, --=20 2.52.0