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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617786; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RyNMoQ9h8mGT+ujBZwuHSSISd4Tl8lptuCjs7agnXO8=; b=S4d7wfKW6SrMs1Wm9VB+n5wIW4r0ZPMRTQZk9iecykx4LezYkwOQCvasfzHF7ovSTnO2JH N56xAqqlGYxoPhTl760m3iRNyrk32FU0gK7B4F50tbz0Cb98kY+3sc9Za1QX/hxO0Meqjx K2RatLwnTVwBdV7mXGb45OMTE3DzjWo= X-MC-Unique: MSVmLuNaO4ilv6J_aIPeZA-1 X-Mimecast-MFC-AGG-ID: MSVmLuNaO4ilv6J_aIPeZA_1767617782 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 02/36] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2600 and AST1030 Date: Mon, 5 Jan 2026 13:55:39 +0100 Message-ID: <20260105125613.622667-3-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767632383216158500 From: Jamin Lin According to the design of the AST2600, it has a Silicon Revision ID Register, specifically SCU004 and SCU014, to set the Revision ID for the AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303. In the "aspeed_ast2600_scu_reset" function, the hardcoded value "AST2600_A3_SILICON_REV" was used for SCU004, while "s->silicon_rev" was used for SCU014. The value of "s->silicon_rev" is set by the SoC layer via the "silicon-rev" property. This patch aligns both SCU004 and SCU014 to use "s->silicon_rev" for consistency and flexibility. Similarly, the "aspeed_ast1030_scu_reset" function also used a fixed revision constant ("AST1030_A1_SILICON_REV"). This change updates it to use the same "s->silicon_rev" property, ensuring that both SoCs follow a consistent and configurable revision handling mechanism. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-4-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index d27e0c7f9158..5bc0b3536f28 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -841,7 +841,7 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev) * of actual revision. QEMU and Linux only support A1 onwards so this = is * sufficient. */ - s->regs[AST2600_SILICON_REV] =3D AST2600_A3_SILICON_REV; + s->regs[AST2600_SILICON_REV] =3D s->silicon_rev; s->regs[AST2600_SILICON_REV2] =3D s->silicon_rev; s->regs[AST2600_HW_STRAP1] =3D s->hw_strap1; s->regs[AST2600_HW_STRAP2] =3D s->hw_strap2; @@ -1137,7 +1137,7 @@ static void aspeed_ast1030_scu_reset(DeviceState *dev) =20 memcpy(s->regs, asc->resets, asc->nr_regs * 4); =20 - s->regs[AST2600_SILICON_REV] =3D AST1030_A1_SILICON_REV; + s->regs[AST2600_SILICON_REV] =3D s->silicon_rev; s->regs[AST2600_SILICON_REV2] =3D s->silicon_rev; s->regs[AST2600_HW_STRAP1] =3D s->hw_strap1; s->regs[AST2600_HW_STRAP2] =3D s->hw_strap2; --=20 2.52.0