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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617838; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WywNb9c2fzJnvtKkFHYliMsQCyp82+NRD4M44Nd+htY=; b=c9cXtf/1IZ/drOIRlFR9USWeK9DQAg3RUkZy6UVfFtCeOZ4uWDr0LgR5ZXLYEpF7D5GXDv 8OuCiRRpeeUE7qb/Wmr4VeDVapXM2nTT3a1Ar1N9yKLuTSCBC8bOYhVUV+MHYwz5DWMnGr 55xq/WUj2hleb6p/xY8MrRK55O4B+KM= X-MC-Unique: _SqLYMxOMraM71N3DFSSZg-1 X-Mimecast-MFC-AGG-ID: _SqLYMxOMraM71N3DFSSZg_1767617835 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yubin Zou , Kane Chen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 28/36] test/qtest: Add Unit test for Aspeed SGPIO Date: Mon, 5 Jan 2026 13:56:05 +0100 Message-ID: <20260105125613.622667-29-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620561100154100 From: Yubin Zou This commit introduces a new qtest for the Aspeed SGPIO controller The test covers the following: - Setting and clearing SGPIO output pins and verifying the pin state. - Setting and clearing SGPIO input pins and verifying the pin state. - Verifying that level-high interrupts are correctly triggered and cleare= d. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-6-fd55931= 78144@google.com Signed-off-by: C=C3=A9dric Le Goater --- tests/qtest/ast2700-sgpio-test.c | 165 +++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 166 insertions(+) create mode 100644 tests/qtest/ast2700-sgpio-test.c diff --git a/tests/qtest/ast2700-sgpio-test.c b/tests/qtest/ast2700-sgpio-t= est.c new file mode 100644 index 000000000000..56c54cca9b63 --- /dev/null +++ b/tests/qtest/ast2700-sgpio-test.c @@ -0,0 +1,165 @@ +/* + * QTest testcase for the ASPEED AST2700 SGPIO Controller. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2025 Google LLC. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qobject/qdict.h" +#include "libqtest-single.h" +#include "hw/core/registerfields.h" +#include "hw/gpio/aspeed_sgpio.h" + +#define AST2700_SGPIO0_BASE 0x14C0C000 +#define AST2700_SGPIO1_BASE 0x14C0D000 + +static void test_output_pins(const char *machine, const uint32_t base, int= idx) +{ + QTestState *s =3D qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t offset =3D 0; + uint32_t value =3D 0; + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Odd index is output port */ + sprintf(name, "sgpio%03d", i * 2 + 1); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + offset =3D base + (R_SGPIO_0_CONTROL + i) * 4; + /* set serial output */ + qtest_writel(s, offset, 0x00000001); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), = =3D=3D, 1); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, tru= e); + + /* clear serial output */ + qtest_writel(s, offset, 0x00000000); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), = =3D=3D, 0); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, fal= se); + } + qtest_quit(s); +} + +static void test_input_pins(const char *machine, const uint32_t base, int = idx) +{ + QTestState *s =3D qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t offset =3D 0; + uint32_t value =3D 0; + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Even index is input port */ + sprintf(name, "sgpio%03d", i * 2); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + offset =3D base + (R_SGPIO_0_CONTROL + i) * 4; + /* set serial input */ + qtest_qom_set_bool(s, qom_path, name, true); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 1); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, tru= e); + + /* clear serial input */ + qtest_qom_set_bool(s, qom_path, name, false); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 0); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, fal= se); + } + qtest_quit(s); +} + +static void test_irq_level_high(const char *machine, + const uint32_t base, int idx) +{ + QTestState *s =3D qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t ctrl_offset =3D 0; + uint32_t int_offset =3D 0; + uint32_t int_reg_idx =3D 0; + uint32_t int_bit_idx =3D 0; + uint32_t value =3D 0; + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Even index is input port */ + sprintf(name, "sgpio%03d", i * 2); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + int_reg_idx =3D i / 32; + int_bit_idx =3D i % 32; + int_offset =3D base + (R_SGPIO_INT_STATUS_0 + int_reg_idx) * 4; + ctrl_offset =3D base + (R_SGPIO_0_CONTROL + i) * 4; + + /* Enable the interrupt */ + value =3D SHARED_FIELD_DP32(value, SGPIO_INT_EN, 1); + qtest_writel(s, ctrl_offset, value); + + /* Set the interrupt type to level-high trigger */ + value =3D SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), + SGPIO_INT_TYPE, 3); + qtest_writel(s, ctrl_offset, value); + + /* Set serial input high */ + qtest_qom_set_bool(s, qom_path, name, true); + value =3D qtest_readl(s, ctrl_offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 1); + + /* Interrupt status is set */ + value =3D qtest_readl(s, int_offset); + g_assert_cmphex(extract32(value, int_bit_idx, 1), =3D=3D, 1); + + /* Clear Interrupt */ + value =3D SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), + SGPIO_INT_STATUS, 1); + qtest_writel(s, ctrl_offset, value); + value =3D qtest_readl(s, int_offset); + g_assert_cmphex(extract32(value, int_bit_idx, 1), =3D=3D, 0); + + /* Clear serial input */ + qtest_qom_set_bool(s, qom_path, name, false); + value =3D qtest_readl(s, ctrl_offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 0); + } + qtest_quit(s); +} + +static void test_ast_2700_sgpio_input(void) +{ + test_input_pins("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_input_pins("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +static void test_ast_2700_sgpio_output(void) +{ + test_output_pins("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_output_pins("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +static void test_ast_2700_sgpio_irq(void) +{ + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_input", + test_ast_2700_sgpio_input); + qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_output", + test_ast_2700_sgpio_output); + qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_irq", + test_ast_2700_sgpio_irq); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 08fba9695b98..0f053fb56de5 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -221,6 +221,7 @@ qtests_aspeed =3D \ qtests_aspeed64 =3D \ ['ast2700-gpio-test', 'ast2700-hace-test', + 'ast2700-sgpio-test', 'ast2700-smc-test'] =20 qtests_stm32l4x5 =3D \ --=20 2.52.0