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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617836; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2eN4X3uyfV9cJriJXGMysA4V49qLGAdRFXwkwfMgEWE=; b=ZAeN44N8p9wnHBqH2u1ZeLADO98C9OOWcahd5YG/NjyDbdNaKd+pYJufiaNRKaKyZINdc5 P5yKqMIJ/Hc33vyV45gaT9J8aaqAiJuTtn4VscjsOBATqdzCWRzEmsaVWkjbsa0JFYYiei WE2FjEt68kCbcpTIUJNxg3m9EvreAX0= X-MC-Unique: WwKwJ853MMCFq-PbYxOElg-1 X-Mimecast-MFC-AGG-ID: WwKwJ853MMCFq-PbYxOElg_1767617831 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yubin Zou , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 26/36] hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers Date: Mon, 5 Jan 2026 13:56:03 +0100 Message-ID: <20260105125613.622667-27-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620350038154100 From: Yubin Zou This commit updates the Aspeed SoC model to support two SGPIO controllers, reflecting the hardware capabilities of the AST2700 The memory map and interrupt map are updated to include entries for two SGPIO controllers (SGPIOM0 and SGPIOM1). This change is a prerequisite for the full implementation of the SGPIO device model. Signed-off-by: Yubin Zou Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-4-fd55931= 78144@google.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 8 ++++++-- hw/arm/aspeed_ast10x0.c | 6 +++--- hw/arm/aspeed_ast27x0.c | 10 ++++++++++ 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 4b8e599f1a53..18ff961a3850 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -32,6 +32,7 @@ #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" #include "hw/gpio/aspeed_gpio.h" +#include "hw/gpio/aspeed_sgpio.h" #include "hw/sd/aspeed_sdhci.h" #include "hw/usb/hcd-ehci.h" #include "qom/object.h" @@ -46,6 +47,7 @@ #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 #define ASPEED_SPIS_NUM 3 +#define ASPEED_SGPIO_NUM 2 #define ASPEED_EHCIS_NUM 4 #define ASPEED_WDTS_NUM 8 #define ASPEED_CPUS_NUM 4 @@ -89,6 +91,7 @@ struct AspeedSoCState { AspeedMiiState mii[ASPEED_MACS_NUM]; AspeedGPIOState gpio; AspeedGPIOState gpio_1_8v; + AspeedSGPIOState sgpiom[ASPEED_SGPIO_NUM]; AspeedSDHCIState sdhci; AspeedSDHCIState emmc; AspeedLPCState lpc; @@ -106,7 +109,6 @@ struct AspeedSoCState { UnimplementedDeviceState pwm; UnimplementedDeviceState espi; UnimplementedDeviceState udc; - UnimplementedDeviceState sgpiom; UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; @@ -166,6 +168,7 @@ struct AspeedSoCClass { uint64_t secsram_size; int pcie_num; int spis_num; + int sgpio_num; int ehcis_num; int wdts_num; int macs_num; @@ -221,6 +224,8 @@ enum { ASPEED_DEV_SDHCI, ASPEED_DEV_GPIO, ASPEED_DEV_GPIO_1_8V, + ASPEED_DEV_SGPIOM0, + ASPEED_DEV_SGPIOM1, ASPEED_DEV_RTC, ASPEED_DEV_TIMER1, ASPEED_DEV_TIMER2, @@ -263,7 +268,6 @@ enum { ASPEED_DEV_I3C, ASPEED_DEV_ESPI, ASPEED_DEV_UDC, - ASPEED_DEV_SGPIOM, ASPEED_DEV_JTAG0, ASPEED_DEV_JTAG1, ASPEED_DEV_FSI1, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 44e1d59ddb3c..41a4e82c1f87 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -36,7 +36,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] =3D { [ASPEED_DEV_ESPI] =3D 0x7E6EE000, [ASPEED_DEV_SBC] =3D 0x7E6F2000, [ASPEED_DEV_GPIO] =3D 0x7E780000, - [ASPEED_DEV_SGPIOM] =3D 0x7E780500, + [ASPEED_DEV_SGPIOM0] =3D 0x7E780500, [ASPEED_DEV_TIMER1] =3D 0x7E782000, [ASPEED_DEV_UART1] =3D 0x7E783000, [ASPEED_DEV_UART2] =3D 0x7E78D000, @@ -94,7 +94,7 @@ static const int aspeed_soc_ast1030_irqmap[] =3D { [ASPEED_DEV_I2C] =3D 110, /* 110 ~ 123 */ [ASPEED_DEV_KCS] =3D 138, /* 138 -> 142 */ [ASPEED_DEV_UDC] =3D 9, - [ASPEED_DEV_SGPIOM] =3D 51, + [ASPEED_DEV_SGPIOM0] =3D 51, [ASPEED_DEV_JTAG0] =3D 27, [ASPEED_DEV_JTAG1] =3D 53, }; @@ -406,7 +406,7 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCSta= te *a, Error **errp) sc->memmap[ASPEED_DEV_UDC], 0x1000); aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom", - sc->memmap[ASPEED_DEV_SGPIOM], 0x100); + sc->memmap[ASPEED_DEV_SGPIOM0], 0x100); =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag", diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 95f155fcf1ad..9f471c399491 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -69,6 +69,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_ADC] =3D 0x14C00000, [ASPEED_DEV_SCUIO] =3D 0x14C02000, [ASPEED_DEV_GPIO] =3D 0x14C0B000, + [ASPEED_DEV_SGPIOM0] =3D 0x14C0C000, + [ASPEED_DEV_SGPIOM1] =3D 0x14C0D000, [ASPEED_DEV_I2C] =3D 0x14C0F000, [ASPEED_DEV_INTCIO] =3D 0x14C18000, [ASPEED_DEV_PCIE_PHY2] =3D 0x14C1C000, @@ -122,6 +124,8 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D { [ASPEED_DEV_KCS] =3D 128, [ASPEED_DEV_ADC] =3D 130, [ASPEED_DEV_GPIO] =3D 130, + [ASPEED_DEV_SGPIOM0] =3D 130, + [ASPEED_DEV_SGPIOM1] =3D 130, [ASPEED_DEV_I2C] =3D 130, [ASPEED_DEV_FMC] =3D 131, [ASPEED_DEV_WDT] =3D 131, @@ -173,6 +177,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_I2C] =3D 194, [ASPEED_DEV_ADC] =3D 194, [ASPEED_DEV_GPIO] =3D 194, + [ASPEED_DEV_SGPIOM0] =3D 194, + [ASPEED_DEV_SGPIOM1] =3D 194, [ASPEED_DEV_FMC] =3D 195, [ASPEED_DEV_WDT] =3D 195, [ASPEED_DEV_PWM] =3D 195, @@ -214,6 +220,8 @@ static const int ast2700_gic130_gic194_intcmap[] =3D { [ASPEED_DEV_I2C] =3D 0, [ASPEED_DEV_ADC] =3D 16, [ASPEED_DEV_GPIO] =3D 18, + [ASPEED_DEV_SGPIOM0] =3D 21, + [ASPEED_DEV_SGPIOM1] =3D 24, }; =20 /* GICINT 131 */ @@ -1063,6 +1071,7 @@ static void aspeed_soc_ast2700a0_class_init(ObjectCla= ss *oc, const void *data) sc->sram_size =3D 0x20000; sc->pcie_num =3D 0; sc->spis_num =3D 3; + sc->sgpio_num =3D 2; sc->ehcis_num =3D 2; sc->wdts_num =3D 8; sc->macs_num =3D 1; @@ -1091,6 +1100,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->sram_size =3D 0x20000; sc->pcie_num =3D 3; sc->spis_num =3D 3; + sc->sgpio_num =3D 2; sc->ehcis_num =3D 4; sc->wdts_num =3D 8; sc->macs_num =3D 3; --=20 2.52.0