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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617831; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ODD8+M+lXInDffmXAIyevk2C2JoBR0MtSv17yxCG0us=; b=YPi6xwdDRf1MtKTG1aEt1p3TOjSiKOXYPrpbd7UH8sZiDTIlCVOe7ptI6pd8MSZtl/Ot/P 54FWKV3ottQCn08Ikvwlzy5cdKMtspTWN43PjEZoi0Wr4FwNr56SHXSV0OGdqKHo4vmnZD /jgcD/a0pTaWnnwO3NvQGgIjjywfJUc= X-MC-Unique: FhG-ZahnOxK5uph1xfKpeQ-1 X-Mimecast-MFC-AGG-ID: FhG-ZahnOxK5uph1xfKpeQ_1767617826 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yubin Zou , Kane Chen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 24/36] hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins Date: Mon, 5 Jan 2026 13:56:01 +0100 Message-ID: <20260105125613.622667-25-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617983150154100 From: Yubin Zou The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are implemented to get and set the level of individual SGPIO pins. These are then exposed as boolean properties on the SGPIO device object. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-2-fd55931= 78144@google.com Signed-off-by: C=C3=A9dric Le Goater --- hw/gpio/aspeed_sgpio.c | 79 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c index 538fb5145c3d..cf5efa70e8d0 100644 --- a/hw/gpio/aspeed_sgpio.c +++ b/hw/gpio/aspeed_sgpio.c @@ -51,6 +51,8 @@ static uint64_t aspeed_sgpio_2700_read(void *opaque, hwad= dr offset, reg =3D offset >> 2; =20 switch (reg) { + case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7: + break; case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: value =3D aspeed_sgpio_2700_read_control_reg(s, reg); break; @@ -82,6 +84,73 @@ static void aspeed_sgpio_2700_write(void *opaque, hwaddr= offset, uint64_t data, } } =20 +static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin) +{ + uint32_t value =3D s->ctrl_regs[pin >> 1]; + bool is_input =3D !(pin % 2); + uint32_t bit_mask =3D 0; + + if (is_input) { + bit_mask =3D SGPIO_SERIAL_IN_VAL_MASK; + } else { + bit_mask =3D SGPIO_SERIAL_OUT_VAL_MASK; + } + + return value & bit_mask; +} + +static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, bool = level) +{ + uint32_t value =3D s->ctrl_regs[pin >> 1]; + bool is_input =3D !(pin % 2); + uint32_t bit_mask =3D 0; + + if (is_input) { + bit_mask =3D SGPIO_SERIAL_IN_VAL_MASK; + } else { + bit_mask =3D SGPIO_SERIAL_OUT_VAL_MASK; + } + + if (level) { + value |=3D bit_mask; + } else { + value &=3D ~bit_mask; + } + s->ctrl_regs[pin >> 1] =3D value; +} + +static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool level =3D true; + int pin =3D 0xfff; + AspeedSGPIOState *s =3D ASPEED_SGPIO(obj); + + if (sscanf(name, "sgpio%03d", &pin) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + level =3D aspeed_sgpio_get_pin_level(s, pin); + visit_type_bool(v, name, &level, errp); +} + +static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool level; + int pin =3D 0xfff; + AspeedSGPIOState *s =3D ASPEED_SGPIO(obj); + + if (!visit_type_bool(v, name, &level, errp)) { + return; + } + if (sscanf(name, "sgpio%03d", &pin) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + aspeed_sgpio_set_pin_level(s, pin, level); +} + static const MemoryRegionOps aspeed_sgpio_2700_ops =3D { .read =3D aspeed_sgpio_2700_read, .write =3D aspeed_sgpio_2700_write, @@ -105,6 +174,15 @@ static void aspeed_sgpio_realize(DeviceState *dev, Err= or **errp) sysbus_init_mmio(sbd, &s->iomem); } =20 +static void aspeed_sgpio_init(Object *obj) +{ + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) { + g_autofree char *name =3D g_strdup_printf("sgpio%03d", i); + object_property_add(obj, name, "bool", aspeed_sgpio_get_pin, + aspeed_sgpio_set_pin, NULL, NULL); + } +} + static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -134,6 +212,7 @@ static const TypeInfo aspeed_sgpio_ast2700_info =3D { .name =3D TYPE_ASPEED_SGPIO "-ast2700", .parent =3D TYPE_ASPEED_SGPIO, .class_init =3D aspeed_sgpio_2700_class_init, + .instance_init =3D aspeed_sgpio_init, }; =20 static void aspeed_sgpio_register_types(void) --=20 2.52.0