From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767617836; cv=none; d=zohomail.com; s=zohoarc; b=V0MpilNlVjAoZLZQA+RfB/OHH3Qt9XzalMNY32X24ekQpYkn5ZdjaZ6EkZyYigY+4AeC5ht0qJN+Fj8jkiRc9GgTg0VDS5h8yjCqZS8SfmaSU6j389/Ad+Vrj5KyzLQVXIsCMD7wc+50KqZlDro+rgN8N0TfOLavZAC77lfIPXo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767617836; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YVC0io8V1/7I6Ovz7Uc7Z6X6LdwYayG3/6XfBBUwGQo=; b=GJ9N+l36A22flD9SFNfnd30VzekUZi9pZGwYgE3FOOEzya+jYMGs/Xb6xWE3mCos/GtqGYRzPDzoCU1FaUjMpGwlIS5F5b8XTC94fGttQmPAjPbjqOtAej8q6e5vcHi8RVBX2hbKdxGtWZo8+YE5x2EDQwjBXJUSxiI/UmosW4E= ARC-Authentication-Results: i=1; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617782; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YVC0io8V1/7I6Ovz7Uc7Z6X6LdwYayG3/6XfBBUwGQo=; b=FsPooHYkAW1T953orjsaBU1OKE1xKOqX5SRvsWSwYRyMtSWxFRTibmQ8xCjrKfrWH43dvS /IkELTW61I7yC1GFCUcoP0NhAdM0Z5zKrPqhe988/1URkq23BiodMZ0thQ9EbsPKJKgQ39 PgKgO/2lsnFp+Jc1AA/nMBJ+bWi/U5E= X-MC-Unique: FuazBHxzNaK7bVrur4cIvg-1 X-Mimecast-MFC-AGG-ID: FuazBHxzNaK7bVrur4cIvg_1767617780 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 01/36] hw/block/m25p80: Add SFDP table for Winbond W25Q02JVM flash Date: Mon, 5 Jan 2026 13:55:38 +0100 Message-ID: <20260105125613.622667-2-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617839156154100 From: Jamin Lin Add the SFDP data table for Winbond W25Q02JVM flash device. The table was generated under Linux kernel by dumping the SFDP content using the following command: ``` hexdump -v -e '8/1 "0x%02x, " "\n"' \ /sys/bus/spi/devices/spi0.0/spi-nor/sfdp ``` Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-3-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/block/m25p80_sfdp.h | 1 + hw/block/m25p80.c | 2 ++ hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h index 35785686a0ec..c1e532de5aeb 100644 --- a/hw/block/m25p80_sfdp.h +++ b/hw/block/m25p80_sfdp.h @@ -27,6 +27,7 @@ uint8_t m25p80_sfdp_w25q256(uint32_t addr); uint8_t m25p80_sfdp_w25q512jv(uint32_t addr); uint8_t m25p80_sfdp_w25q80bl(uint32_t addr); uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr); +uint8_t m25p80_sfdp_w25q02jvm(uint32_t addr); =20 uint8_t m25p80_sfdp_is25wp256(uint32_t addr); =20 diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 4a758f83dc7c..b8a2543c0bdc 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -364,6 +364,8 @@ static const FlashPartInfo known_devices[] =3D { .sfdp_read =3D m25p80_sfdp_w25q512jv }, { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K), .sfdp_read =3D m25p80_sfdp_w25q01jvq }, + { INFO("w25q02jvm", 0xef7022, 0, 64 << 10, 4096, ER_4K), + .sfdp_read =3D m25p80_sfdp_w25q02jvm }, =20 /* Microchip */ { INFO("25csm04", 0x29cc00, 0x100, 64 << 10, 8, 0) }, diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c index a03a291a09b5..87878c2bf0fa 100644 --- a/hw/block/m25p80_sfdp.c +++ b/hw/block/m25p80_sfdp.c @@ -440,6 +440,42 @@ static const uint8_t sfdp_w25q80bl[] =3D { }; define_sfdp_read(w25q80bl); =20 +static const uint8_t sfdp_w25q02jvm[] =3D { + 0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff, + 0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff, + 0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff, + 0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x7f, + 0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, + 0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52, + 0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00, + 0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33, + 0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c, + 0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +}; +define_sfdp_read(w25q02jvm); + /* * Integrated Silicon Solution (ISSI) */ --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767632381; cv=none; d=zohomail.com; s=zohoarc; b=Tt5AC1rdMptYmNOwRv8jdAwXNl346i12iBCT4GfvYPe3SdY0xUVL72sgwlYBuTHPm6qYfefDEHlgYuSOxjY/yYEKbvhoVOnmrVMS4407wymZEhDc6/lnNKqbDQZSXRCpY6gPp8Yw7ZIsdw8yDNA7M+1ueMd6JHw1rCj3QKQL0V4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767632381; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 5 Jan 2026 12:56:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617786; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RyNMoQ9h8mGT+ujBZwuHSSISd4Tl8lptuCjs7agnXO8=; b=S4d7wfKW6SrMs1Wm9VB+n5wIW4r0ZPMRTQZk9iecykx4LezYkwOQCvasfzHF7ovSTnO2JH N56xAqqlGYxoPhTl760m3iRNyrk32FU0gK7B4F50tbz0Cb98kY+3sc9Za1QX/hxO0Meqjx K2RatLwnTVwBdV7mXGb45OMTE3DzjWo= X-MC-Unique: MSVmLuNaO4ilv6J_aIPeZA-1 X-Mimecast-MFC-AGG-ID: MSVmLuNaO4ilv6J_aIPeZA_1767617782 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 02/36] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2600 and AST1030 Date: Mon, 5 Jan 2026 13:55:39 +0100 Message-ID: <20260105125613.622667-3-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767632383216158500 From: Jamin Lin According to the design of the AST2600, it has a Silicon Revision ID Register, specifically SCU004 and SCU014, to set the Revision ID for the AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303. In the "aspeed_ast2600_scu_reset" function, the hardcoded value "AST2600_A3_SILICON_REV" was used for SCU004, while "s->silicon_rev" was used for SCU014. The value of "s->silicon_rev" is set by the SoC layer via the "silicon-rev" property. This patch aligns both SCU004 and SCU014 to use "s->silicon_rev" for consistency and flexibility. Similarly, the "aspeed_ast1030_scu_reset" function also used a fixed revision constant ("AST1030_A1_SILICON_REV"). This change updates it to use the same "s->silicon_rev" property, ensuring that both SoCs follow a consistent and configurable revision handling mechanism. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-4-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index d27e0c7f9158..5bc0b3536f28 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -841,7 +841,7 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev) * of actual revision. QEMU and Linux only support A1 onwards so this = is * sufficient. */ - s->regs[AST2600_SILICON_REV] =3D AST2600_A3_SILICON_REV; + s->regs[AST2600_SILICON_REV] =3D s->silicon_rev; s->regs[AST2600_SILICON_REV2] =3D s->silicon_rev; s->regs[AST2600_HW_STRAP1] =3D s->hw_strap1; s->regs[AST2600_HW_STRAP2] =3D s->hw_strap2; @@ -1137,7 +1137,7 @@ static void aspeed_ast1030_scu_reset(DeviceState *dev) =20 memcpy(s->regs, asc->resets, asc->nr_regs * 4); =20 - s->regs[AST2600_SILICON_REV] =3D AST1030_A1_SILICON_REV; + s->regs[AST2600_SILICON_REV] =3D s->silicon_rev; s->regs[AST2600_SILICON_REV2] =3D s->silicon_rev; s->regs[AST2600_HW_STRAP1] =3D s->hw_strap1; s->regs[AST2600_HW_STRAP2] =3D s->hw_strap2; --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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bh=yJv6P0qh9N/6zxyMRpI9aJZHDQPwnl5DoZNIDIl/Wqw=; b=GT751VG7m5T2SrzAp62NOmDufvMuU5Wird0qw1JHSX90ZMfBLlQ03lGhCRQeMpsLNVoR9r TMEEgoHOZhKS9efxymF+SdotR31I+e2TSM7Vz2kJEDceT5RZ8mtT2Ia2A2bsJKy7Q34kBm YfkmrBbGq0MPiv49pXHhVYMvdbuGABs= X-MC-Unique: JEWB8uXyOgmswZoA3vYyFg-1 X-Mimecast-MFC-AGG-ID: JEWB8uXyOgmswZoA3vYyFg_1767617783 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/36] hhw/misc/aspeed_scu: Add AST1060 A2 silicon revision definition Date: Mon, 5 Jan 2026 13:55:40 +0100 Message-ID: <20260105125613.622667-4-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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This allows the SCU model and related SoC layers to identify and handle AST1060 A2 revision properly in the same way as other Aspeed SoC families. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-5-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/misc/aspeed_scu.h | 1 + hw/misc/aspeed_scu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 35b841960af0..9e28bd4d2e1a 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -51,6 +51,7 @@ struct AspeedSCUState { #define AST2600_A3_SILICON_REV 0x05030303U #define AST1030_A0_SILICON_REV 0x80000000U #define AST1030_A1_SILICON_REV 0x80010000U +#define AST1060_A2_SILICON_REV 0xA0030000U #define AST2700_A0_SILICON_REV 0x06000103U #define AST2720_A0_SILICON_REV 0x06000203U #define AST2750_A0_SILICON_REV 0x06000003U diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 5bc0b3536f28..6829efa2dcd4 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -565,6 +565,7 @@ static uint32_t aspeed_silicon_revs[] =3D { AST2600_A3_SILICON_REV, AST1030_A0_SILICON_REV, AST1030_A1_SILICON_REV, + AST1060_A2_SILICON_REV, AST2700_A0_SILICON_REV, AST2720_A0_SILICON_REV, AST2750_A0_SILICON_REV, --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617788; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=horSo4GLaZE0t3/vJOGkQfg7YC1r8kXsbkI/7d+A1SU=; b=eOSf4rlLzON4EkmSvT+DZVlzXtJPWipazVASAiSYK+Fjz+iCZ46fYJCeXaPYwGry/Fxwpk GOAMine/hLnmqIsCEAGmlcC9lNjv3ALaaDzxTUlCMbiCwTiYH2OJTgyZ6W6l6OmEra56aI KhTCitkdlTmgAZJczmBsoU8nh/iz3RY= X-MC-Unique: duO7CqV4OgCTFhxnL5GUIw-1 X-Mimecast-MFC-AGG-ID: duO7CqV4OgCTFhxnL5GUIw_1767617785 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 04/36] hw/arm/aspeed_ast10x0: Add common init function for AST10x0 SoCs Date: Mon, 5 Jan 2026 13:55:41 +0100 Message-ID: <20260105125613.622667-5-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620190415154100 From: Jamin Lin Introduce a new common initialization function aspeed_soc_ast10x0_init() for AST10x0 series SoCs. This separates the shared initialization logic from the AST1030-specific part, allowing reuse by future SoCs such as AST1060. The AST1060 does not include the LPC and PECI models, so the common initializer is used for all shared modules, while aspeed_soc_ast1030_init() adds initialization of LPC and PECI, which are unique to AST1030. This refactor improves code reuse and prepares the codebase for supporting the AST1060 platform. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-6-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index f923b9505b78..1dd1a95ea5bd 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -107,7 +107,7 @@ static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCSta= te *s, int dev) return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); } =20 -static void aspeed_soc_ast1030_init(Object *obj) +static void aspeed_soc_ast10x0_init(Object *obj) { Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(obj); AspeedSoCState *s =3D ASPEED_SOC(obj); @@ -150,10 +150,6 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "spi[*]", &s->spi[i], typename); } =20 - object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); - - object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); - object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST10X0_SBC); =20 for (i =3D 0; i < sc->wdts_num; i++) { @@ -185,6 +181,15 @@ static void aspeed_soc_ast1030_init(Object *obj) TYPE_UNIMPLEMENTED_DEVICE); } =20 +static void aspeed_soc_ast1030_init(Object *obj) +{ + AspeedSoCState *s =3D ASPEED_SOC(obj); + + aspeed_soc_ast10x0_init(obj); + object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); + object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); +} + static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) { Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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bh=JCqeB5q4nk1qZZKh3AiuHmU774j78tSilI9/XgQofrQ=; b=AfzKWjEHwCxH9hgVB2VYsotZhx3I3TgB1NZMxC1aHKaIlSPn0xme1aGz/dTklYKRvns6S+ 8LX3rxTH8Bw3iWu3ZGapJCMhDUK23r+y87dGIQbMcn7uKxPvvqiw46pCi97+7qqlVSvzSm 5GSqIp9FrzwITluM5fTgef8yBO5MMTw= X-MC-Unique: voe8wOatMe6uHFnH72c_Uw-1 X-Mimecast-MFC-AGG-ID: voe8wOatMe6uHFnH72c_Uw_1767617787 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 05/36] hw/arm/aspeed_ast10x0: Add common realize function for AST10x0 SoCs Date: Mon, 5 Jan 2026 13:55:42 +0100 Message-ID: <20260105125613.622667-6-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617987133154100 From: Jamin Lin Introduce a new common realize function aspeed_soc_ast10x0_realize() for AST10x0 series SoCs. The shared initialization and realization logic is now placed in this common function to improve code reuse and reduce duplication between different SoCs in the same family. The AST1030 realization function aspeed_soc_ast1030_realize() is updated to call the new common routine and then perform realization of its own specific devices such as LPC and PECI, which are not present on future SoCs like AST1060. This refactor simplifies maintenance and prepares the framework for adding AST1060 support. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-7-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 128 ++++++++++++++++++++++------------------ 1 file changed, 70 insertions(+), 58 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 1dd1a95ea5bd..72a8c78ff890 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -190,10 +190,9 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); } =20 -static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) +static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp) { - Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); - AspeedSoCState *s =3D ASPEED_SOC(dev_soc); + AspeedSoCState *s =3D ASPEED_SOC(a); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; Error *err =3D NULL; @@ -203,7 +202,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 if (!clock_has_source(s->sysclk)) { error_setg(errp, "sysclk clock must be wired up by the board code"= ); - return; + return false; } =20 /* General I/O memory space to catch all unimplemented device */ @@ -216,7 +215,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC], 0x40000); =20 - /* AST1030 CPU Core */ + /* AST10x0 CPU Core */ armv7m =3D DEVICE(&a->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 256); qdev_prop_set_string(armv7m, "cpu-type", @@ -232,7 +231,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, = &err); if (err !=3D NULL) { error_propagate(errp, err); - return; + return false; } memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], @@ -241,14 +240,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) sc->secsram_size, &err); if (err !=3D NULL) { error_propagate(errp, err); - return; + return false; } memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM], &s->secsram); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); @@ -258,7 +257,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); @@ -271,7 +270,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* I3C */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); @@ -282,50 +281,11 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); } =20 - /* PECI */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, - sc->memmap[ASPEED_DEV_PECI]); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, - aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI)); - - /* LPC */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, - sc->memmap[ASPEED_DEV_LPC]); - - /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, - aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC)); - - /* - * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. - */ - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_1)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_2)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_3)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); - /* UART */ for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], sc->memmap[uart], errp)) { - return; + return false; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, aspeed_soc_ast1030_get_irq(s, uart)); @@ -335,7 +295,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); @@ -346,7 +306,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* ADC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); @@ -357,7 +317,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); @@ -371,7 +331,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->spi[i]), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0, sc->memmap[ASPEED_DEV_SPI1 + i]); @@ -383,7 +343,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* Secure Boot Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); @@ -392,7 +352,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); @@ -407,14 +367,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offs= et); } =20 /* GPIO */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); @@ -442,6 +402,58 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag", sc->memmap[ASPEED_DEV_JTAG1], 0x20); + + return true; +} + +static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) +{ + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); + AspeedSoCState *s =3D ASPEED_SOC(dev_soc); + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + + if (!aspeed_soc_ast10x0_realize(a, errp)) { + return; + } + + /* PECI */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, + sc->memmap[ASPEED_DEV_PECI]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI)); + + /* LPC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, + sc->memmap[ASPEED_DEV_LPC]); + + /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC)); + + /* + * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. + */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_1)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_2)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_3)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); } =20 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *= data) --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617791; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+AkrKRUkmsRbYLGALlWA0THvFa118QffTUtW7hxF+3Y=; b=A9xUtTo1r3ECrgX2fcDZOMez6i3Ph+q/b9rERuI99RBsYee/VPt4F/cGyEym5V+3p3eZZC dJnV2M5p2kmQqqfmgo10Jkca3MfOnvBEIEhDrWEJYlR9+zIrOHINol9U51DzHhi8IN2VeO u4MpgGOIJnsLdL1O6lphoa1qOxj0agY= X-MC-Unique: RfBOBcT5OEe1QpvnPMreWg-1 X-Mimecast-MFC-AGG-ID: RfBOBcT5OEe1QpvnPMreWg_1767617789 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 06/36] hw/arm/aspeed_ast10x0: Pass SoC name to common init for AST10x0 family reuse Date: Mon, 5 Jan 2026 13:55:43 +0100 Message-ID: <20260105125613.622667-7-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767646435819158500 From: Jamin Lin Refactor the AST10x0 common initialization to accept a socname parameter. The AST1030 model can be reused by AST1060 since they share most of the same controllers. This approach allows AST1060 to leverage the existing AST1030 initialization flow while keeping separate SoC-specific init functions for components that differ. This prepares the framework for AST1060 support, allowing it to reuse AST1030 device models and initialization flow without code duplication. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-8-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 72a8c78ff890..4ed6649e5546 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -107,19 +107,14 @@ static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCS= tate *s, int dev) return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); } =20 -static void aspeed_soc_ast10x0_init(Object *obj) +static void aspeed_soc_ast10x0_init(Object *obj, const char *socname) { Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(obj); AspeedSoCState *s =3D ASPEED_SOC(obj); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - char socname[8]; char typename[64]; int i; =20 - if (sscanf(object_get_typename(obj), "%7s", socname) !=3D 1) { - g_assert_not_reached(); - } - object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); =20 s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); @@ -185,7 +180,7 @@ static void aspeed_soc_ast1030_init(Object *obj) { AspeedSoCState *s =3D ASPEED_SOC(obj); =20 - aspeed_soc_ast10x0_init(obj); + aspeed_soc_ast10x0_init(obj, "ast1030"); object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); } --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767617956; cv=none; d=zohomail.com; s=zohoarc; b=Dz/Tg1A50oJI458eaW5+1uMSrQpg5eBalSNp6dXBbUkAvD4cJnjS0/UGUlLrU6SIDZS5mI43SIBAhF65XkCTUoHaBvqy/qyLg9svAfYnw3wDKsQqojDyo3mDbKoGocUJCNzg+bqXOnDjs9c21uHPb3HYvi7mgCXgZh2ijENjonw= ARC-Message-Signature: i=1; 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Mon, 5 Jan 2026 12:56:31 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 103AB19560A7; Mon, 5 Jan 2026 12:56:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617794; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VubRcQ92hC2orf+/hvxD67znU0vMNup3DnROyTxFHaw=; b=Bo0RGI3bcOkZED5xZ/CzUggbDshS4P/sqx6QdG9IaF7jegzDNBimd2wxga3x6plZpRhPop BUylsj08yWAeiv6OmJuXJ0wpBp0lBQrhgai20TujniXq4kHKIDasMV3JDzMN5U0qR08yEd N+LJZ0Wj8U/N2WVI5v+yJR474Inl5kc= X-MC-Unique: vnGpVYs9Mc6jKB3AwawyLQ-1 X-Mimecast-MFC-AGG-ID: vnGpVYs9Mc6jKB3AwawyLQ_1767617791 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 07/36] hw/arm/aspeed_ast10x0: Add AST1060 SoC support Date: Mon, 5 Jan 2026 13:55:44 +0100 Message-ID: <20260105125613.622667-8-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617958770154100 From: Jamin Lin Add initial support for the Aspeed AST1060 SoC. The AST1060 reuses most of the AST1030 peripheral device models, as the two SoCs share nearly the same controllers including WDT, SCU, TIMER, HACE, ADC, I2C, FMC, and SPI. A new common initialization and realization framework (ast10x0_init and ast10x0_realize) is leveraged so AST1060 can instantiate the existing AST1030 models without redefining duplicate device types. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-9-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 59 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 4ed6649e5546..44e1d59ddb3c 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -185,6 +185,23 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); } =20 +static void aspeed_soc_ast1060_init(Object *obj) +{ + /* + * The AST1060 SoC reuses the AST1030 device models. Since all periphe= ral + * models (e.g. WDT, SCU, TIMER, HACE, ADC, I2C, FMC, SPI) defined for + * AST1030 are compatible with AST1060, we simply reuse the existing + * AST1030 models for AST1060. + * + * To simplify the implementation, AST1060 sets its socname to that of + * AST1030, avoiding the need to create a full set of new + * TYPE_ASPEED_1060_XXX device definitions. This allows the same + * TYPE_ASPEED_1030_WDT and other models to be instantiated for both + * SoCs. + */ + aspeed_soc_ast10x0_init(obj, "ast1030"); +} + static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp) { AspeedSoCState *s =3D ASPEED_SOC(a); @@ -451,6 +468,15 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); } =20 +static void aspeed_soc_ast1060_realize(DeviceState *dev_soc, Error **errp) +{ + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); + + if (!aspeed_soc_ast10x0_realize(a, errp)) { + return; + } +} + static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *= data) { static const char * const valid_cpu_types[] =3D { @@ -479,6 +505,32 @@ static void aspeed_soc_ast1030_class_init(ObjectClass = *klass, const void *data) sc->num_cpus =3D 1; } =20 +static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *= data) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); + + /* Reason: The Aspeed SoC can only be instantiated from a board */ + dc->user_creatable =3D false; + dc->realize =3D aspeed_soc_ast1060_realize; + + sc->valid_cpu_types =3D valid_cpu_types; + sc->silicon_rev =3D AST1060_A2_SILICON_REV; + sc->sram_size =3D 0xc0000; + sc->secsram_size =3D 0x40000; /* 256 * KiB */ + sc->spis_num =3D 2; + sc->wdts_num =3D 4; + sc->uarts_num =3D 1; + sc->uarts_base =3D ASPEED_DEV_UART5; + sc->irqmap =3D aspeed_soc_ast1030_irqmap; + sc->memmap =3D aspeed_soc_ast1030_memmap; + sc->num_cpus =3D 1; +} + static const TypeInfo aspeed_soc_ast10x0_types[] =3D { { .name =3D TYPE_ASPEED10X0_SOC, @@ -490,7 +542,12 @@ static const TypeInfo aspeed_soc_ast10x0_types[] =3D { .parent =3D TYPE_ASPEED10X0_SOC, .instance_init =3D aspeed_soc_ast1030_init, .class_init =3D aspeed_soc_ast1030_class_init, - }, + }, { + .name =3D "ast1060-a2", + .parent =3D TYPE_ASPEED10X0_SOC, + .instance_init =3D aspeed_soc_ast1060_init, + .class_init =3D aspeed_soc_ast1060_class_init, + } }; =20 DEFINE_TYPES(aspeed_soc_ast10x0_types) --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767631144; cv=none; d=zohomail.com; s=zohoarc; b=LKkRUUfGV4HrU9Gdb0F29Ac8sSiFrG9kxckV/PvCdu/yUZY6gqSdR48PZAnM6Uaqzg85ilPP89kcHXbPEAhNxR4w1Qt6wsvAoHb9RUyWHHQ3nakn2/kP3kDlVGBda4JIwms3YpbpCxaEIfnk9jmdeSqU3g9na518L5/fHETkz8A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1767631144; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AQdfds82YWsuOCtG/9BPJjNBteIfOpdB0/SQ8I8VXh0=; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617797; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AQdfds82YWsuOCtG/9BPJjNBteIfOpdB0/SQ8I8VXh0=; b=cmMHlKe6Dd0Mm+YF1XSQuhgmPw+1iEEdusGHHApT0AIHtHSZiEQjS1LRzMR3VELgtjVi9J CA6o4e1SnhXGRbF9lJHMV0FVMC1fMFD3XtkExapqvXgl92EUNvLYDi32Cn0y8uWOUziQs2 v8SMzlDlzUgmJ6MCRpUXz8eVKffj9KY= X-MC-Unique: rLfj2uUYMd2howopUlBjyw-1 X-Mimecast-MFC-AGG-ID: rLfj2uUYMd2howopUlBjyw_1767617793 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/36] hw/arm/aspeed_ast10x0_evb: Add AST1060 EVB machine support Date: Mon, 5 Jan 2026 13:55:45 +0100 Message-ID: <20260105125613.622667-9-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767631145175158501 From: Jamin Lin Add a new machine definition ast1060-evb to support the Aspeed AST1060 evaluation board. The new EVB reuses the same MiniBMC framework used by AST1030, as both SoCs share the same core peripherals and controller designs. The AST1060 EVB machine initializes the ast1060-a2 SoC and sets the FMC and SPI flash models (w25q80bl and w25q02jvm) for simulation. This enables QEMU to boot and emulate firmware images for AST1060-based platforms. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-10-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0_evb.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/arm/aspeed_ast10x0_evb.c b/hw/arm/aspeed_ast10x0_evb.c index 329578a542c3..c19563d1f0a6 100644 --- a/hw/arm/aspeed_ast10x0_evb.c +++ b/hw/arm/aspeed_ast10x0_evb.c @@ -96,12 +96,35 @@ static void aspeed_minibmc_machine_ast1030_evb_class_in= it(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } =20 +static void aspeed_minibmc_machine_ast1060_evb_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Aspeed AST1060 Platform Root of Trust (Cortex-M4)"; + amc->soc_name =3D "ast1060-a2"; + amc->hw_strap1 =3D 0; + amc->hw_strap2 =3D 0; + mc->init =3D aspeed_minibmc_machine_init; + amc->fmc_model =3D "w25q80bl"; + amc->spi_model =3D "w25q02jvm"; + amc->num_cs =3D 2; + amc->macs_mask =3D 0; + aspeed_machine_class_init_cpus_defaults(mc); +} + static const TypeInfo aspeed_ast10x0_evb_types[] =3D { { .name =3D MACHINE_TYPE_NAME("ast1030-evb"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_minibmc_machine_ast1030_evb_class_init, .interfaces =3D arm_machine_interfaces, + }, { + .name =3D MACHINE_TYPE_NAME("ast1060-evb"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_minibmc_machine_ast1060_evb_class_init, + .interfaces =3D arm_machine_interfaces, } }; =20 --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767630769; cv=none; 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Mon, 5 Jan 2026 12:56:35 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 1ECD519560A7; Mon, 5 Jan 2026 12:56:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617798; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xGnMfdF6G4uUQw2uzyCr9taP/1Mlago7zualsFQFCLg=; b=XyZ1XWg7ccAbFM3O4yJHfIt5SRU8qTxHbDNDCN3Tf1PrDt7E+gZoc2anWutAi5LzSnO07P s/ucb+J2ZuZz4WotFpKAQGqOMOR2WUftK7tWWI9jiyfqjOV3qFrMeEC7fy038SlCtR3Dm4 PJhxbTctyn7qXY+AJ7JU4af1DnaGMmw= X-MC-Unique: lzSEMYAsNTOi54Sy2NvY-g-1 X-Mimecast-MFC-AGG-ID: lzSEMYAsNTOi54Sy2NvY-g_1767617795 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 09/36] tests/functional/arm/test_aspeed_ast1060: Add functional tests for Aspeed AST1060 SoC Date: Mon, 5 Jan 2026 13:55:46 +0100 Message-ID: <20260105125613.622667-10-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767630772610158500 From: Jamin Lin Add functional tests for the Aspeed AST1060 SoC and its evaluation board. The new test test_aspeed_ast1060.py validates booting the AST1060 EVB machine using the Zephyr OS and ASPEED PROT application (ast1060_prot_v03.0= 2.tgz) and ensures basic console functionality. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-11-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- tests/functional/arm/meson.build | 1 + tests/functional/arm/test_aspeed_ast1060.py | 52 +++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 tests/functional/arm/test_aspeed_ast1060.py diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.= build index d1ed076a6aa8..1762a496049d 100644 --- a/tests/functional/arm/meson.build +++ b/tests/functional/arm/meson.build @@ -28,6 +28,7 @@ tests_arm_system_quick =3D [ =20 tests_arm_system_thorough =3D [ 'aspeed_ast1030', + 'aspeed_ast1060', 'aspeed_palmetto', 'aspeed_romulus', 'aspeed_witherspoon', diff --git a/tests/functional/arm/test_aspeed_ast1060.py b/tests/functional= /arm/test_aspeed_ast1060.py new file mode 100644 index 000000000000..034efa534262 --- /dev/null +++ b/tests/functional/arm/test_aspeed_ast1060.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED SoCs with firmware +# +# Copyright (C) 2025 ASPEED Technology Inc +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from aspeed import AspeedTest +from qemu_test import Asset, exec_command_and_wait_for_pattern + + +class AST1060Machine(AspeedTest): + ASSET_ASPEED_AST1060_PROT_3_02 =3D Asset( + ('https://github.com/AspeedTech-BMC' + '/aspeed-zephyr-project/releases/download/v03.02' + '/ast1060_prot_v03.02.tgz'), + 'dd5f1adc935316ddd1906506a02e15567bd7290657b52320f1a225564cc175bd= ') + + def test_arm_ast1060_prot_3_02(self): + self.set_machine('ast1060-evb') + + kernel_name =3D "ast1060_prot/zephyr.bin" + kernel_file =3D self.archive_extract( + self.ASSET_ASPEED_AST1060_PROT_3_02, member=3Dkernel_name) + + self.vm.set_console() + self.vm.add_args('-kernel', kernel_file, '-nographic') + self.vm.launch() + self.wait_for_console_pattern("Booting Zephyr OS") + exec_command_and_wait_for_pattern(self, "help", + "Available commands") + + def test_arm_ast1060_otp_blockdev_device(self): + self.vm.set_machine("ast1060-evb") + + kernel_name =3D "ast1060_prot/zephyr.bin" + kernel_file =3D self.archive_extract(self.ASSET_ASPEED_AST1060_PRO= T_3_02, + member=3Dkernel_name) + otp_img =3D self.generate_otpmem_image() + + self.vm.set_console() + self.vm.add_args( + "-kernel", kernel_file, + "-blockdev", f"driver=3Dfile,filename=3D{otp_img},node-name=3D= otp", + "-global", "aspeed-otp.drive=3Dotp", + ) + self.vm.launch() + self.wait_for_console_pattern("Booting Zephyr OS") + +if __name__ =3D=3D '__main__': + AspeedTest.main() --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 05 Jan 2026 07:56:48 -0500 Received: from mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-656-z1tlVpV9N4a_ahvoii_yTA-1; Mon, 05 Jan 2026 07:56:38 -0500 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 98254195FCE9; Mon, 5 Jan 2026 12:56:37 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0EA76195398A; Mon, 5 Jan 2026 12:56:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617803; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NkgUOJhTx0F43VwFud6NhxLZPsuw7OTTJNSweLB1+lA=; b=epAZjqPJCWDnpugLkUvS9DLaMYFqcZb8VMUK6V/mUjmfBJPUWMNlxJ7pM+qioAqD9M4/t/ dSnvvpo7qO1KPYiX0E3zdhVA7jRmCgw0wqSpWBZVxLcpIq+L0GQRwp0VgFWDXPV0y/LEzv 1vDoiHAhW44Rm+3NWu2e6osZiOtpI5g= X-MC-Unique: z1tlVpV9N4a_ahvoii_yTA-1 X-Mimecast-MFC-AGG-ID: z1tlVpV9N4a_ahvoii_yTA_1767617797 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 10/36] docs/system/arm/aspeed: Update Aspeed and 2700 family boards list Date: Mon, 5 Jan 2026 13:55:47 +0100 Message-ID: <20260105125613.622667-11-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767633195280158500 From: Jamin Lin Remove the ast2700-evb entry from the Aspeed family boards list in the documentation. The AST2700 platform now belongs to the new Aspeed 2700 family group, which has its own dedicated documentation section and board definitions. Update the Aspeed 2700 family boards list in the documentation to include the new ast2700fc board entry. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-12-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 6317c0e910a2..81a96994559c 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -1,5 +1,5 @@ -Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, `= `bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2= -bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-fir= ework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonor= apass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-b= mc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``bletchley-bmc``,= ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-b= mc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``qu= anta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``su= permicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspo= on-bmc``, ``yosemitev2-bmc``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =20 The QEMU Aspeed machines model BMCs of various OpenPOWER systems and Aspeed evaluation boards. They are based on different releases of the @@ -274,8 +274,8 @@ configuration file for OTP memory: done > otpmem.img fi =20 -Aspeed 2700 family boards (``ast2700-evb``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Aspeed 2700 family boards (``ast2700-evb``, ``ast2700fc``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D =20 The QEMU Aspeed machines model BMCs of Aspeed evaluation boards. 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617801; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pgScfA+yBMg9P14PP4V/MiHScFQJmqGIiDTtMN/i71M=; b=gB/3qHBSj6zaqY9EBPeh8A0E2F599cO2sIG7FSf8EuUUF5bVuTUrcv9PZLjVqCHDs7AUtQ jLCGDXEMPII5Pg9S/BD+TLi7izq+qI5CeITcriGexuFh8DTWQLEo+1RAmGKSvFnkG4Fk3D 6FoYAPnbNskrOzNDdKSpqogUrGGy1eU= X-MC-Unique: 8cl8JiOOMnisCgN6ZjEUIg-1 X-Mimecast-MFC-AGG-ID: 8cl8JiOOMnisCgN6ZjEUIg_1767617799 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 11/36] docs/system/arm/aspeed: Update Aspeed MiniBMC section to include AST1060 processor Date: Mon, 5 Jan 2026 13:55:48 +0100 Message-ID: <20260105125613.622667-12-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767631136939158500 From: Jamin Lin Added details describing AST1060 as a Platform Root of Trust processor boar= d alongside AST1030 MiniBMC, and extended the list of missing devices to include SMBus Filter and QSPI Monitor controllers. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251112030553.291734-13-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 81a96994559c..4fa1739cb549 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -448,23 +448,24 @@ Use ``tio`` or another terminal emulator to connect t= o the consoles: $ tio /dev/pts/57 =20 =20 -Aspeed minibmc family boards (``ast1030-evb``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Aspeed MiniBMC and Platform Root of Trust processor family boards (``ast10= 30-evb``, ``ast1060-evb``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =20 -The QEMU Aspeed machines model mini BMCs of various Aspeed evaluation -boards. They are based on different releases of the -Aspeed SoC : the AST1030 integrating an ARM Cortex M4F CPU (200MHz). +The QEMU Aspeed machines model mini BMCs and Platform Root of Trust proces= sors of various Aspeed +evaluation boards. They are based on different releases of the Aspeed SoC = : the AST1030 (MiniBMC) +and AST1060 (Platform Root of Trust Processor), both integrating an ARM Co= rtex M4F CPU (200MHz). =20 The SoC comes with SRAM, SPI, I2C, etc. =20 -AST1030 SoC based machines : +AST10x0 SoC based machines : =20 - ``ast1030-evb`` Aspeed AST1030 Evaluation board (Cortex-M4F) +- ``ast1060-evb`` Aspeed AST1060 Evaluation board (Cortex-M4F) =20 Supported devices ----------------- =20 - * SMP (for the AST1030 Cortex-M4F) + * SMP (for the Cortex-M4F) * Interrupt Controller (VIC) * Timer Controller * I2C Controller @@ -492,6 +493,8 @@ Missing devices * Virtual UART * eSPI Controller * I3C Controller + * SMBus Filter Controller + * QSPI Monitor Controller =20 Boot options ------------ @@ -507,4 +510,4 @@ To boot a kernel directly from a Zephyr build tree: .. code-block:: bash =20 $ qemu-system-arm -M ast1030-evb -nographic \ - -kernel zephyr.elf + -kernel zephyr.bin --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617804; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PjGbyXTJjQiByl1WIYDhgkx8UpptFRJQ+nqYwow5KAA=; b=iwG4T+/mBJXWq8VFrbto35HV6OlcgTNkHXtHAfd64v9hrTycPiU3WCMSi7g6kgYQBsuTxd G7fjQgkHOPipfSiK+Zm2HvOVPoKcKHr7chJmmsDRsb98y1MyHXS+sC4ucY2w7Plxwg/+Nr aFr3wpldgY8Xrf9LQU22Q024F0Ak/78= X-MC-Unique: nnNkOU1JOlesuoy3Px_bng-1 X-Mimecast-MFC-AGG-ID: nnNkOU1JOlesuoy3Px_bng_1767617801 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 12/36] hw/arm/aspeed: catalina: add BSM FRU EEPROM Date: Mon, 5 Jan 2026 13:55:49 +0100 Message-ID: <20260105125613.622667-13-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767619221302154100 From: Patrick Williams Use ipmitool/frugen tool to generate a BSM image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-1-dc7= b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 40 +++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 91977a4d3cc4..0f229f4dc695 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -26,6 +26,44 @@ #define TYPE_TMP421 "tmp421" #define TYPE_DS1338 "ds1338" =20 +/* + * "BMC Storage Module" FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "Quanta", + * "pname": "BMC Storage Module (QEMU)", + * "pn": "00000000000", + * "serial": "00000000000000", + * "date": "01/12/2025 00:00", + * "custom": ["09-100183"] + * }, + * "product": { + * "mfg": "Quanta", + * "pname": "CI-Catalina", + * "pn": "10000000001", + * "ver": "MP", + * "serial": "10000000000000", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t bsm_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0xf4, 0x01, 0x09, 0x19, 0x8c, + 0x19, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xd9, 0x42, 0x4d, + 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f, + 0x64, 0x75, 0x6c, 0x65, 0x20, 0x28, 0x51, 0x45, 0x4d, 0x55, 0x29, 0x8b, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x89, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x01, 0xc0, 0x87, 0x50, + 0xd6, 0x44, 0x10, 0x14, 0x61, 0x13, 0xc1, 0x59, 0x01, 0x07, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x43, 0x49, 0x2d, 0x43, 0x61, + 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x89, 0x11, 0x04, 0x41, 0x10, 0x04, + 0x41, 0x10, 0x14, 0x01, 0x82, 0x2d, 0x0c, 0x8b, 0x11, 0x04, 0x41, 0x10, + 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x83, 0x71, 0xd9, 0xd6, 0xc0, + 0xc1, 0x00, 0x00, 0x37 +}; +static const size_t bsm_eeprom_len =3D sizeof(bsm_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -147,7 +185,7 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) /* eeprom@50 */ at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); /* eeprom@56 */ - at24c_eeprom_init(i2c[9], 0x56, 8 * KiB); + at24c_eeprom_init_rom(i2c[9], 0x56, 8 * KiB, bsm_eeprom, bsm_eeprom_le= n); =20 /* &i2c10 */ /* temperature-sensor@1f - tpm421 */ --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767630978; cv=none; d=zohomail.com; s=zohoarc; b=SxTOicNz0iqhIQpAtrhr5/H9gO6c9rvlVrkA5OmCEAudensNP+1mmtUuLXsk7VqqxBo8O6SwffPl/Vn3hT1ScnacWelwByTPHIO78yGqTH3hDy/eNNzFfGG3FDtT3o3Llo09wkvK3+POsIoUnoB0WFlwtn8I5PlQh6KDQ+TI88I= ARC-Message-Signature: i=1; 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Mon, 5 Jan 2026 12:56:43 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0ADEA19560A7; Mon, 5 Jan 2026 12:56:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617807; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=o+iOQ0Z/TKdAXFko9sfzKmC7GBm/i0hT4cyAVeqXfC4=; b=ZwMdpssGFaspmhoI9twwMgkIJkk+ZHYcN5zha71GbUtj8AponvuJRo3ilCyohpifUThJal lZOaGmfpdrPPNIthKot234kE7lRK6vwkNA1jmbcp/J/ZnLO3N4EOMtAuWPy+B0mvcM+ArB 6sQGtouESHbHAkQ1WusGWv1xheJMajw= X-MC-Unique: 1e3vl20FPxK2skrgRkLCDA-1 X-Mimecast-MFC-AGG-ID: 1e3vl20FPxK2skrgRkLCDA_1767617803 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 13/36] hw/arm/aspeed: catalina: add DC-SCM FRU EEPROM Date: Mon, 5 Jan 2026 13:55:50 +0100 Message-ID: <20260105125613.622667-14-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767630979821158501 From: Patrick Williams Use ipmitool/frugen tool to generate a DC-SCM image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-2-dc7= b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 41 +++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 0f229f4dc695..6e8f4d39d97e 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -64,6 +64,45 @@ static const uint8_t bsm_eeprom[] =3D { }; static const size_t bsm_eeprom_len =3D sizeof(bsm_eeprom); =20 +/* + * "Secure Control Module" FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "Quanta", + * "pname": "Catalina SCM MP (QEMU)", + * "pn": "00000000000", + * "serial": "00000000000000", + * "date": "01/12/2025 00:00", + * "custom": ["19-100325"] + * }, + * "product": { + * "mfg": "Quanta", + * "pname": "CI-Catalina", + * "pn": "10000000001", + * "ver": "MP", + * "serial": "10000000000000", + * "atag": "QEMU" + * } + * } + * + */ +static const uint8_t scm_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0xf4, 0x01, 0x09, 0x19, 0x8c, + 0x19, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xd6, 0x43, 0x61, + 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x20, 0x53, 0x43, 0x4d, 0x20, 0x4d, + 0x50, 0x20, 0x28, 0x51, 0x45, 0x4d, 0x55, 0x29, 0x8b, 0x10, 0x04, 0x41, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x89, 0x10, 0x04, 0x41, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x01, 0xc0, 0x87, 0x51, 0xd6, 0x44, 0x10, + 0x34, 0x49, 0x15, 0xc1, 0x00, 0x00, 0x00, 0xc1, 0x01, 0x07, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x43, 0x49, 0x2d, 0x43, 0x61, + 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x89, 0x11, 0x04, 0x41, 0x10, 0x04, + 0x41, 0x10, 0x14, 0x01, 0x82, 0x2d, 0x0c, 0x8b, 0x11, 0x04, 0x41, 0x10, + 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x83, 0x71, 0xd9, 0xd6, 0xc0, + 0xc1, 0x00, 0x00, 0x37 +}; +static const size_t scm_eeprom_len =3D sizeof(scm_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -183,7 +222,7 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) /* temperature-sensor@4b - tpm75 */ i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b); /* eeprom@50 */ - at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); + at24c_eeprom_init_rom(i2c[9], 0x50, 8 * KiB, scm_eeprom, scm_eeprom_le= n); /* eeprom@56 */ at24c_eeprom_init_rom(i2c[9], 0x56, 8 * KiB, bsm_eeprom, bsm_eeprom_le= n); =20 --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767618071; cv=none; d=zohomail.com; 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Mon, 5 Jan 2026 12:56:45 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 066EF19560A7; Mon, 5 Jan 2026 12:56:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617807; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VkRyG+nuOL2if1Rh7rIC8AA3xkyAH90XSBBfJpYnefc=; b=KbJjfUUQofRnWkyqe1oR3u8Ch5qHZvGuB4rtk09ZekGpRyN6c6DqTOtnSMqRVPM9vALSxv 0ot5aVOempLouxW/OWeP9G7CownmLxJegivyDE3u4XRTnNM4Sc6p/knNdYAR27XOoNe1Vj Z/2cuL1YnnRh7byhYN+rZxzn9XxYj9I= X-MC-Unique: f5nJHjXmOLaC4YJzEY5owA-1 X-Mimecast-MFC-AGG-ID: f5nJHjXmOLaC4YJzEY5owA_1767617805 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 14/36] hw/arm/aspeed: catalina: add PDB FRU EEPROM Date: Mon, 5 Jan 2026 13:55:51 +0100 Message-ID: <20260105125613.622667-15-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767618076268154100 From: Patrick Williams Use ipmitool/frugen tool to generate a PDB image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-3-dc7= b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 51 +++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 6e8f4d39d97e..2ba2c5c08850 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -103,6 +103,54 @@ static const uint8_t scm_eeprom[] =3D { }; static const size_t scm_eeprom_len =3D sizeof(scm_eeprom); =20 +/* + * "Power Distribution Board" FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "Quanta", + * "pname": "Catalina PDB MP (QEMU)", + * "pn": "00000000000", + * "serial": "00000000000000", + * "date": "01/12/2025 00:00", + * "custom": [ + * "19-100579", + * "", + * "", + * "hsc-ltc fsc-max vr-delta gndsen-ina p12vsen-ina p12vfan= -mps" + * ] + * }, + * "product": { + * "mfg": "Quanta", + * "pname": "CI-Catalina", + * "pn": "10000000001", + * "ver": "MP", + * "serial": "10000000000000", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t pdb_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x12, 0x00, 0x00, 0xec, 0x01, 0x11, 0x19, 0x8c, + 0x19, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xd6, 0x43, 0x61, + 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x20, 0x50, 0x44, 0x42, 0x20, 0x4d, + 0x50, 0x20, 0x28, 0x51, 0x45, 0x4d, 0x55, 0x29, 0x8b, 0x10, 0x04, 0x41, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x89, 0x10, 0x04, 0x41, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x01, 0xc0, 0x87, 0x51, 0xd6, 0x44, 0x10, + 0x54, 0x5d, 0x19, 0xc0, 0xc0, 0xfb, 0x68, 0x73, 0x63, 0x2d, 0x6c, 0x74, + 0x63, 0x20, 0x66, 0x73, 0x63, 0x2d, 0x6d, 0x61, 0x78, 0x20, 0x76, 0x72, + 0x2d, 0x64, 0x65, 0x6c, 0x74, 0x61, 0x20, 0x67, 0x6e, 0x64, 0x73, 0x65, + 0x6e, 0x2d, 0x69, 0x6e, 0x61, 0x20, 0x70, 0x31, 0x32, 0x76, 0x73, 0x65, + 0x6e, 0x2d, 0x69, 0x6e, 0x61, 0x20, 0x70, 0x31, 0x32, 0x76, 0x66, 0x61, + 0x6e, 0x2d, 0x6d, 0x70, 0x73, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, + 0x01, 0x07, 0x19, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x43, + 0x49, 0x2d, 0x43, 0x61, 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x89, 0x11, + 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x14, 0x01, 0x82, 0x2d, 0x0c, 0x8b, + 0x11, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x83, + 0x71, 0xd9, 0xd6, 0xc0, 0xc1, 0x00, 0x00, 0x37 +}; +static const size_t pdb_eeprom_len =3D sizeof(pdb_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -166,7 +214,8 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) =20 /* i2c1mux0ch5 */ /* eeprom@54 */ - at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB); + at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB, + pdb_eeprom, pdb_eeprom_len); /* tpm75@4f */ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0= x4f); =20 --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767620574; cv=none; d=zohomail.com; s=zohoarc; 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Mon, 5 Jan 2026 12:56:47 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id EABC61953984; Mon, 5 Jan 2026 12:56:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NJ9VhKC40EhF8Zv4jokVa8XUrvbC7GaOIx25OW5QTGc=; b=diBn6Hv3O1R9xLxd3X04Kge211Z6D0s087X6oHyklpz/ISCBC4cT58lmmzhH8neZWXaB7F aPn7PA4jl15x2WfuNfzua7VUVfEX8XYAm7HO1LYQ2r7CxmqOe6rSl/seivEvQ1vxFhujMT hAEalfflKdr6b1NCG26LV8ifHz9ypcQ= X-MC-Unique: ROPYvoQZMiGDFA5pu_GPiw-1 X-Mimecast-MFC-AGG-ID: ROPYvoQZMiGDFA5pu_GPiw_1767617807 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 15/36] hw/arm/aspeed: catalina: add OSFP FRU EEPROM Date: Mon, 5 Jan 2026 13:55:52 +0100 Message-ID: <20260105125613.622667-16-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620575315154100 From: Patrick Williams Use ipmitool/frugen tool to generate an OSFP image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-4-dc7= b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 41 +++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 2ba2c5c08850..c8e62afdfea6 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -151,6 +151,44 @@ static const uint8_t pdb_eeprom[] =3D { }; static const size_t pdb_eeprom_len =3D sizeof(pdb_eeprom); =20 +/* + * OSFP Carrier Board FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "Quanta", + * "pname": "Catalina OSFP MP (QEMU)", + * "pn": "00000000000", + * "serial": "00000000000000", + * "date": "01/12/2025 00:00", + * "custom": ["19-100316"] + * }, + * "product": { + * "mfg": "Quanta", + * "pname": "CI-Catalina", + * "pn": "10000000001", + * "ver": "MP", + * "serial": "10000000000000", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t osfp_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0xf4, 0x01, 0x09, 0x19, 0x8c, + 0x19, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xd7, 0x43, 0x61, + 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x20, 0x4f, 0x53, 0x46, 0x50, 0x20, + 0x4d, 0x50, 0x20, 0x28, 0x51, 0x45, 0x4d, 0x55, 0x29, 0x8b, 0x10, 0x04, + 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x89, 0x10, 0x04, + 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x01, 0xc0, 0x87, 0x51, 0xd6, 0x44, + 0x10, 0x34, 0x45, 0x16, 0xc1, 0x00, 0x00, 0x6e, 0x01, 0x07, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x43, 0x49, 0x2d, 0x43, 0x61, + 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x89, 0x11, 0x04, 0x41, 0x10, 0x04, + 0x41, 0x10, 0x14, 0x01, 0x82, 0x2d, 0x0c, 0x8b, 0x11, 0x04, 0x41, 0x10, + 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x83, 0x71, 0xd9, 0xd6, 0xc0, + 0xc1, 0x00, 0x00, 0x37 +}; +static const size_t osfp_eeprom_len =3D sizeof(osfp_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -227,7 +265,8 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), TYPE_PCA9552, 0x25); /* eeprom@51 */ - at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB); + at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB, + osfp_eeprom, osfp_eeprom_len); =20 /* i2c1mux0ch7 */ /* eeprom@53 */ --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767633196; cv=none; d=zohomail.com; s=zohoarc; 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Mon, 5 Jan 2026 12:56:49 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id E794319560A7; Mon, 5 Jan 2026 12:56:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617812; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HzyOf6WCoRnETebhcLxvKS3EV81G2XXrHR0VELV8rBY=; b=ifkL75zYs4V/KHC7OQWCcMlaxjbI9UyGF0kLCOx4vT5IeaerH0Rv+DtaB1D18M4Z5kw6mb ovs81gTFqeJN5/ZOGfyArNao3d4ArxUOK98QLm3GwkSHjyJpmpNkBme7aLfJK9pvipLkBA TAHWUyoQ4llV1Fu3rQXEGH8x32z8lkQ= X-MC-Unique: PcOydyP2O-mGyyd21CDn-A-1 X-Mimecast-MFC-AGG-ID: PcOydyP2O-mGyyd21CDn-A_1767617809 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 16/36] hw/arm/aspeed: catalina: add FIO FRU EEPROM Date: Mon, 5 Jan 2026 13:55:53 +0100 Message-ID: <20260105125613.622667-17-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767633197009158500 From: Patrick Williams Use ipmitool/frugen tool to generate an FIO image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-5-dc7= b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 41 +++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index c8e62afdfea6..17db9035bda5 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -189,6 +189,44 @@ static const uint8_t osfp_eeprom[] =3D { }; static const size_t osfp_eeprom_len =3D sizeof(osfp_eeprom); =20 +/* + * "Front IO" FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "Quanta", + * "pname": "Catalina FIO MP (QEMU)", + * "pn": "00000000000", + * "serial": "00000000000000", + * "date": "01/12/2025 00:00", + * "custom": ["19-100290"] + * }, + * "product": { + * "mfg": "Quanta", + * "pname": "CI-Catalina", + * "pn": "10000000001", + * "ver": "MP", + * "serial": "10000000000000", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t fio_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0xf4, 0x01, 0x09, 0x19, 0x8c, + 0x19, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xd6, 0x43, 0x61, + 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x20, 0x46, 0x49, 0x4f, 0x20, 0x4d, + 0x50, 0x20, 0x28, 0x51, 0x45, 0x4d, 0x55, 0x29, 0x8b, 0x10, 0x04, 0x41, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x89, 0x10, 0x04, 0x41, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x01, 0xc0, 0x87, 0x51, 0xd6, 0x44, 0x10, + 0x24, 0x65, 0x10, 0xc1, 0x00, 0x00, 0x00, 0xbf, 0x01, 0x07, 0x19, 0xc6, + 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xcb, 0x43, 0x49, 0x2d, 0x43, 0x61, + 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x89, 0x11, 0x04, 0x41, 0x10, 0x04, + 0x41, 0x10, 0x14, 0x01, 0x82, 0x2d, 0x0c, 0x8b, 0x11, 0x04, 0x41, 0x10, + 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x83, 0x71, 0xd9, 0xd6, 0xc0, + 0xc1, 0x00, 0x00, 0x37 +}; +static const size_t fio_eeprom_len =3D sizeof(fio_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -270,7 +308,8 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) =20 /* i2c1mux0ch7 */ /* eeprom@53 */ - at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB); + at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB, + fio_eeprom, fio_eeprom_len); /* temperature-sensor@4b - tmp75 */ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0= x4b); =20 --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767631886; cv=none; d=zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767631888145158500 From: Patrick Williams Use ipmitool/frugen tool to generate a HDD image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-6-dc7= b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 41 +++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 17db9035bda5..4cfde870affa 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -227,6 +227,44 @@ static const uint8_t fio_eeprom[] =3D { }; static const size_t fio_eeprom_len =3D sizeof(fio_eeprom); =20 +/* + * HDD Carrier Board FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "Quanta", + * "pname": "Catalina HDD MP (QEMU)", + * "pn": "00000000000", + * "serial": "00000000000000", + * "date": "01/12/2025 00:00", + * "custom": ["19-100319", "", "", "adc-ina"] + * }, + * "product": { + * "mfg": "Quanta", + * "pname": "CI-Catalina", + * "pn": "10000000001", + * "ver": "MP", + * "serial": "10000000000000", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t hdd_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x8c, + 0x19, 0xf0, 0xc6, 0x51, 0x75, 0x61, 0x6e, 0x74, 0x61, 0xd6, 0x43, 0x61, + 0x74, 0x61, 0x6c, 0x69, 0x6e, 0x61, 0x20, 0x48, 0x44, 0x44, 0x20, 0x4d, + 0x50, 0x20, 0x28, 0x51, 0x45, 0x4d, 0x55, 0x29, 0x8b, 0x10, 0x04, 0x41, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x89, 0x10, 0x04, 0x41, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x01, 0xc0, 0x87, 0x51, 0xd6, 0x44, 0x10, + 0x34, 0x45, 0x19, 0xc0, 0xc0, 0xc7, 0x61, 0x64, 0x63, 0x2d, 0x69, 0x6e, + 0x61, 0xc1, 0x00, 0xff, 0x01, 0x07, 0x19, 0xc6, 0x51, 0x75, 0x61, 0x6e, + 0x74, 0x61, 0xcb, 0x43, 0x49, 0x2d, 0x43, 0x61, 0x74, 0x61, 0x6c, 0x69, + 0x6e, 0x61, 0x89, 0x11, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x14, 0x01, + 0x82, 0x2d, 0x0c, 0x8b, 0x11, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, + 0x41, 0x10, 0x04, 0x83, 0x71, 0xd9, 0xd6, 0xc0, 0xc1, 0x00, 0x00, 0x37 +}; +static const size_t hdd_eeprom_len =3D sizeof(hdd_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -330,7 +368,8 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) i2c_mux =3D i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70); /* i2c5mux0ch6 */ /* eeprom@52 */ - at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB); + at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB, + hdd_eeprom, hdd_eeprom_len); /* i2c5mux0ch7 */ /* ina230@40 - no model */ /* ina230@41 - no model */ --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767631982; 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Mon, 5 Jan 2026 12:56:53 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 040FB19560A7; Mon, 5 Jan 2026 12:56:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617817; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Oazh8Sp0RSLzec0eT5MRbgbZCj2evErxfNkvlx0wdn8=; b=dIB+phGLvLY46OEJ3xTvK5q1BeVlCKs60joo18HbtRX+FkGYc3gz0zYW7Cu+Q07dD+QTcn UdsHPB+4fQ4O0mdXfxVMoY20xMjAHHYSN8E8vCNqiDVHE+aNN4hWSnfgR8xsNTHdyL4/hU 3ja75NZ845SY8CMCDlngyKy//KziL9g= X-MC-Unique: axr7j136ONumHcy5Z4Tmkw-1 X-Mimecast-MFC-AGG-ID: axr7j136ONumHcy5Z4Tmkw_1767617813 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 18/36] hw/arm/aspeed: catalina: add GB200 FRU EEPROM Date: Mon, 5 Jan 2026 13:55:55 +0100 Message-ID: <20260105125613.622667-19-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767631984795158500 From: Patrick Williams Use ipmitool/frugen tool to generate a GB200 image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-7-dc7= b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 45 ++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 4cfde870affa..4dd72c615dc7 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -265,6 +265,45 @@ static const uint8_t hdd_eeprom[] =3D { }; static const size_t hdd_eeprom_len =3D sizeof(hdd_eeprom); =20 +/* + * GB200 CPU/GPU Board FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "NVIDIA", + * "pname": "PG548 (QEMU)", + * "pn": "000-00000-0000-000", + * "serial": "0000000000000", + * "date": "01/12/2025 00:00", + * "custom": ["Version: A", "Rework:"] + * }, + * "product": { + * "mfg": "NVIDIA", + * "pname": "GB200 1CPU:1GPU Board PC", + * "pn": "100-00000-0000-001", + * "ver": "E01", + * "serial": "1000000000001", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t gb200_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0xf4, 0x01, 0x09, 0x19, 0x8c, + 0x19, 0xf0, 0x85, 0xae, 0x9d, 0x92, 0x69, 0x08, 0x89, 0xf0, 0x59, 0x51, + 0x18, 0x80, 0xc4, 0x65, 0x5b, 0x27, 0x8a, 0x10, 0x04, 0x41, 0x10, 0x04, + 0x41, 0x10, 0x04, 0x41, 0x10, 0x8e, 0x10, 0x04, 0x35, 0x10, 0x04, 0x41, + 0x50, 0x03, 0x41, 0x10, 0xd4, 0x40, 0x10, 0x04, 0xc0, 0xca, 0x56, 0x65, + 0x72, 0x73, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x41, 0xc7, 0x52, 0x65, 0x77, + 0x6f, 0x72, 0x6b, 0x3a, 0xc1, 0x00, 0x00, 0x37, 0x01, 0x09, 0x19, 0x85, + 0xae, 0x9d, 0x92, 0x69, 0x08, 0xd8, 0x47, 0x42, 0x32, 0x30, 0x30, 0x20, + 0x31, 0x43, 0x50, 0x55, 0x3a, 0x31, 0x47, 0x50, 0x55, 0x20, 0x42, 0x6f, + 0x61, 0x72, 0x64, 0x20, 0x50, 0x43, 0x8e, 0x11, 0x04, 0x35, 0x10, 0x04, + 0x41, 0x50, 0x03, 0x41, 0x10, 0xd4, 0x40, 0x50, 0x04, 0x83, 0x25, 0x14, + 0x01, 0x8a, 0x11, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x11, + 0x83, 0x71, 0xd9, 0xd6, 0xc0, 0xc1, 0x00, 0x17 +}; +static const size_t gb200_eeprom_len =3D sizeof(gb200_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -403,11 +442,13 @@ static void catalina_bmc_i2c_init(AspeedMachineState = *bmc) =20 /* &i2c12 */ /* eeprom@50 */ - at24c_eeprom_init(i2c[12], 0x50, 8 * KiB); + at24c_eeprom_init_rom(i2c[12], 0x50, 8 * KiB, + gb200_eeprom, gb200_eeprom_len); =20 /* &i2c13 */ /* eeprom@50 */ - at24c_eeprom_init(i2c[13], 0x50, 8 * KiB); + at24c_eeprom_init_rom(i2c[13], 0x50, 8 * KiB, + gb200_eeprom, gb200_eeprom_len); /* eeprom@54 */ at24c_eeprom_init(i2c[13], 0x54, 256); /* eeprom@55 */ --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17676353388941023.8649313021521; Mon, 5 Jan 2026 09:48:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vck98-0004Jf-BH; Mon, 05 Jan 2026 07:57:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vck8r-000435-DC for qemu-devel@nongnu.org; Mon, 05 Jan 2026 07:57:01 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vck8o-00081H-IX for qemu-devel@nongnu.org; Mon, 05 Jan 2026 07:57:01 -0500 Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-459-0X9lNW4hP_Cc0-NzD8x9tQ-1; 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bh=POHV0+sltmYevysbodtEg4zKU7FV0FfzvTJN2VPCqVI=; b=HRMWYLe7aqgBD75PElivt+AWl/a8PIfCP3q//cFOd1z5Whc2Ill7qiBW04pODNflLaCVuq tDCXPI3sBG+X43q/xCY2X3KiIJYCE3MriT6kIACdPdNVPoGwe6fTp5pD5w0kLbMxTGSkrL 324lq9O9iFM/yZj5qDKECfQl+KAg+KE= X-MC-Unique: 0X9lNW4hP_Cc0-NzD8x9tQ-1 X-Mimecast-MFC-AGG-ID: 0X9lNW4hP_Cc0-NzD8x9tQ_1767617815 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 19/36] hw/arm/aspeed: catalina: add GB200-IO FRU EEPROM Date: Mon, 5 Jan 2026 13:55:56 +0100 Message-ID: <20260105125613.622667-20-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767635340219158500 From: Patrick Williams Use ipmitool/frugen tool to generate a GB200-IO image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-8-dc7= b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 43 ++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 4dd72c615dc7..37f0e1b65e48 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -304,6 +304,43 @@ static const uint8_t gb200_eeprom[] =3D { }; static const size_t gb200_eeprom_len =3D sizeof(gb200_eeprom); =20 +/* + * GB200 IO Board FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "Nvidia", + * "pname": "2x ConnectX-7 Mezz (QEMU)", + * "pn": "000-00000-0000-000", + * "serial": "000000000000", + * "date": "01/12/2025 00:00" + * }, + * "product": { + * "mfg": "Nvidia", + * "pname": "2x ConnectX-7 Mezz", + * "pn": "100-00000-0000-001", + * "ver": "A1", + * "serial": "100000000001", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t gb200io_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0xf4, 0x01, 0x09, 0x19, 0x8c, + 0x19, 0xf0, 0xc6, 0x4e, 0x76, 0x69, 0x64, 0x69, 0x61, 0xd9, 0x32, 0x78, + 0x20, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x37, 0x20, + 0x4d, 0x65, 0x7a, 0x7a, 0x20, 0x28, 0x51, 0x45, 0x4d, 0x55, 0x29, 0x89, + 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x8e, 0x10, 0x04, + 0x35, 0x10, 0x04, 0x41, 0x50, 0x03, 0x41, 0x10, 0xd4, 0x40, 0x10, 0x04, + 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x01, 0x08, 0x19, 0xc6, + 0x4e, 0x76, 0x69, 0x64, 0x69, 0x61, 0xd2, 0x32, 0x78, 0x20, 0x43, 0x6f, + 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x37, 0x20, 0x4d, 0x65, 0x7a, + 0x7a, 0x8e, 0x11, 0x04, 0x35, 0x10, 0x04, 0x41, 0x50, 0x03, 0x41, 0x10, + 0xd4, 0x40, 0x50, 0x04, 0x82, 0x61, 0x04, 0x89, 0x11, 0x04, 0x41, 0x10, + 0x04, 0x41, 0x10, 0x04, 0x45, 0x83, 0x71, 0xd9, 0xd6, 0xc0, 0xc1, 0x04 +}; +static const size_t gb200io_eeprom_len =3D sizeof(gb200io_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -329,7 +366,8 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), TYPE_PCA9552, 0x20); /* eeprom@50 */ - at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); + at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB, + gb200io_eeprom, gb200io_eeprom_len); =20 /* i2c-mux@73 (PCA9546) on i2c0 */ i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73); @@ -345,7 +383,8 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), TYPE_PCA9552, 0x21); /* eeprom@50 */ - at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); + at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB, + gb200io_eeprom, gb200io_eeprom_len); =20 /* i2c-mux@77 (PCA9546) on i2c0 */ i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77); 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617822; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XzoCsiyBMFmffYwLbsFar0Vy3vVAU8xpfAwo2wfzSTU=; b=NLHtYPLTBSkFGm0bYNm3zn3ikZphUw44fqZtoaCQw0tyiI2fwUx2VjBrioo/LcFZS/EiGC uggITdQj0E6MYFA2hlr3gpgNO7u3Euh0/2pKFHAFsXXz0f7TDnYQA+coE1fho4iQNMcKFZ ygL0IAppBDtv5mz0NV1nde3i1lMREhM= X-MC-Unique: itw1C5J-Pv-Z4lDYEnLjxA-1 X-Mimecast-MFC-AGG-ID: itw1C5J-Pv-Z4lDYEnLjxA_1767617817 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 20/36] hw/arm/aspeed: catalina: add HMC FRU EEPROM Date: Mon, 5 Jan 2026 13:55:57 +0100 Message-ID: <20260105125613.622667-21-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617981117154100 From: Patrick Williams Use ipmitool/frugen tool to generate a HMC image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-9-dc7= b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 42 +++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 37f0e1b65e48..2c9b4b6fff9a 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -341,6 +341,46 @@ static const uint8_t gb200io_eeprom[] =3D { }; static const size_t gb200io_eeprom_len =3D sizeof(gb200io_eeprom); =20 +/* + * HMC ("HGX Management Controller") FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "NVIDIA", + * "pname": "P4764-A02 (QEMU)", + * "pn": "000-00000-0000-000", + * "serial": "0000000000000", + * "date": "01/12/2025 00:00", + * "custom": ["Version: G", "Rework: R0"] + * }, + * "product": { + * "mfg": "NVIDIA", + * "pname": "HMC for GB200 NVL72", + * "pn": "100-00000-0000-001", + * "ver": "A1", + * "serial": "1000000000001", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t hmc_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x8c, + 0x19, 0xf0, 0x85, 0xae, 0x9d, 0x92, 0x69, 0x08, 0x8c, 0x30, 0x75, 0x59, + 0x54, 0x13, 0x42, 0x12, 0x80, 0xc4, 0x65, 0x5b, 0x27, 0x8a, 0x10, 0x04, + 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x8e, 0x10, 0x04, 0x35, + 0x10, 0x04, 0x41, 0x50, 0x03, 0x41, 0x10, 0xd4, 0x40, 0x10, 0x04, 0xc0, + 0xca, 0x56, 0x65, 0x72, 0x73, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x47, 0xca, + 0x52, 0x65, 0x77, 0x6f, 0x72, 0x6b, 0x3a, 0x20, 0x52, 0x30, 0xc1, 0x00, + 0x00, 0x00, 0x00, 0x81, 0x01, 0x09, 0x19, 0x85, 0xae, 0x9d, 0x92, 0x69, + 0x08, 0xd3, 0x48, 0x4d, 0x43, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x47, 0x42, + 0x32, 0x30, 0x30, 0x20, 0x4e, 0x56, 0x4c, 0x37, 0x32, 0x8e, 0x11, 0x04, + 0x35, 0x10, 0x04, 0x41, 0x50, 0x03, 0x41, 0x10, 0xd4, 0x40, 0x50, 0x04, + 0x82, 0x61, 0x04, 0x8a, 0x11, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, + 0x41, 0x11, 0x83, 0x71, 0xd9, 0xd6, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x65 +}; +static const size_t hmc_eeprom_len =3D sizeof(hmc_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -493,7 +533,7 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) /* eeprom@55 */ at24c_eeprom_init(i2c[13], 0x55, 256); /* eeprom@57 */ - at24c_eeprom_init(i2c[13], 0x57, 256); + at24c_eeprom_init_rom(i2c[13], 0x57, 256, hmc_eeprom, hmc_eeprom_len); =20 /* &i2c14 */ /* io_expander9 - pca9555@10 */ --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767631833; cv=none; d=zohomail.com; s=zohoarc; b=aldblcYN/nAdWUptVasmK1Ydj12+Yx2Oji5eyUuZLA5PLP3Ta37foA8CTs08QP2ahsHce/7N543piJsp2kAWQ6y5iGEKQQqLYGwrj7eJpCjDTuXBOHf+JERn+U8EiaxHw/BnT/EqKnFPgEoccErjkHnVZvq1xjamRjXyacLoHhg= ARC-Message-Signature: i=1; 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Mon, 5 Jan 2026 12:56:59 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id F153519560A7; Mon, 5 Jan 2026 12:56:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617823; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hKFLzSZUEZIFGnRslnS9T4ahjKX/cHwQ4f2c+hz45ZI=; b=HBiH+GVmNsQpTKbS3zEcCPnbMUFXuEd2CRoBdejPQF+Ray9wGf2cm3oxksjnCJS4D3DBb7 YcoAnTtI0Xlqs6WMyeGuGdwktr9d/2uUk0huTDimJo9rtPQXwfVcTriVLjkCq/jYaPWNqL ViqU5WZuHWlyZmupmOO+LkHef06Ge2Q= X-MC-Unique: tPCiZenUMh2p49jsuHB1fg-1 X-Mimecast-MFC-AGG-ID: tPCiZenUMh2p49jsuHB1fg_1767617819 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 21/36] hw/arm/aspeed: catalina: add NIC FRU EEPROM Date: Mon, 5 Jan 2026 13:55:58 +0100 Message-ID: <20260105125613.622667-22-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767631835935158500 From: Patrick Williams Use ipmitool/frugen tool to generate a CX-7 NIC image based on a sanitized set of data from a real device EEPROM. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-10-dc= 7b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 42 ++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 2c9b4b6fff9a..5044441f38d7 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -381,6 +381,44 @@ static const uint8_t hmc_eeprom[] =3D { }; static const size_t hmc_eeprom_len =3D sizeof(hmc_eeprom); =20 +/* + * CX-7 NIC FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "Nvidia", + * "pname": "Nvidia ConnectX-7 OCP3.0 (QEMU)", + * "pn": "CX70000000-000_00", + * "serial": "000000000000", + * "date": "01/12/2025 00:00" + * }, + * "product": { + * "mfg": "Nvidia", + * "pname": "Nvidia ConnectX-7 OCP3.0", + * "pn": "CX71000000-000_01", + * "ver": "A7", + * "serial": "100000000001", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t nic_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0xf4, 0x01, 0x09, 0x19, 0x8c, + 0x19, 0xf0, 0xc6, 0x4e, 0x76, 0x69, 0x64, 0x69, 0x61, 0xdf, 0x4e, 0x76, + 0x69, 0x64, 0x69, 0x61, 0x20, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, + 0x58, 0x2d, 0x37, 0x20, 0x4f, 0x43, 0x50, 0x33, 0x2e, 0x30, 0x20, 0x28, + 0x51, 0x45, 0x4d, 0x55, 0x29, 0x89, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, + 0x10, 0x04, 0x41, 0x8d, 0x23, 0x7e, 0x41, 0x10, 0x04, 0x41, 0x10, 0xd4, + 0x40, 0x10, 0xf4, 0x43, 0x10, 0xc0, 0xc1, 0xc3, 0x01, 0x09, 0x19, 0xc6, + 0x4e, 0x76, 0x69, 0x64, 0x69, 0x61, 0xd8, 0x4e, 0x76, 0x69, 0x64, 0x69, + 0x61, 0x20, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x37, + 0x20, 0x4f, 0x43, 0x50, 0x33, 0x2e, 0x30, 0x8d, 0x23, 0x7e, 0x45, 0x10, + 0x04, 0x41, 0x10, 0xd4, 0x40, 0x10, 0xf4, 0x43, 0x11, 0x82, 0xe1, 0x05, + 0x89, 0x11, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x45, 0x83, 0x71, + 0xd9, 0xd6, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0xf3 +}; +static const size_t nic_eeprom_len =3D sizeof(nic_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -514,7 +552,7 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) /* temperature-sensor@1f - tpm421 */ i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f); /* eeprom@50 */ - at24c_eeprom_init(i2c[10], 0x50, 8 * KiB); + at24c_eeprom_init_rom(i2c[10], 0x50, 8 * KiB, nic_eeprom, nic_eeprom_l= en); =20 /* &i2c11 */ /* ssif-bmc@10 - no model */ @@ -553,7 +591,7 @@ static void catalina_bmc_i2c_init(AspeedMachineState *b= mc) /* temperature-sensor@1f - tmp421 */ i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f); /* eeprom@52 */ - at24c_eeprom_init(i2c[15], 0x52, 8 * KiB); + at24c_eeprom_init_rom(i2c[15], 0x52, 8 * KiB, nic_eeprom, nic_eeprom_l= en); } =20 static void aspeed_machine_catalina_class_init(ObjectClass *oc, --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617824; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JVZDGTnneiiEsr9/YzGC7XE1ut9z/hM7iMuXqfl4I90=; b=I4/fOM3B9vDZTmYWr38EcB0JqhpajlsRKur4KwoWATe7hzIhxiTHx9lX1TuMcESYri34S0 9ixXbq65Ji5gStDBMbwmIoRQ91SQFPXaJyMDUpZYD6nIqta9Fq2KWHn639t8dRoierHEvf 8kemV/xZ0wx3M2oDPgfwRSDCHdrCus8= X-MC-Unique: m-yMS8V2MpusPzSiGNfIHg-1 X-Mimecast-MFC-AGG-ID: m-yMS8V2MpusPzSiGNfIHg_1767617821 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Patrick Williams , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 22/36] hw/arm/aspeed: catalina: add Cable Cartridge FRU EEPROM Date: Mon, 5 Jan 2026 13:55:59 +0100 Message-ID: <20260105125613.622667-23-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620425203154100 From: Patrick Williams Use ipmitool/frugen tool to generate a Cable Cart image based on a sanitized set of data from a real device EEPROM. The EEPROM bus/address did not match device tree for one of the EEPROMs so move it from bus 13 / 55 to bus 12 / 54. Signed-off-by: Patrick Williams Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251217-catalina-eeproms-v1-11-dc= 7b276efd57@stwcx.xyz Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast2600_catalina.c | 46 +++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catal= ina.c index 5044441f38d7..4edb30bb16b8 100644 --- a/hw/arm/aspeed_ast2600_catalina.c +++ b/hw/arm/aspeed_ast2600_catalina.c @@ -419,6 +419,44 @@ static const uint8_t nic_eeprom[] =3D { }; static const size_t nic_eeprom_len =3D sizeof(nic_eeprom); =20 +/* + * Cable Cartridge FRU data. Generated with frugen. + * + * { + * "board": { + * "mfg": "Nvidia", + * "pname": "18x1RU CBL Cartridge (QEMU)", + * "pn": "000-0000-000", + * "serial": "0000000000000", + * "date": "01/12/2025 00:00" + * }, + * "product": { + * "mfg": "Nvidia", + * "pname": "18x1RU CBL Cartridge", + * "pn": "100-00000-0000-001", + * "ver": "E.4", + * "serial": "1000000000001", + * "atag": "QEMU" + * } + * } + */ +static const uint8_t cable_eeprom[] =3D { + 0x01, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0xf4, 0x01, 0x09, 0x19, 0x8c, + 0x19, 0xf0, 0xc6, 0x4e, 0x76, 0x69, 0x64, 0x69, 0x61, 0xdb, 0x31, 0x38, + 0x78, 0x31, 0x52, 0x55, 0x20, 0x43, 0x42, 0x4c, 0x20, 0x43, 0x61, 0x72, + 0x74, 0x72, 0x69, 0x64, 0x67, 0x65, 0x20, 0x28, 0x51, 0x45, 0x4d, 0x55, + 0x29, 0x8a, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, + 0x89, 0x10, 0x04, 0x35, 0x10, 0x04, 0x41, 0x0d, 0x04, 0x41, 0xc0, 0xc1, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb1, 0x01, 0x09, 0x19, 0xc6, + 0x4e, 0x76, 0x69, 0x64, 0x69, 0x61, 0xd4, 0x31, 0x38, 0x78, 0x31, 0x52, + 0x55, 0x20, 0x43, 0x42, 0x4c, 0x20, 0x43, 0x61, 0x72, 0x74, 0x72, 0x69, + 0x64, 0x67, 0x65, 0x8e, 0x11, 0x04, 0x35, 0x10, 0x04, 0x41, 0x50, 0x03, + 0x41, 0x10, 0xd4, 0x40, 0x50, 0x04, 0x83, 0xa5, 0x43, 0x01, 0x8a, 0x11, + 0x04, 0x41, 0x10, 0x04, 0x41, 0x10, 0x04, 0x41, 0x11, 0x83, 0x71, 0xd9, + 0xd6, 0xc0, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x25 +}; +static const size_t cable_eeprom_len =3D sizeof(cable_eeprom); + static void catalina_bmc_i2c_init(AspeedMachineState *bmc) { /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ @@ -561,15 +599,17 @@ static void catalina_bmc_i2c_init(AspeedMachineState = *bmc) /* eeprom@50 */ at24c_eeprom_init_rom(i2c[12], 0x50, 8 * KiB, gb200_eeprom, gb200_eeprom_len); + /* eeprom@54 */ + at24c_eeprom_init_rom(i2c[12], 0x54, 256, + cable_eeprom, cable_eeprom_len); =20 /* &i2c13 */ /* eeprom@50 */ at24c_eeprom_init_rom(i2c[13], 0x50, 8 * KiB, gb200_eeprom, gb200_eeprom_len); /* eeprom@54 */ - at24c_eeprom_init(i2c[13], 0x54, 256); - /* eeprom@55 */ - at24c_eeprom_init(i2c[13], 0x55, 256); + at24c_eeprom_init_rom(i2c[13], 0x54, 256, + cable_eeprom, cable_eeprom_len); /* eeprom@57 */ at24c_eeprom_init_rom(i2c[13], 0x57, 256, hmc_eeprom, hmc_eeprom_len); =20 --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617828; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2tCMD84IGf4Vsqx5fEI1vPIx4poAsnadZX2OcXtZz4w=; b=aSxxRxAVgCBrquhdycH/O1n6vhzoAZ/tXssiiz78Pp2jbeubl5rOszEVH3Dx76TgFYwGhr t7W4lnOMOtg3kIEYttAEv7DDQcHeANRBblnYN8/ro+TVSv3+b/mXj/wJGz5Hil6z9myqR7 5Uwimt1xRyB/MPyvf3OZefVtenvQGLU= X-MC-Unique: cfCqArDdNU-02eyLysAVRg-1 X-Mimecast-MFC-AGG-ID: cfCqArDdNU-02eyLysAVRg_1767617823 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yubin Zou , Kane Chen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 23/36] hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO Date: Mon, 5 Jan 2026 13:56:00 +0100 Message-ID: <20260105125613.622667-24-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617912007154100 From: Yubin Zou This initial implementation includes the basic device structure, memory-mapped register definitions, and read/write handlers for the SGPIO control registers. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-1-fd55931= 78144@google.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/gpio/aspeed_sgpio.h | 66 +++++++++++++++ hw/gpio/aspeed_sgpio.c | 145 +++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + 3 files changed, 212 insertions(+) create mode 100644 include/hw/gpio/aspeed_sgpio.h create mode 100644 hw/gpio/aspeed_sgpio.c diff --git a/include/hw/gpio/aspeed_sgpio.h b/include/hw/gpio/aspeed_sgpio.h new file mode 100644 index 000000000000..7da48920eebf --- /dev/null +++ b/include/hw/gpio/aspeed_sgpio.h @@ -0,0 +1,66 @@ +/* + * ASPEED Serial GPIO Controller + * + * Copyright 2025 Google LLC. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_SGPIO_H +#define ASPEED_SGPIO_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "hw/core/registerfields.h" + +#define TYPE_ASPEED_SGPIO "aspeed.sgpio" +OBJECT_DECLARE_TYPE(AspeedSGPIOState, AspeedSGPIOClass, ASPEED_SGPIO) + +#define ASPEED_SGPIO_MAX_PIN_PAIR 256 +#define ASPEED_SGPIO_MAX_INT 8 + +/* AST2700 SGPIO Register Address Offsets */ +REG32(SGPIO_INT_STATUS_0, 0x40) +REG32(SGPIO_INT_STATUS_1, 0x44) +REG32(SGPIO_INT_STATUS_2, 0x48) +REG32(SGPIO_INT_STATUS_3, 0x4C) +REG32(SGPIO_INT_STATUS_4, 0x50) +REG32(SGPIO_INT_STATUS_5, 0x54) +REG32(SGPIO_INT_STATUS_6, 0x58) +REG32(SGPIO_INT_STATUS_7, 0x5C) +/* AST2700 SGPIO_0 - SGPIO_255 Control Register */ +REG32(SGPIO_0_CONTROL, 0x80) + SHARED_FIELD(SGPIO_SERIAL_OUT_VAL, 0, 1) + SHARED_FIELD(SGPIO_PARALLEL_OUT_VAL, 1, 1) + SHARED_FIELD(SGPIO_INT_EN, 2, 1) + SHARED_FIELD(SGPIO_INT_TYPE, 3, 3) + SHARED_FIELD(SGPIO_RESET_POLARITY, 6, 1) + SHARED_FIELD(SGPIO_RESERVED_1, 7, 2) + SHARED_FIELD(SGPIO_INPUT_MASK, 9, 1) + SHARED_FIELD(SGPIO_PARALLEL_EN, 10, 1) + SHARED_FIELD(SGPIO_PARALLEL_IN_MODE, 11, 1) + SHARED_FIELD(SGPIO_INT_STATUS, 12, 1) + SHARED_FIELD(SGPIO_SERIAL_IN_VAL, 13, 1) + SHARED_FIELD(SGPIO_PARALLEL_IN_VAL, 14, 1) + SHARED_FIELD(SGPIO_RESERVED_2, 15, 12) + SHARED_FIELD(SGPIO_WRITE_PROTECT, 31, 1) +REG32(SGPIO_255_CONTROL, 0x47C) + +struct AspeedSGPIOClass { + SysBusDeviceClass parent_class; + uint32_t nr_sgpio_pin_pairs; + uint64_t mem_size; + const MemoryRegionOps *reg_ops; +}; + +struct AspeedSGPIOState { + /* */ + SysBusDevice parent; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq irq; + uint32_t ctrl_regs[ASPEED_SGPIO_MAX_PIN_PAIR]; + uint32_t int_regs[ASPEED_SGPIO_MAX_INT]; +}; + +#endif /* ASPEED_SGPIO_H */ diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c new file mode 100644 index 000000000000..538fb5145c3d --- /dev/null +++ b/hw/gpio/aspeed_sgpio.c @@ -0,0 +1,145 @@ +/* + * ASPEED Serial GPIO Controller + * + * Copyright 2025 Google LLC. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "hw/core/qdev-properties.h" +#include "hw/gpio/aspeed_sgpio.h" + +static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s, + uint32_t reg) +{ + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_GET_CLASS(s); + uint32_t idx =3D reg - R_SGPIO_0_CONTROL; + if (idx >=3D agc->nr_sgpio_pin_pairs) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n= ", + __func__, idx); + return 0; + } + return s->ctrl_regs[idx]; +} + +static void aspeed_sgpio_2700_write_control_reg(AspeedSGPIOState *s, + uint32_t reg, uint64_t data) +{ + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_GET_CLASS(s); + uint32_t idx =3D reg - R_SGPIO_0_CONTROL; + if (idx >=3D agc->nr_sgpio_pin_pairs) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n= ", + __func__, idx); + return; + } + s->ctrl_regs[idx] =3D data; +} + +static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset, + uint32_t size) +{ + AspeedSGPIOState *s =3D ASPEED_SGPIO(opaque); + uint64_t value =3D 0; + uint64_t reg; + + reg =3D offset >> 2; + + switch (reg) { + case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: + value =3D aspeed_sgpio_2700_read_control_reg(s, reg); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return 0; + } + + return value; +} + +static void aspeed_sgpio_2700_write(void *opaque, hwaddr offset, uint64_t = data, + uint32_t size) +{ + AspeedSGPIOState *s =3D ASPEED_SGPIO(opaque); + uint64_t reg; + + reg =3D offset >> 2; + + switch (reg) { + case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: + aspeed_sgpio_2700_write_control_reg(s, reg, data); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return; + } +} + +static const MemoryRegionOps aspeed_sgpio_2700_ops =3D { + .read =3D aspeed_sgpio_2700_read, + .write =3D aspeed_sgpio_2700_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static void aspeed_sgpio_realize(DeviceState *dev, Error **errp) +{ + AspeedSGPIOState *s =3D ASPEED_SGPIO(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_GET_CLASS(s); + + /* Interrupt parent line */ + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s, + TYPE_ASPEED_SGPIO, agc->mem_size); + + sysbus_init_mmio(sbd, &s->iomem); +} + +static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_sgpio_realize; + dc->desc =3D "Aspeed SGPIO Controller"; +} + +static void aspeed_sgpio_2700_class_init(ObjectClass *klass, const void *d= ata) +{ + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_CLASS(klass); + agc->nr_sgpio_pin_pairs =3D ASPEED_SGPIO_MAX_PIN_PAIR; + agc->mem_size =3D 0x1000; + agc->reg_ops =3D &aspeed_sgpio_2700_ops; +} + +static const TypeInfo aspeed_sgpio_info =3D { + .name =3D TYPE_ASPEED_SGPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedSGPIOState), + .class_size =3D sizeof(AspeedSGPIOClass), + .class_init =3D aspeed_sgpio_class_init, + .abstract =3D true, +}; + +static const TypeInfo aspeed_sgpio_ast2700_info =3D { + .name =3D TYPE_ASPEED_SGPIO "-ast2700", + .parent =3D TYPE_ASPEED_SGPIO, + .class_init =3D aspeed_sgpio_2700_class_init, +}; + +static void aspeed_sgpio_register_types(void) +{ + type_register_static(&aspeed_sgpio_info); + type_register_static(&aspeed_sgpio_ast2700_info); +} + +type_init(aspeed_sgpio_register_types); diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 74840619c01b..6a67ee958faa 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -16,5 +16,6 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( )) system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio= .c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sgpio.c')) system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c')) --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767617980; cv=none; d=zohomail.com; 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Mon, 5 Jan 2026 12:57:06 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 1B11919560A7; Mon, 5 Jan 2026 12:57:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617831; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ODD8+M+lXInDffmXAIyevk2C2JoBR0MtSv17yxCG0us=; b=YPi6xwdDRf1MtKTG1aEt1p3TOjSiKOXYPrpbd7UH8sZiDTIlCVOe7ptI6pd8MSZtl/Ot/P 54FWKV3ottQCn08Ikvwlzy5cdKMtspTWN43PjEZoi0Wr4FwNr56SHXSV0OGdqKHo4vmnZD /jgcD/a0pTaWnnwO3NvQGgIjjywfJUc= X-MC-Unique: FhG-ZahnOxK5uph1xfKpeQ-1 X-Mimecast-MFC-AGG-ID: FhG-ZahnOxK5uph1xfKpeQ_1767617826 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yubin Zou , Kane Chen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 24/36] hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins Date: Mon, 5 Jan 2026 13:56:01 +0100 Message-ID: <20260105125613.622667-25-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617983150154100 From: Yubin Zou The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are implemented to get and set the level of individual SGPIO pins. These are then exposed as boolean properties on the SGPIO device object. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-2-fd55931= 78144@google.com Signed-off-by: C=C3=A9dric Le Goater --- hw/gpio/aspeed_sgpio.c | 79 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c index 538fb5145c3d..cf5efa70e8d0 100644 --- a/hw/gpio/aspeed_sgpio.c +++ b/hw/gpio/aspeed_sgpio.c @@ -51,6 +51,8 @@ static uint64_t aspeed_sgpio_2700_read(void *opaque, hwad= dr offset, reg =3D offset >> 2; =20 switch (reg) { + case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7: + break; case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: value =3D aspeed_sgpio_2700_read_control_reg(s, reg); break; @@ -82,6 +84,73 @@ static void aspeed_sgpio_2700_write(void *opaque, hwaddr= offset, uint64_t data, } } =20 +static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin) +{ + uint32_t value =3D s->ctrl_regs[pin >> 1]; + bool is_input =3D !(pin % 2); + uint32_t bit_mask =3D 0; + + if (is_input) { + bit_mask =3D SGPIO_SERIAL_IN_VAL_MASK; + } else { + bit_mask =3D SGPIO_SERIAL_OUT_VAL_MASK; + } + + return value & bit_mask; +} + +static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, bool = level) +{ + uint32_t value =3D s->ctrl_regs[pin >> 1]; + bool is_input =3D !(pin % 2); + uint32_t bit_mask =3D 0; + + if (is_input) { + bit_mask =3D SGPIO_SERIAL_IN_VAL_MASK; + } else { + bit_mask =3D SGPIO_SERIAL_OUT_VAL_MASK; + } + + if (level) { + value |=3D bit_mask; + } else { + value &=3D ~bit_mask; + } + s->ctrl_regs[pin >> 1] =3D value; +} + +static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool level =3D true; + int pin =3D 0xfff; + AspeedSGPIOState *s =3D ASPEED_SGPIO(obj); + + if (sscanf(name, "sgpio%03d", &pin) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + level =3D aspeed_sgpio_get_pin_level(s, pin); + visit_type_bool(v, name, &level, errp); +} + +static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool level; + int pin =3D 0xfff; + AspeedSGPIOState *s =3D ASPEED_SGPIO(obj); + + if (!visit_type_bool(v, name, &level, errp)) { + return; + } + if (sscanf(name, "sgpio%03d", &pin) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + aspeed_sgpio_set_pin_level(s, pin, level); +} + static const MemoryRegionOps aspeed_sgpio_2700_ops =3D { .read =3D aspeed_sgpio_2700_read, .write =3D aspeed_sgpio_2700_write, @@ -105,6 +174,15 @@ static void aspeed_sgpio_realize(DeviceState *dev, Err= or **errp) sysbus_init_mmio(sbd, &s->iomem); } =20 +static void aspeed_sgpio_init(Object *obj) +{ + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) { + g_autofree char *name =3D g_strdup_printf("sgpio%03d", i); + object_property_add(obj, name, "bool", aspeed_sgpio_get_pin, + aspeed_sgpio_set_pin, NULL, NULL); + } +} + static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -134,6 +212,7 @@ static const TypeInfo aspeed_sgpio_ast2700_info =3D { .name =3D TYPE_ASPEED_SGPIO "-ast2700", .parent =3D TYPE_ASPEED_SGPIO, .class_init =3D aspeed_sgpio_2700_class_init, + .instance_init =3D aspeed_sgpio_init, }; =20 static void aspeed_sgpio_register_types(void) --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767634728; 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Mon, 5 Jan 2026 12:57:08 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 79CAD1953984; Mon, 5 Jan 2026 12:57:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617832; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4z+D4ZsW6OqU9NquvRk/j5XFtDXv6j6Es+pB2xr6DMA=; b=TtbtBAYBAmCD9UH0oYeMjJHcJM+sLx1ffC1HFOp75N5l46f6GIJ+PqAsWpXJ1ldW21TLl0 CWgviIs6MWViCIbcScekgI3XB79DfFH/erpoAVN4MVE8hWbjU/DhOiDjALbvodClpRnW4d x7AYqDONj91M9XiU0KFVspgdrL5aKUo= X-MC-Unique: aaOJZt5ONoKPLyIZZ5_rcQ-1 X-Mimecast-MFC-AGG-ID: aaOJZt5ONoKPLyIZZ5_rcQ_1767617828 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yubin Zou , Kane Chen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 25/36] hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling Date: Mon, 5 Jan 2026 13:56:02 +0100 Message-ID: <20260105125613.622667-26-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767634729642158500 From: Yubin Zou The SGPIO controller can generate interrupts based on various pin state changes, such as rising/falling edges or high/low levels. This change adds the necessary logic to detect these events, update the interrupt status registers, and signal the interrupt to the SoC. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-3-fd55931= 78144@google.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/gpio/aspeed_sgpio.h | 2 + hw/gpio/aspeed_sgpio.c | 126 ++++++++++++++++++++++++++++++++- 2 files changed, 126 insertions(+), 2 deletions(-) diff --git a/include/hw/gpio/aspeed_sgpio.h b/include/hw/gpio/aspeed_sgpio.h index 7da48920eebf..68276baf81da 100644 --- a/include/hw/gpio/aspeed_sgpio.h +++ b/include/hw/gpio/aspeed_sgpio.h @@ -58,7 +58,9 @@ struct AspeedSGPIOState { =20 /*< public >*/ MemoryRegion iomem; + int pending; qemu_irq irq; + qemu_irq sgpios[ASPEED_SGPIO_MAX_PIN_PAIR]; uint32_t ctrl_regs[ASPEED_SGPIO_MAX_PIN_PAIR]; uint32_t int_regs[ASPEED_SGPIO_MAX_INT]; }; diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c index cf5efa70e8d0..0c53b03464e4 100644 --- a/hw/gpio/aspeed_sgpio.c +++ b/hw/gpio/aspeed_sgpio.c @@ -12,9 +12,130 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "hw/core/irq.h" #include "hw/core/qdev-properties.h" #include "hw/gpio/aspeed_sgpio.h" =20 +/* + * For each set of gpios there are three sensitivity registers that contr= ol + * the interrupt trigger mode. + * + * | 2 | 1 | 0 | trigger mode + * ----------------------------- + * | 0 | 0 | 0 | falling-edge + * | 0 | 0 | 1 | rising-edge + * | 0 | 1 | 0 | level-low + * | 0 | 1 | 1 | level-high + * | 1 | X | X | dual-edge + */ + +/* GPIO Interrupt Triggers */ +#define ASPEED_FALLING_EDGE 0 +#define ASPEED_RISING_EDGE 1 +#define ASPEED_LEVEL_LOW 2 +#define ASPEED_LEVEL_HIGH 3 +#define ASPEED_DUAL_EDGE 4 + +static void aspeed_clear_irq(AspeedSGPIOState *s, int idx) +{ + uint32_t reg_index =3D idx / 32; + uint32_t bit_index =3D idx % 32; + uint32_t pending =3D extract32(s->int_regs[reg_index], bit_index, 1); + + assert(s->pending >=3D pending); + + /* No change to s->pending if pending is 0 */ + s->pending -=3D pending; + + /* + * The write acknowledged the interrupt regardless of whether it + * was pending or not. The post-condition is that it mustn't be + * pending. Unconditionally clear the status bit. + */ + s->int_regs[reg_index] =3D deposit32(s->int_regs[reg_index], bit_index= , 1, 0); +} + +static void aspeed_evaluate_irq(AspeedSGPIOState *s, int sgpio_prev_high, + int sgpio_curr_high, int idx) +{ + uint32_t ctrl =3D s->ctrl_regs[idx]; + uint32_t falling_edge =3D 0, rising_edge =3D 0; + uint32_t int_trigger =3D SHARED_FIELD_EX32(ctrl, SGPIO_INT_TYPE); + uint32_t int_enabled =3D SHARED_FIELD_EX32(ctrl, SGPIO_INT_EN); + uint32_t reg_index =3D idx / 32; + uint32_t bit_index =3D idx % 32; + + if (!int_enabled) { + return; + } + + /* Detect edges */ + if (sgpio_curr_high && !sgpio_prev_high) { + rising_edge =3D 1; + } else if (!sgpio_curr_high && sgpio_prev_high) { + falling_edge =3D 1; + } + + if (((int_trigger =3D=3D ASPEED_FALLING_EDGE) && falling_edge) || + ((int_trigger =3D=3D ASPEED_RISING_EDGE) && rising_edge) || + ((int_trigger =3D=3D ASPEED_LEVEL_LOW) && !sgpio_curr_high) || + ((int_trigger =3D=3D ASPEED_LEVEL_HIGH) && sgpio_curr_high) || + ((int_trigger >=3D ASPEED_DUAL_EDGE) && (rising_edge || falling_e= dge))) + { + s->int_regs[reg_index] =3D deposit32(s->int_regs[reg_index], + bit_index, 1, 1); + /* Trigger the VIC IRQ */ + s->pending++; + } +} + +static void aspeed_sgpio_update(AspeedSGPIOState *s, uint32_t idx, + uint32_t value) +{ + uint32_t old =3D s->ctrl_regs[idx]; + uint32_t new =3D value; + uint32_t diff =3D (old ^ new); + if (diff) { + /* If the interrupt clear bit is set */ + if (SHARED_FIELD_EX32(new, SGPIO_INT_STATUS)) { + aspeed_clear_irq(s, idx); + /* Clear the interrupt clear bit */ + new &=3D ~SGPIO_INT_STATUS_MASK; + } + + /* Update the control register. */ + s->ctrl_regs[idx] =3D new; + + /* If the output value is changed */ + if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_OUT_VAL)) { + /* ...trigger the line-state IRQ */ + qemu_set_irq(s->sgpios[idx], 1); + } + + /* If the input value is changed */ + if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_IN_VAL)) { + aspeed_evaluate_irq(s, + SHARED_FIELD_EX32(old, SGPIO_SERIAL_IN_VAL), + SHARED_FIELD_EX32(new, SGPIO_SERIAL_IN_VAL), + idx); + } + } + qemu_set_irq(s->irq, !!(s->pending)); +} + +static uint64_t aspeed_sgpio_2700_read_int_status_reg(AspeedSGPIOState *s, + uint32_t reg) +{ + uint32_t idx =3D reg - R_SGPIO_INT_STATUS_0; + if (idx >=3D ASPEED_SGPIO_MAX_INT) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: interrupt status index: %d, out of bounds\n", + __func__, idx); + return 0; + } + return s->int_regs[idx]; +} + static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s, uint32_t reg) { @@ -38,7 +159,7 @@ static void aspeed_sgpio_2700_write_control_reg(AspeedSG= PIOState *s, __func__, idx); return; } - s->ctrl_regs[idx] =3D data; + aspeed_sgpio_update(s, idx, data); } =20 static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset, @@ -52,6 +173,7 @@ static uint64_t aspeed_sgpio_2700_read(void *opaque, hwa= ddr offset, =20 switch (reg) { case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7: + value =3D aspeed_sgpio_2700_read_int_status_reg(s, reg); break; case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: value =3D aspeed_sgpio_2700_read_control_reg(s, reg); @@ -116,7 +238,7 @@ static void aspeed_sgpio_set_pin_level(AspeedSGPIOState= *s, int pin, bool level) } else { value &=3D ~bit_mask; } - s->ctrl_regs[pin >> 1] =3D value; + aspeed_sgpio_update(s, pin >> 1, value); } =20 static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name, --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767620348; cv=none; d=zohomail.com; s=zohoarc; b=ApbqL+gXkQKaZQHOztPNe1GhYrPH1HHY6MuVtuCvW0jBgUMbm9YzTClJl5rto4OxknOXMqrI/7PcVDfrW/fG3G0XFKW7P2572xQMYdkYkGdbzZbN7/9dDEgY1uGxCXLvlP+PJoostBn5ONMT7SaXA9xzTIh+RqwBGyK+a47+9Aw= ARC-Message-Signature: i=1; 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Mon, 5 Jan 2026 12:57:11 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id E884B1953984; Mon, 5 Jan 2026 12:57:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617836; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2eN4X3uyfV9cJriJXGMysA4V49qLGAdRFXwkwfMgEWE=; b=ZAeN44N8p9wnHBqH2u1ZeLADO98C9OOWcahd5YG/NjyDbdNaKd+pYJufiaNRKaKyZINdc5 P5yKqMIJ/Hc33vyV45gaT9J8aaqAiJuTtn4VscjsOBATqdzCWRzEmsaVWkjbsa0JFYYiei WE2FjEt68kCbcpTIUJNxg3m9EvreAX0= X-MC-Unique: WwKwJ853MMCFq-PbYxOElg-1 X-Mimecast-MFC-AGG-ID: WwKwJ853MMCFq-PbYxOElg_1767617831 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yubin Zou , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 26/36] hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers Date: Mon, 5 Jan 2026 13:56:03 +0100 Message-ID: <20260105125613.622667-27-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620350038154100 From: Yubin Zou This commit updates the Aspeed SoC model to support two SGPIO controllers, reflecting the hardware capabilities of the AST2700 The memory map and interrupt map are updated to include entries for two SGPIO controllers (SGPIOM0 and SGPIOM1). This change is a prerequisite for the full implementation of the SGPIO device model. Signed-off-by: Yubin Zou Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-4-fd55931= 78144@google.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 8 ++++++-- hw/arm/aspeed_ast10x0.c | 6 +++--- hw/arm/aspeed_ast27x0.c | 10 ++++++++++ 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 4b8e599f1a53..18ff961a3850 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -32,6 +32,7 @@ #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" #include "hw/gpio/aspeed_gpio.h" +#include "hw/gpio/aspeed_sgpio.h" #include "hw/sd/aspeed_sdhci.h" #include "hw/usb/hcd-ehci.h" #include "qom/object.h" @@ -46,6 +47,7 @@ #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 #define ASPEED_SPIS_NUM 3 +#define ASPEED_SGPIO_NUM 2 #define ASPEED_EHCIS_NUM 4 #define ASPEED_WDTS_NUM 8 #define ASPEED_CPUS_NUM 4 @@ -89,6 +91,7 @@ struct AspeedSoCState { AspeedMiiState mii[ASPEED_MACS_NUM]; AspeedGPIOState gpio; AspeedGPIOState gpio_1_8v; + AspeedSGPIOState sgpiom[ASPEED_SGPIO_NUM]; AspeedSDHCIState sdhci; AspeedSDHCIState emmc; AspeedLPCState lpc; @@ -106,7 +109,6 @@ struct AspeedSoCState { UnimplementedDeviceState pwm; UnimplementedDeviceState espi; UnimplementedDeviceState udc; - UnimplementedDeviceState sgpiom; UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; @@ -166,6 +168,7 @@ struct AspeedSoCClass { uint64_t secsram_size; int pcie_num; int spis_num; + int sgpio_num; int ehcis_num; int wdts_num; int macs_num; @@ -221,6 +224,8 @@ enum { ASPEED_DEV_SDHCI, ASPEED_DEV_GPIO, ASPEED_DEV_GPIO_1_8V, + ASPEED_DEV_SGPIOM0, + ASPEED_DEV_SGPIOM1, ASPEED_DEV_RTC, ASPEED_DEV_TIMER1, ASPEED_DEV_TIMER2, @@ -263,7 +268,6 @@ enum { ASPEED_DEV_I3C, ASPEED_DEV_ESPI, ASPEED_DEV_UDC, - ASPEED_DEV_SGPIOM, ASPEED_DEV_JTAG0, ASPEED_DEV_JTAG1, ASPEED_DEV_FSI1, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 44e1d59ddb3c..41a4e82c1f87 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -36,7 +36,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] =3D { [ASPEED_DEV_ESPI] =3D 0x7E6EE000, [ASPEED_DEV_SBC] =3D 0x7E6F2000, [ASPEED_DEV_GPIO] =3D 0x7E780000, - [ASPEED_DEV_SGPIOM] =3D 0x7E780500, + [ASPEED_DEV_SGPIOM0] =3D 0x7E780500, [ASPEED_DEV_TIMER1] =3D 0x7E782000, [ASPEED_DEV_UART1] =3D 0x7E783000, [ASPEED_DEV_UART2] =3D 0x7E78D000, @@ -94,7 +94,7 @@ static const int aspeed_soc_ast1030_irqmap[] =3D { [ASPEED_DEV_I2C] =3D 110, /* 110 ~ 123 */ [ASPEED_DEV_KCS] =3D 138, /* 138 -> 142 */ [ASPEED_DEV_UDC] =3D 9, - [ASPEED_DEV_SGPIOM] =3D 51, + [ASPEED_DEV_SGPIOM0] =3D 51, [ASPEED_DEV_JTAG0] =3D 27, [ASPEED_DEV_JTAG1] =3D 53, }; @@ -406,7 +406,7 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCSta= te *a, Error **errp) sc->memmap[ASPEED_DEV_UDC], 0x1000); aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom", - sc->memmap[ASPEED_DEV_SGPIOM], 0x100); + sc->memmap[ASPEED_DEV_SGPIOM0], 0x100); =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag", diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 95f155fcf1ad..9f471c399491 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -69,6 +69,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_ADC] =3D 0x14C00000, [ASPEED_DEV_SCUIO] =3D 0x14C02000, [ASPEED_DEV_GPIO] =3D 0x14C0B000, + [ASPEED_DEV_SGPIOM0] =3D 0x14C0C000, + [ASPEED_DEV_SGPIOM1] =3D 0x14C0D000, [ASPEED_DEV_I2C] =3D 0x14C0F000, [ASPEED_DEV_INTCIO] =3D 0x14C18000, [ASPEED_DEV_PCIE_PHY2] =3D 0x14C1C000, @@ -122,6 +124,8 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D { [ASPEED_DEV_KCS] =3D 128, [ASPEED_DEV_ADC] =3D 130, [ASPEED_DEV_GPIO] =3D 130, + [ASPEED_DEV_SGPIOM0] =3D 130, + [ASPEED_DEV_SGPIOM1] =3D 130, [ASPEED_DEV_I2C] =3D 130, [ASPEED_DEV_FMC] =3D 131, [ASPEED_DEV_WDT] =3D 131, @@ -173,6 +177,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_I2C] =3D 194, [ASPEED_DEV_ADC] =3D 194, [ASPEED_DEV_GPIO] =3D 194, + [ASPEED_DEV_SGPIOM0] =3D 194, + [ASPEED_DEV_SGPIOM1] =3D 194, [ASPEED_DEV_FMC] =3D 195, [ASPEED_DEV_WDT] =3D 195, [ASPEED_DEV_PWM] =3D 195, @@ -214,6 +220,8 @@ static const int ast2700_gic130_gic194_intcmap[] =3D { [ASPEED_DEV_I2C] =3D 0, [ASPEED_DEV_ADC] =3D 16, [ASPEED_DEV_GPIO] =3D 18, + [ASPEED_DEV_SGPIOM0] =3D 21, + [ASPEED_DEV_SGPIOM1] =3D 24, }; =20 /* GICINT 131 */ @@ -1063,6 +1071,7 @@ static void aspeed_soc_ast2700a0_class_init(ObjectCla= ss *oc, const void *data) sc->sram_size =3D 0x20000; sc->pcie_num =3D 0; sc->spis_num =3D 3; + sc->sgpio_num =3D 2; sc->ehcis_num =3D 2; sc->wdts_num =3D 8; sc->macs_num =3D 1; @@ -1091,6 +1100,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->sram_size =3D 0x20000; sc->pcie_num =3D 3; sc->spis_num =3D 3; + sc->sgpio_num =3D 2; sc->ehcis_num =3D 4; sc->wdts_num =3D 8; sc->macs_num =3D 3; --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767617978; cv=none; d=zohomail.com; s=zohoarc; b=EWNZqc+bP7Qm+8Kt33OFi0IiFtUIBsgJE/8C4Qw633gSFwKXKD1Xyaxn3KOB/roz2lAY8QTIedGMylZtv56oQKRYvai4bDehzuQ+eM50y4GfFo1RYZuxR9U7us+IK+t8xXCfgFlnZklnitOGFyUhEKWfM8HlolX1yrHD0c+v+uc= ARC-Message-Signature: i=1; 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Mon, 5 Jan 2026 12:57:13 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A55B91953984; Mon, 5 Jan 2026 12:57:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617835; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qJiqQOiiuVQUHxcT633H/HXmNFo7n9Ya1EAjY7hqJhg=; b=h4qAOiLv3fvvCe6TrNC521Kvl2xOUC7SIEjj0q4dAvyaA2rU1yuu0MlMa9IE8OEqPl3nel F6bH1H6WDQY5JmxTDCYBlHoV+yQQ2k5IGIlW0WeYoh4nK1hUNU9JTW1g1hu62jZ5hO71Aq vpu47+oTueNambCqCPYu4BKq4DnkI5w= X-MC-Unique: vYyNX9iJMxWD8tEbwrIRRw-1 X-Mimecast-MFC-AGG-ID: vYyNX9iJMxWD8tEbwrIRRw_1767617833 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yubin Zou , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 27/36] hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC Date: Mon, 5 Jan 2026 13:56:04 +0100 Message-ID: <20260105125613.622667-28-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767617981217154100 From: Yubin Zou This commit integrates the Aspeed SGPIO controller into the AST2700 Signed-off-by: Yubin Zou Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-5-fd55931= 78144@google.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 9f471c399491..70be3871bb12 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -519,6 +519,11 @@ static void aspeed_soc_ast2700_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "gpio", &s->gpio, typename); =20 + snprintf(typename, sizeof(typename), "aspeed.sgpio-%s", socname); + for (i =3D 0; i < sc->sgpio_num; i++) { + object_initialize_child(obj, "sgpio[*]", &s->sgpiom[i], typename); + } + object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); =20 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); @@ -975,6 +980,17 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); =20 + /* SGPIO */ + for (i =3D 0; i < sc->sgpio_num; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sgpiom[i]), 0, + sc->memmap[ASPEED_DEV_SGPIOM0 + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sgpiom[i]), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SGPIOM0 += i)); + } + /* RTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { return; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617838; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WywNb9c2fzJnvtKkFHYliMsQCyp82+NRD4M44Nd+htY=; b=c9cXtf/1IZ/drOIRlFR9USWeK9DQAg3RUkZy6UVfFtCeOZ4uWDr0LgR5ZXLYEpF7D5GXDv 8OuCiRRpeeUE7qb/Wmr4VeDVapXM2nTT3a1Ar1N9yKLuTSCBC8bOYhVUV+MHYwz5DWMnGr 55xq/WUj2hleb6p/xY8MrRK55O4B+KM= X-MC-Unique: _SqLYMxOMraM71N3DFSSZg-1 X-Mimecast-MFC-AGG-ID: _SqLYMxOMraM71N3DFSSZg_1767617835 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yubin Zou , Kane Chen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 28/36] test/qtest: Add Unit test for Aspeed SGPIO Date: Mon, 5 Jan 2026 13:56:05 +0100 Message-ID: <20260105125613.622667-29-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620561100154100 From: Yubin Zou This commit introduces a new qtest for the Aspeed SGPIO controller The test covers the following: - Setting and clearing SGPIO output pins and verifying the pin state. - Setting and clearing SGPIO input pins and verifying the pin state. - Verifying that level-high interrupts are correctly triggered and cleare= d. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen Link: https://lore.kernel.org/qemu-devel/20251219-aspeed-sgpio-v5-6-fd55931= 78144@google.com Signed-off-by: C=C3=A9dric Le Goater --- tests/qtest/ast2700-sgpio-test.c | 165 +++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 166 insertions(+) create mode 100644 tests/qtest/ast2700-sgpio-test.c diff --git a/tests/qtest/ast2700-sgpio-test.c b/tests/qtest/ast2700-sgpio-t= est.c new file mode 100644 index 000000000000..56c54cca9b63 --- /dev/null +++ b/tests/qtest/ast2700-sgpio-test.c @@ -0,0 +1,165 @@ +/* + * QTest testcase for the ASPEED AST2700 SGPIO Controller. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2025 Google LLC. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qobject/qdict.h" +#include "libqtest-single.h" +#include "hw/core/registerfields.h" +#include "hw/gpio/aspeed_sgpio.h" + +#define AST2700_SGPIO0_BASE 0x14C0C000 +#define AST2700_SGPIO1_BASE 0x14C0D000 + +static void test_output_pins(const char *machine, const uint32_t base, int= idx) +{ + QTestState *s =3D qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t offset =3D 0; + uint32_t value =3D 0; + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Odd index is output port */ + sprintf(name, "sgpio%03d", i * 2 + 1); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + offset =3D base + (R_SGPIO_0_CONTROL + i) * 4; + /* set serial output */ + qtest_writel(s, offset, 0x00000001); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), = =3D=3D, 1); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, tru= e); + + /* clear serial output */ + qtest_writel(s, offset, 0x00000000); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), = =3D=3D, 0); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, fal= se); + } + qtest_quit(s); +} + +static void test_input_pins(const char *machine, const uint32_t base, int = idx) +{ + QTestState *s =3D qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t offset =3D 0; + uint32_t value =3D 0; + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Even index is input port */ + sprintf(name, "sgpio%03d", i * 2); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + offset =3D base + (R_SGPIO_0_CONTROL + i) * 4; + /* set serial input */ + qtest_qom_set_bool(s, qom_path, name, true); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 1); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, tru= e); + + /* clear serial input */ + qtest_qom_set_bool(s, qom_path, name, false); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 0); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, fal= se); + } + qtest_quit(s); +} + +static void test_irq_level_high(const char *machine, + const uint32_t base, int idx) +{ + QTestState *s =3D qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t ctrl_offset =3D 0; + uint32_t int_offset =3D 0; + uint32_t int_reg_idx =3D 0; + uint32_t int_bit_idx =3D 0; + uint32_t value =3D 0; + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Even index is input port */ + sprintf(name, "sgpio%03d", i * 2); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + int_reg_idx =3D i / 32; + int_bit_idx =3D i % 32; + int_offset =3D base + (R_SGPIO_INT_STATUS_0 + int_reg_idx) * 4; + ctrl_offset =3D base + (R_SGPIO_0_CONTROL + i) * 4; + + /* Enable the interrupt */ + value =3D SHARED_FIELD_DP32(value, SGPIO_INT_EN, 1); + qtest_writel(s, ctrl_offset, value); + + /* Set the interrupt type to level-high trigger */ + value =3D SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), + SGPIO_INT_TYPE, 3); + qtest_writel(s, ctrl_offset, value); + + /* Set serial input high */ + qtest_qom_set_bool(s, qom_path, name, true); + value =3D qtest_readl(s, ctrl_offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 1); + + /* Interrupt status is set */ + value =3D qtest_readl(s, int_offset); + g_assert_cmphex(extract32(value, int_bit_idx, 1), =3D=3D, 1); + + /* Clear Interrupt */ + value =3D SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), + SGPIO_INT_STATUS, 1); + qtest_writel(s, ctrl_offset, value); + value =3D qtest_readl(s, int_offset); + g_assert_cmphex(extract32(value, int_bit_idx, 1), =3D=3D, 0); + + /* Clear serial input */ + qtest_qom_set_bool(s, qom_path, name, false); + value =3D qtest_readl(s, ctrl_offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 0); + } + qtest_quit(s); +} + +static void test_ast_2700_sgpio_input(void) +{ + test_input_pins("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_input_pins("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +static void test_ast_2700_sgpio_output(void) +{ + test_output_pins("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_output_pins("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +static void test_ast_2700_sgpio_irq(void) +{ + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_input", + test_ast_2700_sgpio_input); + qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_output", + test_ast_2700_sgpio_output); + qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_irq", + test_ast_2700_sgpio_irq); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 08fba9695b98..0f053fb56de5 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -221,6 +221,7 @@ qtests_aspeed =3D \ qtests_aspeed64 =3D \ ['ast2700-gpio-test', 'ast2700-hace-test', + 'ast2700-sgpio-test', 'ast2700-smc-test'] =20 qtests_stm32l4x5 =3D \ --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617840; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gUSrHrWXsYiAofCo/hJotjUzkEJ1WydAy1nzr+S3xuQ=; b=N/0A5lYBk84BENW0fCDmIKgCE/J70zL+E4Pxivt8E0WSB4KHfXqjnlTLy6Z7QqycQ/KoPI LgaprC3ClFu6jqtRDX+mbFL8dkkOMtyKA89qmPqUZQ/ye6JDmppbJu1nxVAXt4/2YIKTjK nf/YVNgXea1CV9JRWFaHYOuusj8NCkU= X-MC-Unique: zt--GEy_OE6aSuSXqb7maQ-1 X-Mimecast-MFC-AGG-ID: zt--GEy_OE6aSuSXqb7maQ_1767617837 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Ed Tanous , Patrick Williams , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 29/36] tests/functional: Fix URL of gb200nvl-bmc image Date: Mon, 5 Jan 2026 13:56:06 +0100 Message-ID: <20260105125613.622667-30-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767629097928139101 Commit [1] moved the FW image of the gb200nvl-bmc machine and broke the associated functional test. Fix that. [1] https://github.com/legoater/qemu-aspeed-boot/commit/52451b2472eeb40aa97= e131aeea327e9d4a8a78a Cc: Ed Tanous Cc: Patrick Williams Tested-by: Philippe Mathieu-Daud=C3=A9 Link: https://lore.kernel.org/qemu-devel/20251222073351.166720-1-clg@redhat= .com Signed-off-by: C=C3=A9dric Le Goater --- tests/functional/arm/test_aspeed_gb200nvl_bmc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/functional/arm/test_aspeed_gb200nvl_bmc.py b/tests/funct= ional/arm/test_aspeed_gb200nvl_bmc.py index 8e8e3f05c1b2..e5f2dce0f569 100755 --- a/tests/functional/arm/test_aspeed_gb200nvl_bmc.py +++ b/tests/functional/arm/test_aspeed_gb200nvl_bmc.py @@ -11,7 +11,7 @@ class GB200Machine(AspeedTest): =20 ASSET_GB200_FLASH =3D Asset( - 'https://github.com/legoater/qemu-aspeed-boot/raw/refs/heads/maste= r/images/gb200nvl-obmc/obmc-phosphor-image-gb200nvl-obmc-20250702182348.sta= tic.mtd.xz', + 'https://github.com/legoater/qemu-aspeed-boot/raw/refs/heads/maste= r/images/gb200nvl-bmc/openbmc-20250702182348/obmc-phosphor-image-gb200nvl-o= bmc-20250702182348.static.mtd.xz', 'b84819317cb3dc762895ad507705978ef000bfc77c50c33a63bdd37921db0dbc') =20 def test_arm_aspeed_gb200_openbmc(self): --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dUNgTCcgVwMHoRdHx+5eUBcnLo70zMvS6I1BEpTwZDs=; b=W7SCC17voWxacpQ+rtzxRZ/hfpUeWHKzS8NVgSsl/PxfUMlKg5DPkRhOjYhzuSOtEnndEX KUtDFVDJHjElNfEGdZZjbuv/Tw1vcZM5blK6usYUSR1YAtif5T+WKvZ7E65xgNbzj7u77o E58E8wmqisfmF7lewvF0iprO16PTUXw= X-MC-Unique: k9RJQIkBNnOYT-gWkwdDJg-1 X-Mimecast-MFC-AGG-ID: k9RJQIkBNnOYT-gWkwdDJg_1767617839 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 30/36] hw/arm: Remove ast2700a0-evb machine Date: Mon, 5 Jan 2026 13:56:07 +0100 Message-ID: <20260105125613.622667-31-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620577420154100 From: Jamin Lin The ast2700a0-evb machine represents the first revision of the AST2700 and serves as the initial engineering sample rather than a production version. A newer revision, A1, is now supported, and the ast2700a1-evb should replace the older A0 version. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-2-jamin_lin= @aspeedtech.com [ clg: Updated docs/about/removed-features.rst ] Signed-off-by: C=C3=A9dric Le Goater --- docs/about/deprecated.rst | 8 -------- docs/about/removed-features.rst | 8 ++++++++ hw/arm/aspeed_ast27x0_evb.c | 26 -------------------------- 3 files changed, 8 insertions(+), 34 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index ac31a2bce427..7abb3dab592b 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -280,14 +280,6 @@ deprecated; use the new name ``dtb-randomness`` instea= d. The new name better reflects the way this property affects all random data within the device tree blob, not just the ``kaslr-seed`` node. =20 -Arm ``ast2700a0-evb`` machine (since 10.1) -'''''''''''''''''''''''''''''''''''''''''' - -The ``ast2700a0-evb`` machine represents the first revision of the AST2700 -and serves as the initial engineering sample rather than a production vers= ion. -A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should -replace the older A0 version. - Arm ``sonorapass-bmc`` machine (since 10.2) ''''''''''''''''''''''''''''''''''''''''''' =20 diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index 422b9c98d354..e81d79da47f2 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -1136,6 +1136,14 @@ Mips ``mipssim`` machine (removed in 10.2) Linux dropped support for this virtual machine type in kernel v3.7, and there was also no binary available online to use with that board. =20 +Arm ``ast2700a0-evb`` machine (since 11.0) +'''''''''''''''''''''''''''''''''''''''''' + +The ``ast2700a0-evb`` machine represents the first revision of the AST2700 +and serves as the initial engineering sample rather than a production vers= ion. +A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should +replace the older A0 version. + linux-user mode CPUs -------------------- =20 diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c index 0c4e9cd9cd8e..31f7d61117a9 100644 --- a/hw/arm/aspeed_ast27x0_evb.c +++ b/hw/arm/aspeed_ast27x0_evb.c @@ -28,27 +28,6 @@ static void ast2700_evb_i2c_init(AspeedMachineState *bmc) TYPE_TMP105, 0x4d); } =20 -static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); - - mc->desc =3D "Aspeed AST2700 A0 EVB (Cortex-A35)"; - amc->soc_name =3D "ast2700-a0"; - amc->hw_strap1 =3D AST2700_EVB_HW_STRAP1; - amc->hw_strap2 =3D AST2700_EVB_HW_STRAP2; - amc->fmc_model =3D "w25q01jvq"; - amc->spi_model =3D "w25q512jv"; - amc->num_cs =3D 2; - amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; - amc->uart_default =3D ASPEED_DEV_UART12; - amc->i2c_init =3D ast2700_evb_i2c_init; - amc->vbootrom =3D true; - mc->default_ram_size =3D 1 * GiB; - aspeed_machine_class_init_cpus_defaults(mc); -} - static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, const void *data) { @@ -73,11 +52,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(Obje= ctClass *oc, =20 static const TypeInfo aspeed_ast27x0_evb_types[] =3D { { - .name =3D MACHINE_TYPE_NAME("ast2700a0-evb"), - .parent =3D TYPE_ASPEED_MACHINE, - .class_init =3D aspeed_machine_ast2700a0_evb_class_init, - .interfaces =3D aarch64_machine_interfaces, - }, { .name =3D MACHINE_TYPE_NAME("ast2700a1-evb"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_ast2700a1_evb_class_init, --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617845; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9nyCI6Sy88qGcEs2t2mZ8Esp7vOW+H+nEdg2NcqpXI4=; b=XYAuGFQ0BQ0/Z+O7q1/bVWdIRXY5rbP+Sfu+WywjGUPEwV8oqvhAGht2k0rhRJyt+G6A7b R2yFumTVv12o/0y8B9ODkSi5f2W+ep7CtFqcwUPgOTz2O/Y2n+IOTQ7H4EtSX+VC4ajCDA 7KtCeWpUk3KHIsw4AcY4M+48fSmpmF4= X-MC-Unique: NhSc7oMpMCuU-THUww-wgw-1 X-Mimecast-MFC-AGG-ID: NhSc7oMpMCuU-THUww-wgw_1767617841 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 31/36] hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC Date: Mon, 5 Jan 2026 13:56:08 +0100 Message-ID: <20260105125613.622667-32-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767621146809154100 From: Jamin Lin The ast2700-a1 SOC represented the first revision of the AST2700 and was intended as an early engineering sample rather than a production platform. A newer revision, A1, is now supported, and the ast2700-a1 SOC should replace the older A0 version. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-3-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 84 ----------------------------------------- 1 file changed, 84 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 70be3871bb12..6d6ffe31272c 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -100,56 +100,6 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { #define AST2700_MAX_IRQ 256 =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ -static const int aspeed_soc_ast2700a0_irqmap[] =3D { - [ASPEED_DEV_SDMC] =3D 0, - [ASPEED_DEV_HACE] =3D 4, - [ASPEED_DEV_XDMA] =3D 5, - [ASPEED_DEV_UART4] =3D 8, - [ASPEED_DEV_SCU] =3D 12, - [ASPEED_DEV_RTC] =3D 13, - [ASPEED_DEV_EMMC] =3D 15, - [ASPEED_DEV_TIMER1] =3D 16, - [ASPEED_DEV_TIMER2] =3D 17, - [ASPEED_DEV_TIMER3] =3D 18, - [ASPEED_DEV_TIMER4] =3D 19, - [ASPEED_DEV_TIMER5] =3D 20, - [ASPEED_DEV_TIMER6] =3D 21, - [ASPEED_DEV_TIMER7] =3D 22, - [ASPEED_DEV_TIMER8] =3D 23, - [ASPEED_DEV_DP] =3D 28, - [ASPEED_DEV_EHCI1] =3D 33, - [ASPEED_DEV_EHCI2] =3D 37, - [ASPEED_DEV_LPC] =3D 128, - [ASPEED_DEV_IBT] =3D 128, - [ASPEED_DEV_KCS] =3D 128, - [ASPEED_DEV_ADC] =3D 130, - [ASPEED_DEV_GPIO] =3D 130, - [ASPEED_DEV_SGPIOM0] =3D 130, - [ASPEED_DEV_SGPIOM1] =3D 130, - [ASPEED_DEV_I2C] =3D 130, - [ASPEED_DEV_FMC] =3D 131, - [ASPEED_DEV_WDT] =3D 131, - [ASPEED_DEV_PWM] =3D 131, - [ASPEED_DEV_I3C] =3D 131, - [ASPEED_DEV_UART0] =3D 132, - [ASPEED_DEV_UART1] =3D 132, - [ASPEED_DEV_UART2] =3D 132, - [ASPEED_DEV_UART3] =3D 132, - [ASPEED_DEV_UART5] =3D 132, - [ASPEED_DEV_UART6] =3D 132, - [ASPEED_DEV_UART7] =3D 132, - [ASPEED_DEV_UART8] =3D 132, - [ASPEED_DEV_UART9] =3D 132, - [ASPEED_DEV_UART10] =3D 132, - [ASPEED_DEV_UART11] =3D 132, - [ASPEED_DEV_UART12] =3D 132, - [ASPEED_DEV_ETH1] =3D 132, - [ASPEED_DEV_ETH2] =3D 132, - [ASPEED_DEV_ETH3] =3D 132, - [ASPEED_DEV_PECI] =3D 133, - [ASPEED_DEV_SDHCI] =3D 133, -}; - static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_SDMC] =3D 0, [ASPEED_DEV_HACE] =3D 4, @@ -1069,35 +1019,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) AST2700_SOC_IOMEM_SIZE); } =20 -static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *d= ata) -{ - static const char * const valid_cpu_types[] =3D { - ARM_CPU_TYPE_NAME("cortex-a35"), - NULL - }; - DeviceClass *dc =3D DEVICE_CLASS(oc); - AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); - - /* Reason: The Aspeed SoC can only be instantiated from a board */ - dc->user_creatable =3D false; - dc->realize =3D aspeed_soc_ast2700_realize; - - sc->valid_cpu_types =3D valid_cpu_types; - sc->silicon_rev =3D AST2700_A0_SILICON_REV; - sc->sram_size =3D 0x20000; - sc->pcie_num =3D 0; - sc->spis_num =3D 3; - sc->sgpio_num =3D 2; - sc->ehcis_num =3D 2; - sc->wdts_num =3D 8; - sc->macs_num =3D 1; - sc->uarts_num =3D 13; - sc->num_cpus =3D 4; - sc->uarts_base =3D ASPEED_DEV_UART0; - sc->irqmap =3D aspeed_soc_ast2700a0_irqmap; - sc->memmap =3D aspeed_soc_ast2700_memmap; -} - static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *d= ata) { static const char * const valid_cpu_types[] =3D { @@ -1133,11 +1054,6 @@ static const TypeInfo aspeed_soc_ast27x0_types[] =3D= { .parent =3D TYPE_ASPEED_SOC, .instance_size =3D sizeof(Aspeed27x0SoCState), .abstract =3D true, - }, { - .name =3D "ast2700-a0", - .parent =3D TYPE_ASPEED27X0_SOC, - .instance_init =3D aspeed_soc_ast2700_init, - .class_init =3D aspeed_soc_ast2700a0_class_init, }, { .name =3D "ast2700-a1", --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767635153; cv=none; d=zohomail.com; s=zohoarc; b=j/Y8DrDg6NnzGmWG4/xoqGR3T8PU9aFTmN7RWLO4iYfJ4kA55cmlLIq0BNAThnw4gPYsHEnDesAnWjZsI9GQKc5GQDmDAjevvKgtCamtq6tZfZZjY9BlI9IdOsHoBwEEuvhcjqHR2cEkeO+WaxNutf99OEW5P/rTI5tkx6GJOzA= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767635155748158500 From: Jamin Lin The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC. Since the AST2700 A0 has been deprecated, these interrupt definitions are no longer needed. This commit removes them to clean up the codebase. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-4-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 47 +++++++++---------------------------- hw/intc/aspeed_intc.c | 51 ++--------------------------------------- 2 files changed, 13 insertions(+), 85 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6d6ffe31272c..d17f44666112 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -153,20 +153,17 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_SDHCI] =3D 197, }; =20 -/* GICINT 128 */ /* GICINT 192 */ -static const int ast2700_gic128_gic192_intcmap[] =3D { +static const int ast2700_gic192_intcmap[] =3D { [ASPEED_DEV_LPC] =3D 0, [ASPEED_DEV_IBT] =3D 2, [ASPEED_DEV_KCS] =3D 4, }; =20 -/* GICINT 129 */ /* GICINT 193 */ =20 -/* GICINT 130 */ /* GICINT 194 */ -static const int ast2700_gic130_gic194_intcmap[] =3D { +static const int ast2700_gic194_intcmap[] =3D { [ASPEED_DEV_I2C] =3D 0, [ASPEED_DEV_ADC] =3D 16, [ASPEED_DEV_GPIO] =3D 18, @@ -174,18 +171,16 @@ static const int ast2700_gic130_gic194_intcmap[] =3D { [ASPEED_DEV_SGPIOM1] =3D 24, }; =20 -/* GICINT 131 */ /* GICINT 195 */ -static const int ast2700_gic131_gic195_intcmap[] =3D { +static const int ast2700_gic195_intcmap[] =3D { [ASPEED_DEV_I3C] =3D 0, [ASPEED_DEV_WDT] =3D 16, [ASPEED_DEV_FMC] =3D 25, [ASPEED_DEV_PWM] =3D 29, }; =20 -/* GICINT 132 */ /* GICINT 196 */ -static const int ast2700_gic132_gic196_intcmap[] =3D { +static const int ast2700_gic196_intcmap[] =3D { [ASPEED_DEV_ETH1] =3D 0, [ASPEED_DEV_ETH2] =3D 1, [ASPEED_DEV_ETH3] =3D 2, @@ -206,14 +201,12 @@ static const int ast2700_gic132_gic196_intcmap[] =3D { [ASPEED_DEV_PCIE2] =3D 31, }; =20 -/* GICINT 133 */ /* GICINT 197 */ -static const int ast2700_gic133_gic197_intcmap[] =3D { +static const int ast2700_gic197_intcmap[] =3D { [ASPEED_DEV_SDHCI] =3D 1, [ASPEED_DEV_PECI] =3D 4, }; =20 -/* GICINT 128 ~ 136 */ /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { int irq; @@ -223,25 +216,16 @@ struct gic_intc_irq_info { }; =20 static const struct gic_intc_irq_info ast2700_gic_intcmap[] =3D { - {192, 1, 0, ast2700_gic128_gic192_intcmap}, + {192, 1, 0, ast2700_gic192_intcmap}, {193, 1, 1, NULL}, - {194, 1, 2, ast2700_gic130_gic194_intcmap}, - {195, 1, 3, ast2700_gic131_gic195_intcmap}, - {196, 1, 4, ast2700_gic132_gic196_intcmap}, - {197, 1, 5, ast2700_gic133_gic197_intcmap}, + {194, 1, 2, ast2700_gic194_intcmap}, + {195, 1, 3, ast2700_gic195_intcmap}, + {196, 1, 4, ast2700_gic196_intcmap}, + {197, 1, 5, ast2700_gic197_intcmap}, {198, 1, 6, NULL}, {199, 1, 7, NULL}, {200, 1, 8, NULL}, {201, 1, 9, NULL}, - {128, 0, 1, ast2700_gic128_gic192_intcmap}, - {129, 0, 2, NULL}, - {130, 0, 3, ast2700_gic130_gic194_intcmap}, - {131, 0, 4, ast2700_gic131_gic195_intcmap}, - {132, 0, 5, ast2700_gic132_gic196_intcmap}, - {133, 0, 6, ast2700_gic133_gic197_intcmap}, - {134, 0, 7, NULL}, - {135, 0, 8, NULL}, - {136, 0, 9, NULL}, }; =20 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) @@ -285,8 +269,7 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(Aspeed= SoCState *s, int dev, } =20 /* - * Invalid OR gate index, device IRQ should be between 128 to 136 - * and 192 to 201. + * Invalid OR gate index, device IRQ should be between 192 to 201. */ g_assert_not_reached(); } @@ -701,7 +684,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) } =20 /* INTC -> GIC192 - GIC201 */ - /* INTC -> GIC128 - GIC136 */ for (i =3D 0; i < ic->num_outpins; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, qdev_get_gpio_in(DEVICE(&a->gic), @@ -901,13 +883,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) /* * The AST2700 I2C controller has one source INTC per bus. * - * For AST2700 A0: - * I2C bus interrupts are connected to the OR gate from bit 0 to b= it - * 15, and the OR gate output pin is connected to the input pin of - * GICINT130 of INTC (CPU Die). Then, the output pin is connected = to - * the GIC. - * - * For AST2700 A1: * I2C bus interrupts are connected to the OR gate from bit 0 to b= it * 15, and the OR gate output pin is connected to the input pin of * GICINT194 of INTCIO (IO Die). Then, the output pin is connected diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index f14c340b602f..ad95d76543f3 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -21,24 +21,6 @@ * because its memory region is start at 0x1000 * */ -REG32(GICINT128_EN, 0x000) -REG32(GICINT128_STATUS, 0x004) -REG32(GICINT129_EN, 0x100) -REG32(GICINT129_STATUS, 0x104) -REG32(GICINT130_EN, 0x200) -REG32(GICINT130_STATUS, 0x204) -REG32(GICINT131_EN, 0x300) -REG32(GICINT131_STATUS, 0x304) -REG32(GICINT132_EN, 0x400) -REG32(GICINT132_STATUS, 0x404) -REG32(GICINT133_EN, 0x500) -REG32(GICINT133_STATUS, 0x504) -REG32(GICINT134_EN, 0x600) -REG32(GICINT134_STATUS, 0x604) -REG32(GICINT135_EN, 0x700) -REG32(GICINT135_STATUS, 0x704) -REG32(GICINT136_EN, 0x800) -REG32(GICINT136_STATUS, 0x804) REG32(GICINT192_201_EN, 0xB00) REG32(GICINT192_201_STATUS, 0xB04) =20 @@ -507,29 +489,9 @@ static void aspeed_intc_write(void *opaque, hwaddr off= set, uint64_t data, trace_aspeed_intc_write(name, offset, size, data); =20 switch (reg) { - case R_GICINT128_EN: - case R_GICINT129_EN: - case R_GICINT130_EN: - case R_GICINT131_EN: - case R_GICINT132_EN: - case R_GICINT133_EN: - case R_GICINT134_EN: - case R_GICINT135_EN: - case R_GICINT136_EN: case R_GICINT192_201_EN: aspeed_intc_enable_handler(s, offset, data); break; - case R_GICINT128_STATUS: - case R_GICINT129_STATUS: - case R_GICINT130_STATUS: - case R_GICINT131_STATUS: - case R_GICINT132_STATUS: - case R_GICINT133_STATUS: - case R_GICINT134_STATUS: - case R_GICINT135_STATUS: - case R_GICINT136_STATUS: - aspeed_intc_status_handler(s, offset, data); - break; case R_GICINT192_201_STATUS: aspeed_intc_status_handler_multi_outpins(s, offset, data); break; @@ -891,15 +853,6 @@ static const TypeInfo aspeed_intc_info =3D { =20 static AspeedINTCIRQ aspeed_2700_intc_irqs[ASPEED_INTC_MAX_INPINS] =3D { {0, 0, 10, R_GICINT192_201_EN, R_GICINT192_201_STATUS}, - {1, 10, 1, R_GICINT128_EN, R_GICINT128_STATUS}, - {2, 11, 1, R_GICINT129_EN, R_GICINT129_STATUS}, - {3, 12, 1, R_GICINT130_EN, R_GICINT130_STATUS}, - {4, 13, 1, R_GICINT131_EN, R_GICINT131_STATUS}, - {5, 14, 1, R_GICINT132_EN, R_GICINT132_STATUS}, - {6, 15, 1, R_GICINT133_EN, R_GICINT133_STATUS}, - {7, 16, 1, R_GICINT134_EN, R_GICINT134_STATUS}, - {8, 17, 1, R_GICINT135_EN, R_GICINT135_STATUS}, - {9, 18, 1, R_GICINT136_EN, R_GICINT136_STATUS}, }; =20 static void aspeed_2700_intc_class_init(ObjectClass *klass, const void *da= ta) @@ -909,8 +862,8 @@ static void aspeed_2700_intc_class_init(ObjectClass *kl= ass, const void *data) =20 dc->desc =3D "ASPEED 2700 INTC Controller"; aic->num_lines =3D 32; - aic->num_inpins =3D 10; - aic->num_outpins =3D 19; + aic->num_inpins =3D 1; + aic->num_outpins =3D 10; aic->mem_size =3D 0x4000; aic->nr_regs =3D 0xB08 >> 2; aic->reg_offset =3D 0x1000; --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767646436; cv=none; d=zohomail.com; s=zohoarc; b=KLNDHLAwh6ds4V8TMLqGJEBrnzJm7372gcp/Z+4YwxQbgr66uVtIl353lwi7SvNc0a136MXCuUlcrSt6chlQlxhLwOwu+dcGiTdUcqCHJRH5dGYIEav78m1JEw/hJPcNJHPimPzKBnpQJyc+DCM4QyBzQElI8luu2m+AsgOXhQY= ARC-Message-Signature: i=1; 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Mon, 5 Jan 2026 12:57:25 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 4C77619560A7; Mon, 5 Jan 2026 12:57:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617848; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Z7PnNdkMr7GqJLMntFWlItt1vMRaPIoDbRubisjevB4=; b=jECL6h7EW58y0PbYuwa1u+cDTmE14Szn/FE15Njqq7QXSrRnKe214FUzLwkRtlfrc/LiC4 k+0GdAW/AZRkun1U1wkJJklvxddgzFhjabJlcNAmFGEamgHjOF46UgBRL+hCgboXTGZxY0 YQ/2M+5pfVbgAFuteCeVtK2mMCsYRks= X-MC-Unique: uuIHRbMkMrGZ0TDMv0ZgFg-1 X-Mimecast-MFC-AGG-ID: uuIHRbMkMrGZ0TDMv0ZgFg_1767617845 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 33/36] docs/specs/aspeed-intc: Remove GIC 128 - 136 Date: Mon, 5 Jan 2026 13:56:10 +0100 Message-ID: <20260105125613.622667-34-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767646437652158500 From: Jamin Lin The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC. Since the AST2700 A0 has been deprecated, these interrupt definitions are no longer needed. This commit removes them to clean up the codebase. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250901040808.1454742-5-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- docs/specs/aspeed-intc.rst | 92 +++++++++++--------------------------- 1 file changed, 25 insertions(+), 67 deletions(-) diff --git a/docs/specs/aspeed-intc.rst b/docs/specs/aspeed-intc.rst index 9cefd7f37f85..892a74a0c357 100644 --- a/docs/specs/aspeed-intc.rst +++ b/docs/specs/aspeed-intc.rst @@ -47,18 +47,7 @@ Bit GIC 9 201 =3D=3D=3D=3D =3D=3D=3D=3D =20 -AST2700 A0 ----------- -It has only one INTC controller, and currently, only GIC 128-136 is suppor= ted. -To support both AST2700 A1 and AST2700 A0, there are 10 OR gates in the IN= TC, -with gates 1 to 9 supporting GIC 128-136. - -Design for GICINT 132 ---------------------- -The orgate has interrupt sources ranging from 0 to 31, with its output pin -connected to INTC. The output pin is then connected to GIC 132. - -Block Diagram of GICINT 196 for AST2700 A1 and GICINT 132 for AST2700 A0 +Block Diagram of GICINT 196 for AST2700 A1 ------------------------------------------------------------------------ =20 .. code-block:: @@ -68,69 +57,38 @@ Block Diagram of GICINT 196 for AST2700 A1 and GICINT 1= 32 for AST2700 A0 | To GICINT196 = | | = | | ETH1 |-----------| |-------------------------= -| |--------------| | - | -------->|0 | | INTCIO = | | orgates[0] | | + | ------->|0 | | INTCIO = | | orgates[0] | | | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0= ]|------->| 0 | | - | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1= ]|------->| 1 | | + | ------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1= ]|------->| 1 | | | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2= ]|------->| 2 | | - | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3= ]|------->| 3 OR[0:9] |-----| | + | ------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3= ]|------->| 3 OR[0:9] |-----| | | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4= ]|------->| 4 | | | - | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5= ]|------->| 5 | | | + | ------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5= ]|------->| 5 | | | | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6= ]|------->| 6 | | | - | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7= ]|------->| 7 | | | + | ------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7= ]|------->| 7 | | | | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8= ]|------->| 8 | | | - | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9= ]|------->| 9 | | | + | ------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9= ]|------->| 9 | | | | UART3 | 26| |-------------------------= -| |--------------| | | - | ---------|10 27| = | | + | ------->|10 27| = | | | UART5 | 28| = | | - | -------->|11 29| = | | + | ------->|11 29| = | | | UART6 | | = | | - | -------->|12 30| |----------------------------------------= -------------------------------| | + | ------->|12 30| |----------------------------------------= -------------------------------| | | UART7 | 31| | = | - | -------->|13 | | = | - | UART8 | OR[0:31] | | |-----------------------= -------| |----------| | - | -------->|14 | | | INTC = | | GIC | | - | UART9 | | | |inpin[0:0]--------->out= pin[0] |---------->|192 | | - | -------->|15 | | |inpin[0:1]--------->out= pin[1] |---------->|193 | | - | UART10 | | | |inpin[0:2]--------->out= pin[2] |---------->|194 | | - | -------->|16 | | |inpin[0:3]--------->out= pin[3] |---------->|195 | | - | UART11 | | |--------------> |inpin[0:4]--------->out= pin[4] |---------->|196 | | - | -------->|17 | |inpin[0:5]--------->out= pin[5] |---------->|197 | | - | UART12 | | |inpin[0:6]--------->out= pin[6] |---------->|198 | | - | -------->|18 | |inpin[0:7]--------->out= pin[7] |---------->|199 | | - | |-----------| |inpin[0:8]--------->out= pin[8] |---------->|200 | | - | |inpin[0:9]--------->out= pin[9] |---------->|201 | | - |----------------------------------------------------------------------= ---------------------------------| - |----------------------------------------------------------------------= ---------------------------------| - | ETH1 |-----------| orgates[1]------->|inpin[1]----------->out= pin[10]|---------->|128 | | - | -------->|0 | orgates[2]------->|inpin[2]----------->out= pin[11]|---------->|129 | | - | ETH2 | 4| orgates[3]------->|inpin[3]----------->out= pin[12]|---------->|130 | | - | -------->|1 5| orgates[4]------->|inpin[4]----------->out= pin[13]|---------->|131 | | - | ETH3 | 6|---->orgates[5]------->|inpin[5]----------->out= pin[14]|---------->|132 | | - | -------->|2 19| orgates[6]------->|inpin[6]----------->out= pin[15]|---------->|133 | | - | UART0 | 20| orgates[7]------->|inpin[7]----------->out= pin[16]|---------->|134 | | - | -------->|7 21| orgates[8]------->|inpin[8]----------->out= pin[17]|---------->|135 | | - | UART1 | 22| orgates[9]------->|inpin[9]----------->out= pin[18]|---------->|136 | | - | -------->|8 23| |-----------------------= -------| |----------| | - | UART2 | 24| = | - | -------->|9 25| AST2700 A0 Design = | - | UART3 | 26| = | - | -------->|10 27| = | - | UART5 | 28| = | - | -------->|11 29| GICINT132 = | - | UART6 | | = | - | -------->|12 30| = | - | UART7 | 31| = | - | -------->|13 | = | - | UART8 | OR[0:31] | = | - | -------->|14 | = | - | UART9 | | = | - | -------->|15 | = | - | UART10 | | = | - | -------->|16 | = | - | UART11 | | = | - | -------->|17 | = | - | UART12 | | = | - | -------->|18 | = | - | |-----------| = | + | ------->|13 | | = | + | UART8 | OR[0:31] | | |-----------------------= ------| |----------| | + | ------->|14 | | | INTC = | | GIC | | + | UART9 | | | |inpin[0:0]--------->out= pin[0]|--------->|192 | | + | ------->|15 | | |inpin[0:1]--------->out= pin[1]|--------->|193 | | + | UART10 | | | |inpin[0:2]--------->out= pin[2]|--------->|194 | | + | ------->|16 | | |inpin[0:3]--------->out= pin[3]|--------->|195 | | + | UART11 | | |--------------> |inpin[0:4]--------->out= pin[4]|--------->|196 | | + | ------->|17 | |inpin[0:5]--------->out= pin[5]|--------->|197 | | + | UART12 | | |inpin[0:6]--------->out= pin[6]|--------->|198 | | + | ------->|18 | |inpin[0:7]--------->out= pin[7]|--------->|199 | | + | |-----------| |inpin[0:8]--------->out= pin[8]|--------->|200 | | + | |inpin[0:9]--------->out= pin[9]|--------->|201 | | + | |-----------------------= ------| |----------| | + | = | | = | |----------------------------------------------------------------------= ---------------------------------| --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617850; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BA3dxywMHeGUNlWZ2F4hoO7u7Gjqb4ptsqFeYGCOu54=; b=AYUj6G0MDgr/4/ky8qjuqhRnw8tpGUwbF22+UqmEdyprXRDgRGm1IYLnmXfydA9FGxqyiW wHkAtIpu729pCp0Bf9dODv9n7DLOczuHN4rF1zINaHeBRdLkeJYO+Pk6GonZbvZW4GcbVo K6ZLHWzuhVC2SDS3gWsJMlie2OSh/QA= X-MC-Unique: yA46j9crMyWU-GP6cLdWSw-1 X-Mimecast-MFC-AGG-ID: yA46j9crMyWU-GP6cLdWSw_1767617847 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 34/36] hw/intc/aspeed: Remove SSP 128 - 138 Date: Mon, 5 Jan 2026 13:56:11 +0100 Message-ID: <20260105125613.622667-35-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767621585020154100 From: Jamin Lin The SSP interrupts 128 - 138 were only used by the AST2700 A0 SoC. Since the AST2700 A0 has been deprecated, these interrupt definitions are no longer needed. This commit removes them to clean up the codebase. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20260102090746.1130033-2-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0-ssp.c | 13 ++------- hw/intc/aspeed_intc.c | 55 ++----------------------------------- 2 files changed, 4 insertions(+), 64 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 04d37056596a..cee937b37e9b 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -62,7 +62,7 @@ static const int aspeed_soc_ast27x0ssp_irqmap[] =3D { }; =20 /* SSPINT 164 */ -static const int ast2700_ssp132_ssp164_intcmap[] =3D { +static const int ast2700_ssp164_intcmap[] =3D { [ASPEED_DEV_UART0] =3D 7, [ASPEED_DEV_UART1] =3D 8, [ASPEED_DEV_UART2] =3D 9, @@ -89,21 +89,12 @@ static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = =3D { {161, 1, 1, NULL}, {162, 1, 2, NULL}, {163, 1, 3, NULL}, - {164, 1, 4, ast2700_ssp132_ssp164_intcmap}, + {164, 1, 4, ast2700_ssp164_intcmap}, {165, 1, 5, NULL}, {166, 1, 6, NULL}, {167, 1, 7, NULL}, {168, 1, 8, NULL}, {169, 1, 9, NULL}, - {128, 0, 1, NULL}, - {129, 0, 2, NULL}, - {130, 0, 3, NULL}, - {131, 0, 4, NULL}, - {132, 0, 5, ast2700_ssp132_ssp164_intcmap}, - {133, 0, 6, NULL}, - {134, 0, 7, NULL}, - {135, 0, 8, NULL}, - {136, 0, 9, NULL}, }; =20 static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCoprocessorState *s, diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index ad95d76543f3..9542df1c952d 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -47,28 +47,6 @@ REG32(GICINT197_STATUS, 0x54) /* * SSP INTC Registers */ -REG32(SSPINT128_EN, 0x2000) -REG32(SSPINT128_STATUS, 0x2004) -REG32(SSPINT129_EN, 0x2100) -REG32(SSPINT129_STATUS, 0x2104) -REG32(SSPINT130_EN, 0x2200) -REG32(SSPINT130_STATUS, 0x2204) -REG32(SSPINT131_EN, 0x2300) -REG32(SSPINT131_STATUS, 0x2304) -REG32(SSPINT132_EN, 0x2400) -REG32(SSPINT132_STATUS, 0x2404) -REG32(SSPINT133_EN, 0x2500) -REG32(SSPINT133_STATUS, 0x2504) -REG32(SSPINT134_EN, 0x2600) -REG32(SSPINT134_STATUS, 0x2604) -REG32(SSPINT135_EN, 0x2700) -REG32(SSPINT135_STATUS, 0x2704) -REG32(SSPINT136_EN, 0x2800) -REG32(SSPINT136_STATUS, 0x2804) -REG32(SSPINT137_EN, 0x2900) -REG32(SSPINT137_STATUS, 0x2904) -REG32(SSPINT138_EN, 0x2A00) -REG32(SSPINT138_STATUS, 0x2A04) REG32(SSPINT160_169_EN, 0x2B00) REG32(SSPINT160_169_STATUS, 0x2B04) =20 @@ -511,29 +489,9 @@ static void aspeed_ssp_intc_write(void *opaque, hwaddr= offset, uint64_t data, trace_aspeed_intc_write(name, offset, size, data); =20 switch (reg) { - case R_SSPINT128_EN: - case R_SSPINT129_EN: - case R_SSPINT130_EN: - case R_SSPINT131_EN: - case R_SSPINT132_EN: - case R_SSPINT133_EN: - case R_SSPINT134_EN: - case R_SSPINT135_EN: - case R_SSPINT136_EN: case R_SSPINT160_169_EN: aspeed_intc_enable_handler(s, offset, data); break; - case R_SSPINT128_STATUS: - case R_SSPINT129_STATUS: - case R_SSPINT130_STATUS: - case R_SSPINT131_STATUS: - case R_SSPINT132_STATUS: - case R_SSPINT133_STATUS: - case R_SSPINT134_STATUS: - case R_SSPINT135_STATUS: - case R_SSPINT136_STATUS: - aspeed_intc_status_handler(s, offset, data); - break; case R_SSPINT160_169_STATUS: aspeed_intc_status_handler_multi_outpins(s, offset, data); break; @@ -911,15 +869,6 @@ static const TypeInfo aspeed_2700_intcio_info =3D { =20 static AspeedINTCIRQ aspeed_2700ssp_intc_irqs[ASPEED_INTC_MAX_INPINS] =3D { {0, 0, 10, R_SSPINT160_169_EN, R_SSPINT160_169_STATUS}, - {1, 10, 1, R_SSPINT128_EN, R_SSPINT128_STATUS}, - {2, 11, 1, R_SSPINT129_EN, R_SSPINT129_STATUS}, - {3, 12, 1, R_SSPINT130_EN, R_SSPINT130_STATUS}, - {4, 13, 1, R_SSPINT131_EN, R_SSPINT131_STATUS}, - {5, 14, 1, R_SSPINT132_EN, R_SSPINT132_STATUS}, - {6, 15, 1, R_SSPINT133_EN, R_SSPINT133_STATUS}, - {7, 16, 1, R_SSPINT134_EN, R_SSPINT134_STATUS}, - {8, 17, 1, R_SSPINT135_EN, R_SSPINT135_STATUS}, - {9, 18, 1, R_SSPINT136_EN, R_SSPINT136_STATUS}, }; =20 static void aspeed_2700ssp_intc_class_init(ObjectClass *klass, const void = *data) @@ -929,8 +878,8 @@ static void aspeed_2700ssp_intc_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "ASPEED 2700 SSP INTC Controller"; aic->num_lines =3D 32; - aic->num_inpins =3D 10; - aic->num_outpins =3D 19; + aic->num_inpins =3D 1; + aic->num_outpins =3D 10; aic->mem_size =3D 0x4000; aic->nr_regs =3D 0x2B08 >> 2; aic->reg_offset =3D 0x0; --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767620529; cv=none; d=zohomail.com; s=zohoarc; b=ZeVH3OjfDci5sh3DS8cAexcteEnsUtWWzXSpI6XUXjGtzVYrUkV6+ASEgppEe9rwULAN+FV7vk4UiY/+qMP0W5BOqAcAvCr6hZG9KGKv3kuXWj0oC4/QJ4xZcap/sPbjoYBMiU6qR27PsmaAtbQsceMp0zqU0P0AvnS66Af7GtE= ARC-Message-Signature: i=1; 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Mon, 5 Jan 2026 12:57:29 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 2C8DB19560A7; Mon, 5 Jan 2026 12:57:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617853; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=42yCFCdA4HubgLTfystsISSWBl4Hbmik8bU56AWH8tk=; b=J35AyAKCVT0gXJfV0B6WlXSt0+UMAXeT4mbli4gQG5EIE5+JNhoDG+e0QSeCC1maJdIKlt 5VvetGKZvbROYoJVdTawXL3N+qMlm4rRLza1hCx2ufahK3PgKDROm2nMZ/l0wISe0nF3pJ +zvCdwwUPh4x6pgcrwPBn6wmTZRwzjI= X-MC-Unique: _InV3dkGOLayliPE2wEEZg-1 X-Mimecast-MFC-AGG-ID: _InV3dkGOLayliPE2wEEZg_1767617849 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 35/36] hw/intc/aspeed: Remove TSP 128 - 138 Date: Mon, 5 Jan 2026 13:56:12 +0100 Message-ID: <20260105125613.622667-36-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620530681154100 From: Jamin Lin The SSP interrupts 128 - 138 were only used by the AST2700 A0 SoC. Since the AST2700 A0 has been deprecated, these interrupt definitions are no longer needed. This commit removes them to clean up the codebase. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20260102090746.1130033-3-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0-tsp.c | 13 ++------- hw/intc/aspeed_intc.c | 55 ++----------------------------------- 2 files changed, 4 insertions(+), 64 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index f40c70fea544..9c11c016ca4b 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -62,7 +62,7 @@ static const int aspeed_soc_ast27x0tsp_irqmap[] =3D { }; =20 /* TSPINT 164 */ -static const int ast2700_tsp132_tsp164_intcmap[] =3D { +static const int ast2700_tsp164_intcmap[] =3D { [ASPEED_DEV_UART0] =3D 7, [ASPEED_DEV_UART1] =3D 8, [ASPEED_DEV_UART2] =3D 9, @@ -89,21 +89,12 @@ static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = =3D { {161, 1, 1, NULL}, {162, 1, 2, NULL}, {163, 1, 3, NULL}, - {164, 1, 4, ast2700_tsp132_tsp164_intcmap}, + {164, 1, 4, ast2700_tsp164_intcmap}, {165, 1, 5, NULL}, {166, 1, 6, NULL}, {167, 1, 7, NULL}, {168, 1, 8, NULL}, {169, 1, 9, NULL}, - {128, 0, 1, NULL}, - {129, 0, 2, NULL}, - {130, 0, 3, NULL}, - {131, 0, 4, NULL}, - {132, 0, 5, ast2700_tsp132_tsp164_intcmap}, - {133, 0, 6, NULL}, - {134, 0, 7, NULL}, - {135, 0, 8, NULL}, - {136, 0, 9, NULL}, }; =20 static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCoprocessorState *s, diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 9542df1c952d..77fae3920584 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -69,28 +69,6 @@ REG32(SSPINT165_STATUS, 0x1D4) /* * TSP INTC Registers */ -REG32(TSPINT128_EN, 0x3000) -REG32(TSPINT128_STATUS, 0x3004) -REG32(TSPINT129_EN, 0x3100) -REG32(TSPINT129_STATUS, 0x3104) -REG32(TSPINT130_EN, 0x3200) -REG32(TSPINT130_STATUS, 0x3204) -REG32(TSPINT131_EN, 0x3300) -REG32(TSPINT131_STATUS, 0x3304) -REG32(TSPINT132_EN, 0x3400) -REG32(TSPINT132_STATUS, 0x3404) -REG32(TSPINT133_EN, 0x3500) -REG32(TSPINT133_STATUS, 0x3504) -REG32(TSPINT134_EN, 0x3600) -REG32(TSPINT134_STATUS, 0x3604) -REG32(TSPINT135_EN, 0x3700) -REG32(TSPINT135_STATUS, 0x3704) -REG32(TSPINT136_EN, 0x3800) -REG32(TSPINT136_STATUS, 0x3804) -REG32(TSPINT137_EN, 0x3900) -REG32(TSPINT137_STATUS, 0x3904) -REG32(TSPINT138_EN, 0x3A00) -REG32(TSPINT138_STATUS, 0x3A04) REG32(TSPINT160_169_EN, 0x3B00) REG32(TSPINT160_169_STATUS, 0x3B04) =20 @@ -511,29 +489,9 @@ static void aspeed_tsp_intc_write(void *opaque, hwaddr= offset, uint64_t data, trace_aspeed_intc_write(name, offset, size, data); =20 switch (reg) { - case R_TSPINT128_EN: - case R_TSPINT129_EN: - case R_TSPINT130_EN: - case R_TSPINT131_EN: - case R_TSPINT132_EN: - case R_TSPINT133_EN: - case R_TSPINT134_EN: - case R_TSPINT135_EN: - case R_TSPINT136_EN: case R_TSPINT160_169_EN: aspeed_intc_enable_handler(s, offset, data); break; - case R_TSPINT128_STATUS: - case R_TSPINT129_STATUS: - case R_TSPINT130_STATUS: - case R_TSPINT131_STATUS: - case R_TSPINT132_STATUS: - case R_TSPINT133_STATUS: - case R_TSPINT134_STATUS: - case R_TSPINT135_STATUS: - case R_TSPINT136_STATUS: - aspeed_intc_status_handler(s, offset, data); - break; case R_TSPINT160_169_STATUS: aspeed_intc_status_handler_multi_outpins(s, offset, data); break; @@ -929,15 +887,6 @@ static const TypeInfo aspeed_2700ssp_intcio_info =3D { =20 static AspeedINTCIRQ aspeed_2700tsp_intc_irqs[ASPEED_INTC_MAX_INPINS] =3D { {0, 0, 10, R_TSPINT160_169_EN, R_TSPINT160_169_STATUS}, - {1, 10, 1, R_TSPINT128_EN, R_TSPINT128_STATUS}, - {2, 11, 1, R_TSPINT129_EN, R_TSPINT129_STATUS}, - {3, 12, 1, R_TSPINT130_EN, R_TSPINT130_STATUS}, - {4, 13, 1, R_TSPINT131_EN, R_TSPINT131_STATUS}, - {5, 14, 1, R_TSPINT132_EN, R_TSPINT132_STATUS}, - {6, 15, 1, R_TSPINT133_EN, R_TSPINT133_STATUS}, - {7, 16, 1, R_TSPINT134_EN, R_TSPINT134_STATUS}, - {8, 17, 1, R_TSPINT135_EN, R_TSPINT135_STATUS}, - {9, 18, 1, R_TSPINT136_EN, R_TSPINT136_STATUS}, }; =20 static void aspeed_2700tsp_intc_class_init(ObjectClass *klass, const void = *data) @@ -947,8 +896,8 @@ static void aspeed_2700tsp_intc_class_init(ObjectClass = *klass, const void *data) =20 dc->desc =3D "ASPEED 2700 TSP INTC Controller"; aic->num_lines =3D 32; - aic->num_inpins =3D 10; - aic->num_outpins =3D 19; + aic->num_inpins =3D 1; + aic->num_outpins =3D 10; aic->mem_size =3D 0x4000; aic->nr_regs =3D 0x3B08 >> 2; aic->reg_offset =3D 0; --=20 2.52.0 From nobody Sun Feb 8 18:18:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1767620502; cv=none; d=zohomail.com; s=zohoarc; b=hr51ddo4PkYOG0df2AbaTlWSlCIS68KYPe+U9+3/y93kxxwTCh5CD8zRWiH39uDmxb9cKkr8V4TSbJu+5fGAfVpK0FQjOeU1ESdm383jSG1MdjWQoD9PaDP5337B2i/gH7p88aiY19TeF7KTubnflgwzvRnet5HuPKuj6dLoJlU= ARC-Message-Signature: i=1; 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Mon, 5 Jan 2026 12:57:32 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 3341819560A7; Mon, 5 Jan 2026 12:57:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1767617855; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kJamzIu5Cl83GuxCo518L71tooIf9xFruKQPqLcFGn4=; b=IX4cOWiOIVzWyEPEMgG+jD4jdnncSQ18o1b1UcHfXz6W57TcXK/Fyyxp6zG5QXw7Mn5wQp f/taJOCmeazW4at3XGpx2PEGm7RrIv5z3kqzRTnJYI8tSiZxT/+RBiUeZIyb51jIFbmUxG xm9uuIdKJdEnQcbk1whh7/fRRX6okj4= X-MC-Unique: S6rv44lDNZ2OVtk_wdFGwA-1 X-Mimecast-MFC-AGG-ID: S6rv44lDNZ2OVtk_wdFGwA_1767617853 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 36/36] hw/i2c/aspeed: Fix wrong I2CC_DMA_LEN when I2CM_DMA_TX/RX_ADDR set first Date: Mon, 5 Jan 2026 13:56:13 +0100 Message-ID: <20260105125613.622667-37-clg@redhat.com> In-Reply-To: <20260105125613.622667-1-clg@redhat.com> References: <20260105125613.622667-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1767620508454154100 From: Jamin Lin In the previous design, the I2C model would update I2CC_DMA_LEN (0x54) base= d on the value of I2CM_DMA_LEN (0x1C) when the firmware set either I2CM_DMA_TX_A= DDR (0x30) or I2CM_DMA_RX_ADDR (0x34). However, this only worked correctly if t= he firmware set I2CM_DMA_LEN before setting I2CM_DMA_TX_ADDR or I2CM_DMA_RX_AD= DR. If the firmware instead set I2CM_DMA_TX_ADDR or I2CM_DMA_RX_ADDR before set= ting I2CM_DMA_LEN, the value written to I2CC_DMA_LEN would be incorrect. To fix this issue, the model should be updated to set I2CC_DMA_LEN when the firmware writes to the I2CM_DMA_LEN register, rather than when it writes to= the I2CM_DMA_RX_ADDR and I2CM_DMA_TX_ADDR registers. Signed-off-by: Jamin Lin Fixes: ba2cccd64e90 ("aspeed: i2c: Add new mode support") Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20260102090746.1130033-4-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/i2c/aspeed_i2c.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index faf2160c0670..1b8ac561c33b 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -656,8 +656,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset, bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 0, 32, FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR)); - bus->regs[R_I2CC_DMA_LEN] =3D ARRAY_FIELD_EX32(bus->regs, I2CM_DMA= _LEN, - TX_BUF_LEN) + 1; break; case A_I2CM_DMA_RX_ADDR: bus->regs[R_I2CM_DMA_RX_ADDR] =3D FIELD_EX32(value, I2CM_DMA_RX_AD= DR, @@ -665,8 +663,6 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset, bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 0, 32, FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR)); - bus->regs[R_I2CC_DMA_LEN] =3D ARRAY_FIELD_EX32(bus->regs, I2CM_DMA= _LEN, - RX_BUF_LEN) + 1; break; case A_I2CM_DMA_LEN: w1t =3D FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) || @@ -679,10 +675,16 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bu= s, hwaddr offset, if (FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) { ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN, FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN)); + bus->regs[R_I2CC_DMA_LEN] =3D ARRAY_FIELD_EX32(bus->regs, + I2CM_DMA_LEN, + RX_BUF_LEN) + 1; } if (FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) { ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN, FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN)); + bus->regs[R_I2CC_DMA_LEN] =3D ARRAY_FIELD_EX32(bus->regs, + I2CM_DMA_LEN, + TX_BUF_LEN) + 1; } break; case A_I2CM_DMA_LEN_STS: --=20 2.52.0