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Mon, 05 Jan 2026 02:59:54 -0800 (PST) From: Kito Cheng To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, kito.cheng@gmail.com, Kito Cheng Subject: [PATCH 2/5] target/riscv: Add arch=help to list supported ISA extensions Date: Mon, 5 Jan 2026 18:59:37 +0800 Message-ID: <20260105105940.3567112-3-kito.cheng@sifive.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260105105940.3567112-1-kito.cheng@sifive.com> References: <20260105105940.3567112-1-kito.cheng@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=kito.cheng@sifive.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1767610817440154100 Content-Type: text/plain; charset="utf-8" --- docs/system/target-riscv.rst | 14 ++++- target/riscv/cpu.c | 69 +++++++++++++++++++++++ target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 7 ++- tests/functional/riscv32/test_cpu_arch.py | 12 ++++ tests/functional/riscv64/test_cpu_arch.py | 25 ++++++++ 6 files changed, 124 insertions(+), 4 deletions(-) diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 3ec53dbf9e5..9acc51fbc2b 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -90,8 +90,18 @@ Individual ISA extensions can be enabled or disabled usi= ng boolean properties:: The ``arch`` property ^^^^^^^^^^^^^^^^^^^^^ =20 -The ``arch`` property provides a convenient way to inspect the current ISA -configuration: +The ``arch`` property provides convenient ways to discover and inspect ISA +extensions: + +* ``arch=3Dhelp`` + + Print a list of all supported ISA extensions and exit:: + + $ qemu-system-riscv64 -M virt -cpu rv64,arch=3Dhelp + $ qemu-riscv64 -cpu rv64,arch=3Dhelp /bin/true + + This lists standard single-letter extensions (with descriptions), multi-= letter + extensions, vendor extensions, and experimental extensions. =20 * ``arch=3Ddump`` =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2886b7ebcdd..b1d8438cd14 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -896,6 +896,23 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu= , Error **errp) } #endif =20 +/* + * Helper function to print single-letter extensions for arch=3Dhelp. + */ +static void riscv_cpu_help_misa_exts(void) +{ + qemu_printf("Standard Extensions (single-letter):\n"); + + for (int i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + const char *name =3D riscv_get_misa_ext_name(bit); + const char *desc =3D riscv_get_misa_ext_description(bit); + + qemu_printf(" %-4s %s\n", name, desc); + } + qemu_printf("\n"); +} + static inline const char *riscv_ext_status_str(bool enabled) { return enabled ? "enabled" : "disabled"; @@ -965,6 +982,58 @@ static void riscv_cpu_dump_priv_implied_exts(RISCVCPU = *cpu) qemu_printf("\n"); } =20 +/* + * Helper function to print multi-letter extension names for arch=3Dhelp. + * Does not print section header. + */ +static void riscv_cpu_help_multiext_entries(const RISCVCPUMultiExtConfig *= exts) +{ + for (const RISCVCPUMultiExtConfig *prop =3D exts; + prop && prop->name; prop++) { + qemu_printf(" %s\n", prop->name); + } +} + +/* + * Helper function to print multi-letter extensions for arch=3Dhelp. + */ +static void riscv_cpu_help_multiext(const char *title, + const RISCVCPUMultiExtConfig *exts) +{ + qemu_printf("%s:\n", title); + + riscv_cpu_help_multiext_entries(exts); + qemu_printf("\n"); +} + +/* + * Print list of supported ISA extensions and exit. + * Called when arch=3Dhelp is specified. + */ +G_NORETURN void riscv_cpu_list_supported_extensions(void) +{ + qemu_printf("\n"); + qemu_printf("Supported RISC-V ISA Extensions\n"); + qemu_printf("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n\n"); + + riscv_cpu_help_misa_exts(); + + /* Print multi-letter standard extensions (including named features) */ + qemu_printf("Standard Extensions (multi-letter):\n"); + riscv_cpu_help_multiext_entries(riscv_cpu_extensions); + riscv_cpu_help_multiext_entries(riscv_cpu_named_features); + qemu_printf("\n"); + + riscv_cpu_help_multiext("Vendor Extensions", riscv_cpu_vendor_exts); + riscv_cpu_help_multiext("Experimental Extensions", + riscv_cpu_experimental_exts); + + qemu_printf("Use '-cpu ,=3Dtrue' to enable an extension.\n"); + qemu_printf("Use '-cpu ,arch=3Ddump' to show current configuratio= n.\n"); + + exit(0); +} + /* * Print detailed ISA configuration and exit. * Called when arch=3Ddump is specified. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 90b3e951053..5c08c2ca4d6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -986,4 +986,5 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32= _bit); extern const RISCVCSR th_csr_list[]; =20 const char *priv_spec_to_str(int priv_version); +G_NORETURN void riscv_cpu_list_supported_extensions(void); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f7187472cd2..c9600a52e1c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1567,9 +1567,11 @@ static void cpu_set_arch(Object *obj, Visitor *v, co= nst char *name, =20 if (g_strcmp0(value, "dump") =3D=3D 0) { cpu->cfg.arch_dump_requested =3D true; + } else if (g_strcmp0(value, "help") =3D=3D 0) { + riscv_cpu_list_supported_extensions(); } else { error_setg(errp, "unknown arch option '%s'. " - "Supported options: dump", value); + "Supported options: dump, help", value); } } =20 @@ -1579,7 +1581,8 @@ static void riscv_cpu_add_arch_property(Object *obj) NULL, cpu_set_arch, NULL, NULL); object_property_set_description(obj, "arch", - "ISA configuration string (write-only). Use 'dump' to print ISA co= nfig."); + "ISA configuration (write-only). " + "Use 'help' to list extensions, 'dump' to show current config."); } =20 /* diff --git a/tests/functional/riscv32/test_cpu_arch.py b/tests/functional/r= iscv32/test_cpu_arch.py index 7b2f87cad88..b2042f1e5d8 100644 --- a/tests/functional/riscv32/test_cpu_arch.py +++ b/tests/functional/riscv32/test_cpu_arch.py @@ -47,6 +47,18 @@ def test_arch_dump_shows_enabled_extensions(self): self.assertRegex(res.stdout, r'd\s+enabled') self.assertRegex(res.stdout, r'c\s+enabled') =20 + def test_arch_help(self): + """Test arch=3Dhelp prints list of supported extensions and exits"= "" + res =3D self.run_qemu('rv32,arch=3Dhelp') + + self.assertEqual(res.returncode, 0, + f"arch=3Dhelp should exit with 0, got {res.return= code}") + + # Check for expected output sections + self.assertIn('Supported RISC-V ISA Extensions', res.stdout) + self.assertIn('Standard Extensions (single-letter):', res.stdout) + self.assertIn('Standard Extensions (multi-letter):', res.stdout) + def test_arch_invalid_option(self): """Test invalid arch=3D option shows error with supported options"= "" res =3D self.run_qemu('rv32,arch=3Dinvalid') diff --git a/tests/functional/riscv64/test_cpu_arch.py b/tests/functional/r= iscv64/test_cpu_arch.py index b0af8991397..4ec807b7276 100644 --- a/tests/functional/riscv64/test_cpu_arch.py +++ b/tests/functional/riscv64/test_cpu_arch.py @@ -66,6 +66,31 @@ def test_arch_dump_position_independence(self): self.assertRegex(res1.stdout, r'v\s+enabled') self.assertRegex(res2.stdout, r'v\s+enabled') =20 + def test_arch_help(self): + """Test arch=3Dhelp prints list of supported extensions and exits"= "" + res =3D self.run_qemu('rv64,arch=3Dhelp') + + self.assertEqual(res.returncode, 0, + f"arch=3Dhelp should exit with 0, got {res.return= code}") + + # Check for expected output sections + self.assertIn('Supported RISC-V ISA Extensions', res.stdout) + self.assertIn('Standard Extensions (single-letter):', res.stdout) + self.assertIn('Standard Extensions (multi-letter):', res.stdout) + self.assertIn('Vendor Extensions:', res.stdout) + + def test_arch_help_shows_extensions(self): + """Test arch=3Dhelp lists common extensions""" + res =3D self.run_qemu('rv64,arch=3Dhelp') + + # Check single-letter extensions with descriptions + self.assertIn('Base integer instruction set', res.stdout) + self.assertIn('Vector operations', res.stdout) + + # Check multi-letter extensions are listed + self.assertIn('zba', res.stdout) + self.assertIn('zbb', res.stdout) + def test_arch_invalid_option(self): """Test invalid arch=3D option shows error with supported options"= "" res =3D self.run_qemu('rv64,arch=3Dinvalid') --=20 2.52.0