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a=openpgp-sha256; l=4086; i=fustini@kernel.org; h=from:subject:message-id; bh=DEQYQbjVSlboGU+BOdVfGwtVHZcRjAKo5oA3AsVDxuE=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTGGGsePTUjqY1v5sJL+5dkPOXvztixrmGVifE/5sUn1 n1VneS1u6OUhUGMi0FWTJFl04e8C0u8Qr8umP9iG8wcViaQIQxcnAIwkem3GBney0r4FXEd91s9 W4lVpCRs96dkvnV6UX0f9vv9+Mo7xWQWI8NmsaiQmPeTsqd1Je9pPqnYy/shdnJOb/K/Ve4Hp6z eoMgPAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.105.4.254; envelope-from=fustini@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1767650131559158500 From: Nicolas Pitre Define structs to represent the hardware capabilities of capacity and bandwidth controllers according to the RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI). Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Signed-off-by: Nicolas Pitre Reviewed-by: Daniel Henrique Barboza Signed-off-by: Drew Fustini --- MAINTAINERS | 7 +++++ include/hw/riscv/cbqri.h | 82 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 89 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cbae7c26f83e..9d1b2b411010 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -357,6 +357,13 @@ F: target/riscv/XVentanaCondOps.decode F: target/riscv/insn_trans/trans_xventanacondops.c.inc F: disas/riscv-xventana* =20 +RISC-V QoS (Ssqosid ext and CBQRI spec) +M: Nicolas Pitre +M: Drew Fustini +L: qemu-riscv@nongnu.org +S: Supported +F: include/hw/riscv/cbqri.h + RENESAS RX CPUs R: Yoshinori Sato S: Orphan diff --git a/include/hw/riscv/cbqri.h b/include/hw/riscv/cbqri.h new file mode 100644 index 000000000000..a07f1e3a2dde --- /dev/null +++ b/include/hw/riscv/cbqri.h @@ -0,0 +1,82 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 + * + * Copyright (c) 2023 BayLibre SAS + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_RISCV_CBQRI_H +#define HW_RISCV_CBQRI_H + +#include "qemu/typedefs.h" + +#define RISCV_CBQRI_VERSION_MAJOR 0 +#define RISCV_CBQRI_VERSION_MINOR 1 + +#define TYPE_RISCV_CBQRI_CC "riscv.cbqri.capacity" +#define TYPE_RISCV_CBQRI_BC "riscv.cbqri.bandwidth" + +/* Capacity Controller hardware capabilities */ +typedef struct RiscvCbqriCapacityCaps { + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t ncblks; + + bool supports_at_data:1; + bool supports_at_code:1; + + bool supports_alloc_op_config_limit:1; + bool supports_alloc_op_read_limit:1; + bool supports_alloc_op_flush_rcid:1; + + bool supports_mon_op_config_event:1; + bool supports_mon_op_read_counter:1; + + bool supports_mon_evt_id_none:1; + bool supports_mon_evt_id_occupancy:1; +} RiscvCbqriCapacityCaps; + +/* Bandwidth Controller hardware capabilities */ +typedef struct RiscvCbqriBandwidthCaps { + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t nbwblks; + uint16_t mrbwb; + + bool supports_at_data:1; + bool supports_at_code:1; + + bool supports_alloc_op_config_limit:1; + bool supports_alloc_op_read_limit:1; + + bool supports_mon_op_config_event:1; + bool supports_mon_op_read_counter:1; + + bool supports_mon_evt_id_none:1; + bool supports_mon_evt_id_rdwr_count:1; + bool supports_mon_evt_id_rdonly_count:1; + bool supports_mon_evt_id_wronly_count:1; +} RiscvCbqriBandwidthCaps; + +DeviceState *riscv_cbqri_cc_create(hwaddr addr, + const RiscvCbqriCapacityCaps *caps, + const char *target_name); +DeviceState *riscv_cbqri_bc_create(hwaddr addr, + const RiscvCbqriBandwidthCaps *caps, + const char *target_name); +#endif --=20 2.43.0