From nobody Thu Jan 8 13:46:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1767493823133945.7897922094018; Sat, 3 Jan 2026 18:30:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vcDry-0002vE-I2; Sat, 03 Jan 2026 21:29:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vcDrv-0002uj-Sx for qemu-devel@nongnu.org; Sat, 03 Jan 2026 21:29:23 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vcDrt-00072I-Fo for qemu-devel@nongnu.org; Sat, 03 Jan 2026 21:29:23 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxcfB40Flp+koFAA--.17012S3; Sun, 04 Jan 2026 10:29:12 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAxWcF30Flp4vULAA--.13603S2; Sun, 04 Jan 2026 10:29:12 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 2/4] target/loongarch: Add generic CPU model information Date: Sun, 4 Jan 2026 10:29:03 +0800 Message-Id: <20260104022905.2120787-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260104022905.2120787-1-maobibo@loongson.cn> References: <20260104022905.2120787-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAxWcF30Flp4vULAA--.13603S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767493825229154100 Content-Type: text/plain; charset="utf-8" On LoongArch system, CPU model name comes from IOCSR register LOONGARCH_IOCSR_VENDOR and LOONGARCH_IOCSR_CPUNAME. Its value can be initialized when CPU is created. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 6 ++++-- target/loongarch/cpu.c | 4 ++++ target/loongarch/cpu.h | 6 ++++++ 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 6efa15da47..4db0e8a981 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -635,7 +635,9 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(opaque); uint64_t ret =3D 0; int features; + CPULoongArchState *env; =20 + env =3D &LOONGARCH_CPU(first_cpu)->env; switch (addr) { case VERSION_REG: ret =3D 0x11ULL; @@ -650,10 +652,10 @@ static MemTxResult virt_iocsr_misc_read(void *opaque,= hwaddr addr, } break; case VENDOR_REG: - ret =3D 0x6e6f73676e6f6f4cULL; /* "Loongson" */ + ret =3D env->vendor_id; break; case CPUNAME_REG: - ret =3D 0x303030354133ULL; /* "3A5000" */ + ret =3D env->cpu_id; break; case MISC_FUNC_REG: if (kvm_irqchip_in_kernel()) { diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ead1dccd0b..dffe6f652f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -282,6 +282,8 @@ static void loongarch_la464_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA464); data =3D FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON); env->cpucfg[0] =3D data; + memccpy((void *)&env->vendor_id, CPU_VENDOR_LOONGSON, 0, 8); + memccpy((void *)&env->cpu_id, CPU_MODEL_3A5000, 0, 8); =20 data =3D 0; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 2); @@ -393,6 +395,8 @@ static void loongarch_la132_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA132); data =3D FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON); env->cpucfg[0] =3D data; + memccpy((void *)&env->vendor_id, CPU_VENDOR_LOONGSON, 0, 8); + memccpy((void *)&env->cpu_id, CPU_MODEL_1C101, 0, 8); =20 data =3D 0; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index a258b22141..a2613cecb7 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -301,6 +301,10 @@ typedef struct LoongArchBT { uint32_t ftop; } lbt_t; =20 +#define CPU_VENDOR_LOONGSON "Loongson" +#define CPU_MODEL_3A5000 "3A5000" +#define CPU_MODEL_1C101 "1C101" + typedef struct CPUArchState { uint64_t gpr[32]; uint64_t pc; @@ -312,6 +316,8 @@ typedef struct CPUArchState { =20 uint32_t cpucfg[21]; uint32_t pv_features; + uint64_t vendor_id; + uint64_t cpu_id; =20 /* LoongArch CSRs */ uint64_t CSR_CRMD; --=20 2.39.3