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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1767384873066158500 From: Taylor Simpson I noticed that analyze_packet is marking the implicit pred reads after marking all the writes. However, the semantics of the instrucion and packet are to do all the reads, then do the operation, then do all the writes. Here is the old code static void analyze_packet(DisasContext *ctx) { Packet *pkt =3D ctx->pkt; ctx->read_after_write =3D false; ctx->has_hvx_overlap =3D false; for (int i =3D 0; i < pkt->num_insns; i++) { Insn *insn =3D &pkt->insn[i]; ctx->insn =3D insn; if (opcode_analyze[insn->opcode]) { opcode_analyze[insn->opcode](ctx); } mark_implicit_reg_writes(ctx); mark_implicit_pred_writes(ctx); mark_implicit_pred_reads(ctx); } ctx->need_commit =3D need_commit(ctx); } Recall that opcode_analyze[insn->opcode](ctx) will mark all the explicit reads then all the explicit writes. To properly handle the semantics, we'll create two new functions mark_implicit_reads mark_implicit_writes Then we change gen_analyze_funcs.py to add a call to the former after all the explicit reads and a call to the latter after all the explicit_writes. The reason this is an RFC patch is I can't find any instructions where this distinction makes a difference in ctx->need_commit which determines if the packet commit can be short-circuited. However, this could change in the future if the architecture introduces an instruction with an implicit read of a register that is also written (either implicit or explicit). Then, anlayze_packet would detect a read-after-write, and the packet would not short-circuit. The execution would be correct, but the performance would not be optimal. Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Tested-by: Brian Cain Message-Id: <20250325021440.81386-1-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/translate.c | 18 +++++++++++++++--- target/hexagon/gen_analyze_funcs.py | 4 ++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index f3240953b5..3762faec4d 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -37,6 +37,10 @@ #include "exec/helper-info.c.inc" #undef HELPER_H =20 +/* Forward declarations referenced in analyze_funcs_generated.c.inc */ +static void mark_implicit_reads(DisasContext *ctx); +static void mark_implicit_writes(DisasContext *ctx); + #include "analyze_funcs_generated.c.inc" =20 typedef void (*AnalyzeInsn)(DisasContext *ctx); @@ -377,6 +381,17 @@ static void mark_implicit_pred_reads(DisasContext *ctx) mark_implicit_pred_read(ctx, A_IMPLICIT_READS_P3, 3); } =20 +static void mark_implicit_reads(DisasContext *ctx) +{ + mark_implicit_pred_reads(ctx); +} + +static void mark_implicit_writes(DisasContext *ctx) +{ + mark_implicit_reg_writes(ctx); + mark_implicit_pred_writes(ctx); +} + static void analyze_packet(DisasContext *ctx) { Packet *pkt =3D ctx->pkt; @@ -388,9 +403,6 @@ static void analyze_packet(DisasContext *ctx) if (opcode_analyze[insn->opcode]) { opcode_analyze[insn->opcode](ctx); } - mark_implicit_reg_writes(ctx); - mark_implicit_pred_writes(ctx); - mark_implicit_pred_reads(ctx); } =20 ctx->need_commit =3D need_commit(ctx); diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy= ze_funcs.py index 3ac7cc2cfe..fdefd5b4b3 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -67,6 +67,8 @@ def gen_analyze_func(f, tag, regs, imms): if reg.is_read(): reg.analyze_read(f, regno) =20 + f.write(" mark_implicit_reads(ctx);\n") + ## Analyze the register writes for regno, register in enumerate(regs): reg_type, reg_id =3D register @@ -74,6 +76,8 @@ def gen_analyze_func(f, tag, regs, imms): if reg.is_written(): reg.analyze_write(f, tag, regno) =20 + f.write(" mark_implicit_writes(ctx);\n") + f.write("}\n\n") =20 =20 --=20 2.34.1