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helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=46.105.63.100; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=6.mo575.mail-out.ovh.net X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= From: frederic.petrot--- via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767291449088158500 We had to check that mttcg was not used when executing QEMU with -cpu x-rv128 as a single 128-bit access was done as two distinct 64-bit accesses. Now that we use the 128-bit ld/st that access the data atomically, this check is no longer necessary. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot --- target/riscv/tcg/tcg-cpu.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 440626ddfa..15d39f9912 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Erro= r **errp) } =20 #ifndef CONFIG_USER_ONLY - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - - if (mcc->def->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled())= { - /* Missing 128-bit aligned atomics */ - error_setg(errp, - "128-bit RISC-V currently does not work with Multi " - "Threaded TCG. Please use: -accel tcg,thread=3Dsingle"); - return false; - } - CPURISCVState *env =3D &cpu->env; =20 tcg_cflags_set(CPU(cs), CF_PCREL); --=20 2.43.0