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Thu, 1 Jan 2026 18:15:15 +0000 (UTC) Received: from ghost-submission-7d8d68f679-kbmwb (unknown [10.110.164.150]) by director8.ghost.mail-out.ovh.net (Postfix) with ESMTPS id 42C57C02A2; Thu, 1 Jan 2026 18:15:15 +0000 (UTC) Received: from petrot.fr ([37.59.142.99]) by ghost-submission-7d8d68f679-kbmwb with ESMTPSA id QUyEM6q5Vmlo/w0A7Yva2g:T2 (envelope-from ); Thu, 01 Jan 2026 18:15:15 +0000 Authentication-Results: garm.ovh; auth=pass (GARM-99G00396cbf9ef-74af-4aa7-989c-49a740ff6e7a, 8D8ADDDE20E1118D614694FD1C3138A4D0B19743) smtp.auth=frederic@petrot.fr X-OVh-ClientIp: 79.90.201.35 To: philmd@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= , Richard Henderson Subject: [PATCH 1/2] trans_rvi.c.inc: Make lq and sq use 128-bit ld/st Date: Thu, 1 Jan 2026 19:14:41 +0100 Message-ID: <20260101181442.2489496-2-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260101181442.2489496-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20260101181442.2489496-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 Content-Type: text/plain; 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helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=188.165.51.82; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=14.mo583.mail-out.ovh.net X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= From: frederic.petrot--- via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767291471929158500 The lq and sq helpers for the experimental rv128 architecture currently use direct memory accesses. Replace these direct accesses with the standard tcg_gen_qemu_{ld,st}_i128 TCG helpers that handle endianness issues. Reported-by: Philippe Mathieu-Daud=C3=A9 Suggested-by: Richard Henderson Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot --- target/riscv/insn_trans/trans_rvi.c.inc | 32 ++++++++++++++++++------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 54b9b4f241..2c82ae41a7 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -377,6 +377,9 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a,= MemOp memop) TCGv destl =3D dest_gpr(ctx, a->rd); TCGv desth =3D dest_gprh(ctx, a->rd); TCGv addrl =3D tcg_temp_new(); + TCGv_i128 t16 =3D tcg_temp_new_i128(); + TCGv_i64 tl =3D tcg_temp_new_i64(); + TCGv_i64 th =3D tcg_temp_new_i64(); =20 tcg_gen_addi_tl(addrl, src1l, a->imm); =20 @@ -388,10 +391,14 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *= a, MemOp memop) tcg_gen_movi_tl(desth, 0); } } else { - /* assume little-endian memory access for now */ - tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ); - tcg_gen_addi_tl(addrl, addrl, 8); - tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i128(t16, addrl, ctx->mem_idx, memop); + if (mo_endian(ctx) =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(tl, th, t16); + } else { + tcg_gen_extr_i128_i64(th, tl, t16); + } + tcg_gen_trunc_i64_tl(destl, tl); + tcg_gen_trunc_i64_tl(desth, th); } =20 gen_set_gpr128(ctx, a->rd, destl, desth); @@ -488,16 +495,25 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb = *a, MemOp memop) TCGv src2l =3D get_gpr(ctx, a->rs2, EXT_NONE); TCGv src2h =3D get_gprh(ctx, a->rs2); TCGv addrl =3D tcg_temp_new(); + TCGv_i128 t16 =3D tcg_temp_new_i128(); + TCGv_i64 tl =3D tcg_temp_new_i64(); + TCGv_i64 th =3D tcg_temp_new_i64(); =20 tcg_gen_addi_tl(addrl, src1l, a->imm); =20 if ((memop & MO_SIZE) <=3D MO_64) { tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); } else { - /* little-endian memory access assumed for now */ - tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ); - tcg_gen_addi_tl(addrl, addrl, 8); - tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ); + + tcg_gen_ext_tl_i64(tl, src2l); + tcg_gen_ext_tl_i64(th, src2h); + + if (mo_endian(ctx) =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(t16, tl, th); + } else { + tcg_gen_concat_i64_i128(t16, th, tl); + } + tcg_gen_qemu_st_i128(t16, addrl, ctx->mem_idx, memop); } return true; } --=20 2.43.0 From nobody Wed Jan 7 09:28:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1767291447; cv=none; d=zohomail.com; s=zohoarc; b=e85HH3AjS3kFg3YH5byxQuU4OT7Lt1PFxdqheibYC83XRGpc2ivqvPN+7xeO0eyOsRZwQ2VXEAeBe/5j7zsNOOu+hDPYW1aHYTdglEL1gAzIO97pRhF08qzgZUNScp0ZFlKhDsT+aWEtV+FnLVjLqLFWUQet4J0ldcbG4q4unpk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=46.105.63.100; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=6.mo575.mail-out.ovh.net X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= From: frederic.petrot--- via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1767291449088158500 We had to check that mttcg was not used when executing QEMU with -cpu x-rv128 as a single 128-bit access was done as two distinct 64-bit accesses. Now that we use the 128-bit ld/st that access the data atomically, this check is no longer necessary. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot --- target/riscv/tcg/tcg-cpu.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 440626ddfa..15d39f9912 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Erro= r **errp) } =20 #ifndef CONFIG_USER_ONLY - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - - if (mcc->def->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled())= { - /* Missing 128-bit aligned atomics */ - error_setg(errp, - "128-bit RISC-V currently does not work with Multi " - "Threaded TCG. Please use: -accel tcg,thread=3Dsingle"); - return false; - } - CPURISCVState *env =3D &cpu->env; =20 tcg_cflags_set(CPU(cs), CF_PCREL); --=20 2.43.0