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charset="utf-8" From: Zhao Liu Current DiamondRapids hasn't supported cache model. Instead, document its special CPU & cache topology to allow user emulate with "-smp" & "-machine smp-cache". Reviewed-by: Yu Chen Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20251215073743.4055227-12-zhao1.liu@intel.c= om Signed-off-by: Paolo Bonzini --- docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x8= 6.rst.inc index 6a770ca8351..3605d05a8c4 100644 --- a/docs/system/cpu-models-x86.rst.inc +++ b/docs/system/cpu-models-x86.rst.inc @@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live mig= ration compatibility is required, use the newest CPU model that is compatible across all desired hosts. =20 +``DiamondRapids`` + Intel Xeon Processor. + + Diamond Rapids product has a topology which differs from previous Xeon + products. It does not support SMT, but instead features a dual core + module (DCM) architecture. It also has core building blocks (CBB - die + level in CPU topology). The cache hierarchy is organized as follows: + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per + CBB. This cache topology can be emulated for DiamondRapids CPU model + using the smp-cache configuration as shown below: + + Example: + + :: + + -machine smp-cache.0.cache=3Dl1d,smp-cache.0.topology=3Dthread= ,\ + smp-cache.1.cache=3Dl1i,smp-cache.1.topology=3Dthread= ,\ + smp-cache.2.cache=3Dl2,smp-cache.2.topology=3Dmodule,\ + smp-cache.3.cache=3Dl3,smp-cache.3.topology=3Ddie + ``ClearwaterForest`` Intel Xeon Processor (ClearwaterForest, 2025) =20 --=20 2.52.0