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Sat, 27 Dec 2025 01:51:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IF7wjzsEhSIGQLSNW6I+u469gOU38imzhpZCZV66zljLHR5KMwyyYupzchhBc77xoro4ccAoQ== X-Received: by 2002:a05:600c:828d:b0:477:73cc:82c2 with SMTP id 5b1f17b1804b1-47d1954a14dmr284074115e9.9.1766829097444; Sat, 27 Dec 2025 01:51:37 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Farrah Chen , Zide Chen , Xiaoyao Li , Xudong Hao Subject: [PULL 145/153] i386/cpu: Add CPU model for Diamond Rapids Date: Sat, 27 Dec 2025 10:47:50 +0100 Message-ID: <20251227094759.35658-71-pbonzini@redhat.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251227091622.20725-1-pbonzini@redhat.com> References: <20251227091622.20725-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Zhao Liu According to table 1-2 in Intel Architecture Instruction Set Extensions and Future Features (rev 059), Diamond Rapids has the following new features which have already been supported for guest: * SM4 (EVEX) * Intel Advanced Vector Extensions 10 Version 2 (Intel AVX10.2) * MOVRS and the PREFETCHRST2 instruction * AMX-MOVRS, AMX-AVX512, AMX-FP8, AMX-TF32 * Intel Advanced Performance Extensions And FRED - Flexible Return and Event Delivery (FRED) and the LKGS instruction (introduced since Clearwater Forest & Diamond Rapids) - is included in Diamond Rapids CPU model. In addition, the following features are added into Diamond Rapids CPU model: * CET: Control-flow Enforcement Technology (introduced since Sapphire Rapids & Sierra Forest). Tested-by: Xudong Hao Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20251215073743.4055227-11-zhao1.liu@intel.c= om Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 192 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3440a70852d..37803cd7249 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5443,6 +5443,198 @@ static const X86CPUDefinition builtin_x86_defs[] = =3D { { /* end of list */ }, }, }, + { + .name =3D "DiamondRapids", + .level =3D 0x29, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 0x13, /* family: 0xf, extended famil: 0x4 */ + .model =3D 0x1, /* model: 0x1, extended model: 0x0 */ + .stepping =3D 0, + .avx10_version =3D 2, /* avx10.2 */ + .cpuid_0x1f =3D true, + /* + * Please keep the ascending order so that we can have a clear vie= w of + * bit position of each feature. + * + * Missing: CPUID_EXT_DTES64, CPUID_EXT_MONITOR, CPUID_EXT_DSCPL, + * CPUID_EXT_VMX, CPUID_EXT_SMX, CPUID_EXT_EST, CPUID_EXT_TM2, + * CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_DCA, CPUID_EXT_OSXSAVE + */ + .features[FEAT_1_ECX] =3D + CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | + CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SS= E41 | + CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | + CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AE= S | + CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_R= DRAND, + /* Missing: CPUID_DTS, CPUID_ACPI, CPUID_HT, CPUID_TM, CPUID_PBE */ + .features[FEAT_1_EDX] =3D + CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | + CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | + CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | + CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FX= SR | + CPUID_SSE | CPUID_SSE2 | CPUID_SS, + .features[FEAT_6_EAX] =3D CPUID_6_EAX_ARAT, + /* + * Missing: CPUID_7_0_EBX_SGX, "cqm" Cache QoS Monitoring, + * "rdt_a" Resource Director Technology Allocation, + * CPUID_7_0_EBX_INTEL_PT, + */ + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | + CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | + CPUID_7_0_EBX_FDP_EXCPTN_ONLY | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_ZERO_FCS_FDS | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | + CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | + CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_AVX512BW | + CPUID_7_0_EBX_AVX512VL, + /* + * Missing: CPUID_7_0_ECX_OSPKE, CPUID_7_0_ECX_WAITPKG, TME, ENQCM= D, + * CPUID_7_0_ECX_SGX_LC, CPUID_7_0_ECX_PKS + */ + .features[FEAT_7_0_ECX] =3D + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | + CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_AVX512_VBMI2 | + CPUID_7_0_ECX_CET_SHSTK | CPUID_7_0_ECX_GFNI | CPUID_7_0_ECX_V= AES | + CPUID_7_0_ECX_VPCLMULQDQ | CPUID_7_0_ECX_AVX512VNNI | + CPUID_7_0_ECX_AVX512BITALG | CPUID_7_0_ECX_AVX512_VPOPCNTDQ | + CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_RDPID | + CPUID_7_0_ECX_BUS_LOCK_DETECT | CPUID_7_0_ECX_CLDEMOTE | + CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_MOVDIR64B, + /* + * Missing: SGX-KEYS, UINTR, PCONFIG, ARCH LBR, + * CPUID_7_0_EDX_CORE_CAPABILITY + */ + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_MD_CLEAR | + CPUID_7_0_EDX_SERIALIZE | CPUID_7_0_EDX_TSX_LDTRK | + CPUID_7_0_EDX_CET_IBT | CPUID_7_0_EDX_AMX_BF16 | + CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | + CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | + CPUID_7_0_EDX_STIBP | CPUID_7_0_EDX_FLUSH_L1D | + CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, + /* Missing: CPUID_7_1_EAX_LASS, ArchPerfmonExt (0x23 leaf), MSRLIS= T */ + .features[FEAT_7_1_EAX] =3D + CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | + CPUID_7_1_EAX_CMPCCXADD | CPUID_7_1_EAX_FZRM | + CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_FRED | + CPUID_7_1_EAX_LKGS | CPUID_7_1_EAX_WRMSRNS | + CPUID_7_1_EAX_AMX_FP16 | CPUID_7_1_EAX_AVX_IFMA | + CPUID_7_1_EAX_LAM | CPUID_7_1_EAX_MOVRS, + /* Missing: CET_SSS */ + .features[FEAT_7_1_EDX] =3D + CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | + CPUID_7_1_EDX_AMX_COMPLEX | CPUID_7_1_EDX_PREFETCHITI | + CPUID_7_1_EDX_AVX10 | CPUID_7_1_EDX_APXF, + /* Missing: UC-lock disable */ + .features[FEAT_7_2_EDX] =3D + CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | + CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | + CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, + .features[FEAT_1E_1_EAX] =3D + CPUID_1E_1_EAX_AMX_INT8_MIRROR | CPUID_1E_1_EAX_AMX_BF16_MIRRO= R | + CPUID_1E_1_EAX_AMX_COMPLEX_MIRROR | + CPUID_1E_1_EAX_AMX_FP16_MIRROR | CPUID_1E_1_EAX_AMX_FP8 | + CPUID_1E_1_EAX_AMX_TF32 | CPUID_1E_1_EAX_AMX_AVX512 | + CPUID_1E_1_EAX_AMX_MOVRS, + .features[FEAT_29_0_EBX] =3D CPUID_29_0_EBX_APX_NCI_NDD_NF, + /* + * Though this bit will be set by avx_version=3D2, it's better to + * explicitly enumerate this feature here. + */ + .features[FEAT_24_1_ECX] =3D CPUID_24_1_ECX_AVX10_VNNI_INT, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, + .features[FEAT_8000_0008_EBX] =3D CPUID_8000_0008_EBX_WBNOINVD, + /* + * Missing: ARCH_CAP_RRSBA (KVM bit 19), ARCH_CAP_RFDS_CLEAR (KVM = bit + * 28), MCU_CONTROL (bit 9), MISC_PACKAGE_CTLS (bit 10), + * ENERGY_FILTERING_CTL (bit 11), DOITM (bit 12), MCU_ENUMERATION = (bit + * 16), RRSBA (bit 19), XAPIC_DISABLE_STATUS (bit 21), + * OVERCLOCKING_STATUS (bit 23). + */ + .features[FEAT_ARCH_CAPABILITIES] =3D + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | + MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | + MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | + MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_BHI_NO | + MSR_ARCH_CAP_PBRSB_NO | MSR_ARCH_CAP_GDS_NO | + MSR_ARCH_CAP_RFDS_NO, + .features[FEAT_VMX_BASIC] =3D + MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS | + MSR_VMX_BASIC_NESTED_EXCEPTION, + .features[FEAT_VMX_ENTRY_CTLS] =3D + VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | + VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER | + VMX_VM_ENTRY_LOAD_CET | VMX_VM_ENTRY_LOAD_IA32_FRED, + .features[FEAT_VMX_EPT_VPID_CAPS] =3D + MSR_VMX_EPT_EXECONLY | + MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_= 5 | + MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | + MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | + MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CON= TEXT | + MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | + MSR_VMX_EPT_INVVPID_ALL_CONTEXT | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, + .features[FEAT_VMX_EXIT_CTLS] =3D + VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_= SIZE, + VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | + VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER | + VMX_VM_EXIT_SAVE_CET | VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS, + .features[FEAT_VMX_MISC] =3D + MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | + MSR_VMX_MISC_ACTIVITY_SHUTDOWN | MSR_VMX_MISC_ACTIVITY_WAIT_SI= PI | + MSR_VMX_MISC_VMWRITE_VMEXIT, + .features[FEAT_VMX_PINBASED_CTLS] =3D + VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | + VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIME= R | + VMX_PIN_BASED_POSTED_INTR, + .features[FEAT_VMX_PROCBASED_CTLS] =3D + VMX_CPU_BASED_VIRTUAL_INTR_PENDING | + VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | + VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | + VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | + VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITI= NG | + VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITI= NG | + VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | + VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING= | + VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG= | + VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | + VMX_CPU_BASED_PAUSE_EXITING | + VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, + .features[FEAT_VMX_SECONDARY_CTLS] =3D + VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | + VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | + VMX_SECONDARY_EXEC_RDTSCP | + VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | + VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXI= TING | + VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | + VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | + VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | + VMX_SECONDARY_EXEC_RDRAND_EXITING | + VMX_SECONDARY_EXEC_ENABLE_INVPCID | + VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_V= MCS | + VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_= PML | + VMX_SECONDARY_EXEC_XSAVES | VMX_SECONDARY_EXEC_TSC_SCALING | + VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE, + .features[FEAT_VMX_VMFUNC] =3D MSR_VMX_VMFUNC_EPT_SWITCHING, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Xeon Processor (DiamondRapids)", + }, { .name =3D "SierraForest", .level =3D 0x23, --=20 2.52.0