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charset="utf-8" From: Zhao Liu The x86_ext_save_areas[] is expected to be well initialized by accelerators and its xstate detail information cannot be changed by user. So use x86_ext_save_areas[] to encode CPUID.0XD subleaves directly without other hardcoding & masking. And for arch LBR, KVM fills its xstate in x86_ext_save_areas[] via host_cpuid(). The info obtained this way matches what would be retrieved from x86_cpu_get_supported_cpuid() (since KVM just fills CPUID with the host xstate info directly anyway). So just use the initialized x86_ext_save_areas[] instead of calling x86_cpu_get_supported_cpuid(). Tested-by: Farrah Chen Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20251211060801.3600039-7-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 812a2151471..f4c0ae533d0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8188,20 +8188,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } } else if (count =3D=3D 0xf && cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LB= R)) { - x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); + const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; + + *eax =3D esa->size; + *ebx =3D esa->offset; + *ecx =3D esa->ecx; } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; =20 - if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { - *eax =3D esa->size; - *ebx =3D esa->offset; - *ecx =3D esa->ecx & - (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); - } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)= ) { - *eax =3D esa->size; - *ebx =3D 0; - *ecx =3D 1; - } + *eax =3D esa->size; + *ebx =3D esa->offset; + *ecx =3D esa->ecx; } break; } --=20 2.52.0