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charset="utf-8" Do not separate visible and hidden state; both of them are used in the same circumstances and it's easiest to place both of them under the same BqlRefCell. Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- rust/hw/timer/hpet/src/device.rs | 151 +++++++++++++++---------------- 1 file changed, 71 insertions(+), 80 deletions(-) diff --git a/rust/hw/timer/hpet/src/device.rs b/rust/hw/timer/hpet/src/devi= ce.rs index 916ae587b08..005e41aec47 100644 --- a/rust/hw/timer/hpet/src/device.rs +++ b/rust/hw/timer/hpet/src/device.rs @@ -171,9 +171,9 @@ const fn deactivating_bit(old: u64, new: u64, shift: us= ize) -> bool { } =20 fn timer_handler(timer_cell: &BqlRefCell) { - let mut t =3D timer_cell.borrow_mut(); + let t =3D timer_cell.borrow(); // SFAETY: state field is valid after timer initialization. - let hpet_regs =3D &mut unsafe { t.state.as_mut() }.regs; + let hpet_regs =3D &unsafe { t.state.as_ref() }.regs; t.callback(&mut hpet_regs.borrow_mut()) } =20 @@ -187,9 +187,35 @@ pub struct HPETTimerRegisters { cmp: u64, /// Timer N FSB Interrupt Route Register fsb: u64, + + // Hidden register state + /// comparator (extended to counter width) + cmp64: u64, + /// Last value written to comparator + period: u64, + /// timer pop will indicate wrap for one-shot 32-bit + /// mode. Next pop will be actual timer expiration. + wrap_flag: u8, + /// last value armed, to avoid timer storms + last: u64, } =20 impl HPETTimerRegisters { + /// calculate next value of the general counter that matches the + /// target (either entirely, or the low 32-bit only depending on + /// the timer mode). + fn update_cmp64(&mut self, cur_tick: u64) { + self.cmp64 =3D if self.is_32bit_mod() { + let mut result: u64 =3D cur_tick.deposit(0, 32, self.cmp); + if result < cur_tick { + result +=3D 0x100000000; + } + result + } else { + self.cmp + } + } + const fn is_fsb_route_enabled(&self) -> bool { self.config & (1 << HPET_TN_CFG_FSB_ENABLE_SHIFT) !=3D 0 } @@ -234,17 +260,6 @@ pub struct HPETTimer { qemu_timer: Timer, /// timer block abstraction containing this timer state: NonNull, - - // Hidden register state - /// comparator (extended to counter width) - cmp64: u64, - /// Last value written to comparator - period: u64, - /// timer pop will indicate wrap for one-shot 32-bit - /// mode. Next pop will be actual timer expiration. - wrap_flag: u8, - /// last value armed, to avoid timer storms - last: u64, } =20 // SAFETY: Sync is not automatically derived due to the `state` field, @@ -259,10 +274,6 @@ fn new(index: u8, state: *const HPETState) -> HPETTime= r { // is initialized below. qemu_timer: unsafe { Timer::new() }, state: NonNull::new(state.cast_mut()).unwrap(), - cmp64: 0, - period: 0, - wrap_flag: 0, - last: 0, } } =20 @@ -284,22 +295,6 @@ fn is_int_active(&self, regs: &HPETRegisters) -> bool { regs.is_timer_int_active(self.index.into()) } =20 - /// calculate next value of the general counter that matches the - /// target (either entirely, or the low 32-bit only depending on - /// the timer mode). - fn calculate_cmp64(&self, regs: &HPETRegisters, cur_tick: u64, target:= u64) -> u64 { - let tn_regs =3D ®s.tn_regs[self.index as usize]; - if tn_regs.is_32bit_mod() { - let mut result: u64 =3D cur_tick.deposit(0, 32, target); - if result < cur_tick { - result +=3D 0x100000000; - } - result - } else { - target - } - } - fn get_int_route(&self, regs: &HPETRegisters) -> usize { if self.index <=3D 1 && regs.is_legacy_mode() { // If LegacyReplacement Route bit is set, HPET specification r= equires @@ -364,35 +359,34 @@ fn update_irq(&self, regs: &mut HPETRegisters, set: b= ool) { self.set_irq(regs, set); } =20 - fn arm_timer(&mut self, regs: &HPETRegisters, tick: u64) { - let tn_regs =3D ®s.tn_regs[self.index as usize]; + fn arm_timer(&self, tn_regs: &mut HPETTimerRegisters, tick: u64) { let mut ns =3D self.get_state().get_ns(tick); =20 // Clamp period to reasonable min value (1 us) - if tn_regs.is_periodic() && ns - self.last < 1000 { - ns =3D self.last + 1000; + if tn_regs.is_periodic() && ns - tn_regs.last < 1000 { + ns =3D tn_regs.last + 1000; } =20 - self.last =3D ns; - self.qemu_timer.modify(self.last); + tn_regs.last =3D ns; + self.qemu_timer.modify(tn_regs.last); } =20 - fn set_timer(&mut self, regs: &HPETRegisters) { - let tn_regs =3D ®s.tn_regs[self.index as usize]; + fn set_timer(&self, regs: &mut HPETRegisters) { + let tn_regs =3D &mut regs.tn_regs[self.index as usize]; let cur_tick: u64 =3D self.get_state().get_ticks(); =20 - self.wrap_flag =3D 0; - self.cmp64 =3D self.calculate_cmp64(regs, cur_tick, tn_regs.cmp); + tn_regs.wrap_flag =3D 0; + tn_regs.update_cmp64(cur_tick); if tn_regs.is_32bit_mod() { // HPET spec says in one-shot 32-bit mode, generate an interru= pt when // counter wraps in addition to an interrupt with comparator m= atch. - if !tn_regs.is_periodic() && self.cmp64 > hpet_next_wrap(cur_t= ick) { - self.wrap_flag =3D 1; - self.arm_timer(regs, hpet_next_wrap(cur_tick)); + if !tn_regs.is_periodic() && tn_regs.cmp64 > hpet_next_wrap(cu= r_tick) { + tn_regs.wrap_flag =3D 1; + self.arm_timer(tn_regs, hpet_next_wrap(cur_tick)); return; } } - self.arm_timer(regs, self.cmp64); + self.arm_timer(tn_regs, tn_regs.cmp64); } =20 fn del_timer(&self, regs: &mut HPETRegisters) { @@ -431,7 +425,7 @@ fn prepare_tn_cfg_reg_new( } =20 /// Configuration and Capability Register - fn set_tn_cfg_reg(&mut self, regs: &mut HPETRegisters, shift: u32, len= : u32, val: u64) { + fn set_tn_cfg_reg(&self, regs: &mut HPETRegisters, shift: u32, len: u3= 2, val: u64) { // Factor out a prepare_tn_cfg_reg_new() to better handle immutabl= e scope. let (new_val, old_val) =3D self.prepare_tn_cfg_reg_new(regs, shift= , len, val); regs.tn_regs[self.index as usize].config =3D new_val; @@ -445,7 +439,7 @@ fn set_tn_cfg_reg(&mut self, regs: &mut HPETRegisters, = shift: u32, len: u32, val let tn_regs =3D &mut regs.tn_regs[self.index as usize]; if tn_regs.is_32bit_mod() { tn_regs.cmp =3D u64::from(tn_regs.cmp as u32); // truncate! - self.period =3D u64::from(self.period as u32); // truncate! + tn_regs.period =3D u64::from(tn_regs.period as u32); // trunca= te! } =20 if regs.is_hpet_enabled() { @@ -454,7 +448,7 @@ fn set_tn_cfg_reg(&mut self, regs: &mut HPETRegisters, = shift: u32, len: u32, val } =20 /// Comparator Value Register - fn set_tn_cmp_reg(&mut self, regs: &mut HPETRegisters, shift: u32, len= : u32, val: u64) { + fn set_tn_cmp_reg(&self, regs: &mut HPETRegisters, shift: u32, len: u3= 2, val: u64) { let tn_regs =3D &mut regs.tn_regs[self.index as usize]; let mut length =3D len; let mut value =3D val; @@ -476,7 +470,7 @@ fn set_tn_cmp_reg(&mut self, regs: &mut HPETRegisters, = shift: u32, len: u32, val } =20 if tn_regs.is_periodic() { - self.period =3D self.period.deposit(shift, length, value); + tn_regs.period =3D tn_regs.period.deposit(shift, length, value= ); } =20 tn_regs.clear_valset(); @@ -491,7 +485,7 @@ fn set_tn_fsb_route_reg(&self, regs: &mut HPETRegisters= , shift: u32, len: u32, v tn_regs.fsb =3D tn_regs.fsb.deposit(shift, len, val); } =20 - fn reset(&mut self, regs: &mut HPETRegisters) { + fn reset(&self, regs: &mut HPETRegisters) { self.del_timer(regs); =20 let tn_regs =3D &mut regs.tn_regs[self.index as usize]; @@ -503,29 +497,28 @@ fn reset(&mut self, regs: &mut HPETRegisters) { // advertise availability of ioapic int tn_regs.config |=3D (u64::from(self.get_state().int_route_cap)) << HPET_TN_CFG_INT= _ROUTE_CAP_SHIFT; - self.period =3D 0; - self.wrap_flag =3D 0; + tn_regs.period =3D 0; + tn_regs.wrap_flag =3D 0; } =20 /// timer expiration callback - fn callback(&mut self, regs: &mut HPETRegisters) { + fn callback(&self, regs: &mut HPETRegisters) { let tn_regs =3D &mut regs.tn_regs[self.index as usize]; - let period: u64 =3D self.period; let cur_tick: u64 =3D self.get_state().get_ticks(); =20 - if tn_regs.is_periodic() && period !=3D 0 { - while hpet_time_after(cur_tick, self.cmp64) { - self.cmp64 +=3D period; + if tn_regs.is_periodic() && tn_regs.period !=3D 0 { + while hpet_time_after(cur_tick, tn_regs.cmp64) { + tn_regs.cmp64 +=3D tn_regs.period; } if tn_regs.is_32bit_mod() { - tn_regs.cmp =3D u64::from(self.cmp64 as u32); // truncate! + tn_regs.cmp =3D u64::from(tn_regs.cmp64 as u32); // trunca= te! } else { - tn_regs.cmp =3D self.cmp64; + tn_regs.cmp =3D tn_regs.cmp64; } - self.arm_timer(regs, self.cmp64); - } else if self.wrap_flag !=3D 0 { - self.wrap_flag =3D 0; - self.arm_timer(regs, self.cmp64); + self.arm_timer(tn_regs, tn_regs.cmp64); + } else if tn_regs.wrap_flag !=3D 0 { + tn_regs.wrap_flag =3D 0; + self.arm_timer(tn_regs, tn_regs.cmp64); } self.update_irq(regs, true); } @@ -542,7 +535,7 @@ fn read(&self, target: TimerRegister, regs: &HPETRegist= ers) -> u64 { } =20 fn write( - &mut self, + &self, target: TimerRegister, regs: &mut HPETRegisters, value: u64, @@ -691,7 +684,7 @@ fn set_cfg_reg(&self, regs: &mut HPETRegisters, shift: = u32, len: u32, val: u64) .set(ticks_to_ns(regs.counter) - CLOCK_VIRTUAL.get_ns()); =20 for timer in self.timers.iter().take(self.num_timers) { - let mut t =3D timer.borrow_mut(); + let t =3D timer.borrow(); let id =3D t.index as usize; let tn_regs =3D ®s.tn_regs[id]; =20 @@ -815,7 +808,7 @@ fn realize(&self) -> util::Result<()> { fn reset_hold(&self, _type: ResetType) { let mut regs =3D self.regs.borrow_mut(); for timer in self.timers.iter().take(self.num_timers) { - timer.borrow_mut().reset(&mut regs); + timer.borrow().reset(&mut regs); } =20 regs.counter =3D 0; @@ -871,7 +864,7 @@ fn read(&self, addr: hwaddr, size: u32) -> u64 { use DecodedRegister::*; use GlobalRegister::*; (match target { - Timer(timer, tn_target) =3D> timer.borrow_mut().read(tn_target= , regs), + Timer(timer, tn_target) =3D> timer.borrow().read(tn_target, re= gs), Global(CAP) =3D> regs.capability, /* including HPET_PERIOD 0x0= 04 */ Global(CFG) =3D> regs.config, Global(INT_STATUS) =3D> regs.int_status, @@ -903,7 +896,7 @@ fn write(&self, addr: hwaddr, value: u64, size: u32) { use GlobalRegister::*; match target { Timer(timer, tn_target) =3D> timer - .borrow_mut() + .borrow() .write(tn_target, &mut regs, value, shift, len), Global(CAP) =3D> {} // General Capabilities and ID Register: R= ead Only Global(CFG) =3D> self.set_cfg_reg(&mut regs, shift, len, value= ), @@ -929,15 +922,14 @@ fn pre_save(&self) -> Result<(), migration::Infallibl= e> { } =20 fn post_load(&self, _version_id: u8) -> Result<(), migration::Infallib= le> { - let regs =3D self.regs.borrow(); + let mut regs =3D self.regs.borrow_mut(); + let cnt =3D regs.counter; =20 - for timer in self.timers.iter().take(self.num_timers) { - let mut t =3D timer.borrow_mut(); - let cnt =3D regs.counter; - let cmp =3D regs.tn_regs[t.index as usize].cmp; + for index in 0..self.num_timers { + let tn_regs =3D &mut regs.tn_regs[index]; =20 - t.cmp64 =3D t.calculate_cmp64(®s, cnt, cmp); - t.last =3D CLOCK_VIRTUAL.get_ns() - NANOSECONDS_PER_SECOND; + tn_regs.update_cmp64(cnt); + tn_regs.last =3D CLOCK_VIRTUAL.get_ns() - NANOSECONDS_PER_SECO= ND; } =20 // Recalculate the offset between the main counter and guest time @@ -1010,6 +1002,8 @@ impl ObjectImpl for HPETState { vmstate_of!(HPETTimerRegisters, config), vmstate_of!(HPETTimerRegisters, cmp), vmstate_of!(HPETTimerRegisters, fsb), + vmstate_of!(HPETTimerRegisters, period), + vmstate_of!(HPETTimerRegisters, wrap_flag), }) .build() ); @@ -1020,9 +1014,6 @@ impl ObjectImpl for HPETState { .version_id(2) .minimum_version_id(2) .fields(vmstate_fields! { - vmstate_of!(HPETTimer, index), - vmstate_of!(HPETTimer, period), - vmstate_of!(HPETTimer, wrap_flag), vmstate_of!(HPETTimer, qemu_timer), }) .build(); --=20 2.52.0