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charset="utf-8" From: Zhao Liu Place all timer N's registers in a HPETTimerRegisters struct. This allows all Timer N registers to be grouped together with global registers and managed using a single lock (BqlRefCell or Mutex) in future. And this makes it easier to apply ToMigrationState macro. Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20251113051937.4017675-11-zhao1.liu@intel.c= om Signed-off-by: Paolo Bonzini --- rust/hw/timer/hpet/src/device.rs | 101 ++++++++++++++++++------------- 1 file changed, 60 insertions(+), 41 deletions(-) diff --git a/rust/hw/timer/hpet/src/device.rs b/rust/hw/timer/hpet/src/devi= ce.rs index c5b58f8dee7..1bdee064d43 100644 --- a/rust/hw/timer/hpet/src/device.rs +++ b/rust/hw/timer/hpet/src/device.rs @@ -174,6 +174,18 @@ fn timer_handler(timer_cell: &BqlRefCell) { timer_cell.borrow_mut().callback() } =20 +#[repr(C)] +#[derive(Debug, Default)] +pub struct HPETTimerRegisters { + // Memory-mapped, software visible timer registers + /// Timer N Configuration and Capability Register + config: u64, + /// Timer N Comparator Value Register + cmp: u64, + /// Timer N FSB Interrupt Route Register + fsb: u64, +} + /// HPET Timer Abstraction #[repr(C)] #[derive(Debug)] @@ -185,14 +197,7 @@ pub struct HPETTimer { /// timer block abstraction containing this timer state: NonNull, =20 - // Memory-mapped, software visible timer registers - /// Timer N Configuration and Capability Register - config: u64, - /// Timer N Comparator Value Register - cmp: u64, - /// Timer N FSB Interrupt Route Register - fsb: u64, - + regs: HPETTimerRegisters, // Hidden register state /// comparator (extended to counter width) cmp64: u64, @@ -217,9 +222,7 @@ fn new(index: u8, state: *const HPETState) -> HPETTimer= { // is initialized below. qemu_timer: unsafe { Timer::new() }, state: NonNull::new(state.cast_mut()).unwrap(), - config: 0, - cmp: 0, - fsb: 0, + regs: Default::default(), cmp64: 0, period: 0, wrap_flag: 0, @@ -246,32 +249,32 @@ fn is_int_active(&self) -> bool { } =20 const fn is_fsb_route_enabled(&self) -> bool { - self.config & (1 << HPET_TN_CFG_FSB_ENABLE_SHIFT) !=3D 0 + self.regs.config & (1 << HPET_TN_CFG_FSB_ENABLE_SHIFT) !=3D 0 } =20 const fn is_periodic(&self) -> bool { - self.config & (1 << HPET_TN_CFG_PERIODIC_SHIFT) !=3D 0 + self.regs.config & (1 << HPET_TN_CFG_PERIODIC_SHIFT) !=3D 0 } =20 const fn is_int_enabled(&self) -> bool { - self.config & (1 << HPET_TN_CFG_INT_ENABLE_SHIFT) !=3D 0 + self.regs.config & (1 << HPET_TN_CFG_INT_ENABLE_SHIFT) !=3D 0 } =20 const fn is_32bit_mod(&self) -> bool { - self.config & (1 << HPET_TN_CFG_32BIT_SHIFT) !=3D 0 + self.regs.config & (1 << HPET_TN_CFG_32BIT_SHIFT) !=3D 0 } =20 const fn is_valset_enabled(&self) -> bool { - self.config & (1 << HPET_TN_CFG_SETVAL_SHIFT) !=3D 0 + self.regs.config & (1 << HPET_TN_CFG_SETVAL_SHIFT) !=3D 0 } =20 fn clear_valset(&mut self) { - self.config &=3D !(1 << HPET_TN_CFG_SETVAL_SHIFT); + self.regs.config &=3D !(1 << HPET_TN_CFG_SETVAL_SHIFT); } =20 /// True if timer interrupt is level triggered; otherwise, edge trigge= red. const fn is_int_level_triggered(&self) -> bool { - self.config & (1 << HPET_TN_CFG_INT_TYPE_SHIFT) !=3D 0 + self.regs.config & (1 << HPET_TN_CFG_INT_TYPE_SHIFT) !=3D 0 } =20 /// calculate next value of the general counter that matches the @@ -290,7 +293,7 @@ fn calculate_cmp64(&self, cur_tick: u64, target: u64) -= > u64 { } =20 const fn get_individual_route(&self) -> usize { - ((self.config & HPET_TN_CFG_INT_ROUTE_MASK) >> HPET_TN_CFG_INT_ROU= TE_SHIFT) as usize + ((self.regs.config & HPET_TN_CFG_INT_ROUTE_MASK) >> HPET_TN_CFG_IN= T_ROUTE_SHIFT) as usize } =20 fn get_int_route(&self) -> usize { @@ -328,8 +331,8 @@ fn set_irq(&self, set: bool) { unsafe { address_space_stl_le( addr_of_mut!(address_space_memory), - self.fsb >> 32, // Timer N FSB int addr - self.fsb as u32, // Timer N FSB int value, truncat= e! + self.regs.fsb >> 32, // Timer N FSB int addr + self.regs.fsb as u32, // Timer N FSB int value, tr= uncate! MEMTXATTRS_UNSPECIFIED, null_mut(), ); @@ -369,7 +372,7 @@ fn set_timer(&mut self) { let cur_tick: u64 =3D self.get_state().get_ticks(); =20 self.wrap_flag =3D 0; - self.cmp64 =3D self.calculate_cmp64(cur_tick, self.cmp); + self.cmp64 =3D self.calculate_cmp64(cur_tick, self.regs.cmp); if self.is_32bit_mod() { // HPET spec says in one-shot 32-bit mode, generate an interru= pt when // counter wraps in addition to an interrupt with comparator m= atch. @@ -398,25 +401,25 @@ fn del_timer(&self) { fn set_tn_cfg_reg(&mut self, shift: u32, len: u32, val: u64) { trace::trace_hpet_ram_write_tn_cfg((shift / 8).try_into().unwrap()= ); =20 - let old_val: u64 =3D self.config; + let old_val: u64 =3D self.regs.config; let mut new_val: u64 =3D old_val.deposit(shift, len, val); new_val =3D hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MAS= K); =20 // Switch level-type interrupt to edge-type. if deactivating_bit(old_val, new_val, HPET_TN_CFG_INT_TYPE_SHIFT) { - // Do this before changing timer.config; otherwise, if + // Do this before changing timer.regs.config; otherwise, if // HPET_TN_FSB is set, update_irq will not lower the qemu_irq. self.update_irq(false); } =20 - self.config =3D new_val; + self.regs.config =3D new_val; =20 if activating_bit(old_val, new_val, HPET_TN_CFG_INT_ENABLE_SHIFT) = && self.is_int_active() { self.update_irq(true); } =20 if self.is_32bit_mod() { - self.cmp =3D u64::from(self.cmp as u32); // truncate! + self.regs.cmp =3D u64::from(self.regs.cmp as u32); // truncate! self.period =3D u64::from(self.period as u32); // truncate! } =20 @@ -443,7 +446,7 @@ fn set_tn_cmp_reg(&mut self, shift: u32, len: u32, val:= u64) { trace::trace_hpet_ram_write_tn_cmp((shift / 8).try_into().unwrap()= ); =20 if !self.is_periodic() || self.is_valset_enabled() { - self.cmp =3D self.cmp.deposit(shift, length, value); + self.regs.cmp =3D self.regs.cmp.deposit(shift, length, value); } =20 if self.is_periodic() { @@ -458,18 +461,19 @@ fn set_tn_cmp_reg(&mut self, shift: u32, len: u32, va= l: u64) { =20 /// FSB Interrupt Route Register fn set_tn_fsb_route_reg(&mut self, shift: u32, len: u32, val: u64) { - self.fsb =3D self.fsb.deposit(shift, len, val); + self.regs.fsb =3D self.regs.fsb.deposit(shift, len, val); } =20 fn reset(&mut self) { self.del_timer(); - self.cmp =3D u64::MAX; // Comparator Match Registers reset to all = 1's. - self.config =3D (1 << HPET_TN_CFG_PERIODIC_CAP_SHIFT) | (1 << HPET= _TN_CFG_SIZE_CAP_SHIFT); + self.regs.cmp =3D u64::MAX; // Comparator Match Registers reset to= all 1's. + self.regs.config =3D + (1 << HPET_TN_CFG_PERIODIC_CAP_SHIFT) | (1 << HPET_TN_CFG_SIZE= _CAP_SHIFT); if self.get_state().has_msi_flag() { - self.config |=3D 1 << HPET_TN_CFG_FSB_CAP_SHIFT; + self.regs.config |=3D 1 << HPET_TN_CFG_FSB_CAP_SHIFT; } // advertise availability of ioapic int - self.config |=3D + self.regs.config |=3D (u64::from(self.get_state().int_route_cap)) << HPET_TN_CFG_INT= _ROUTE_CAP_SHIFT; self.period =3D 0; self.wrap_flag =3D 0; @@ -485,9 +489,9 @@ fn callback(&mut self) { self.cmp64 +=3D period; } if self.is_32bit_mod() { - self.cmp =3D u64::from(self.cmp64 as u32); // truncate! + self.regs.cmp =3D u64::from(self.cmp64 as u32); // truncat= e! } else { - self.cmp =3D self.cmp64; + self.regs.cmp =3D self.cmp64; } self.arm_timer(self.cmp64); } else if self.wrap_flag !=3D 0 { @@ -500,9 +504,9 @@ fn callback(&mut self) { const fn read(&self, target: TimerRegister) -> u64 { use TimerRegister::*; match target { - CFG =3D> self.config, // including interrupt capabilities - CMP =3D> self.cmp, // comparator register - ROUTE =3D> self.fsb, + CFG =3D> self.regs.config, // including interrupt capabilities + CMP =3D> self.regs.cmp, // comparator register + ROUTE =3D> self.regs.fsb, } } =20 @@ -862,7 +866,7 @@ fn post_load(&self, _version_id: u8) -> Result<(), migr= ation::Infallible> { for timer in self.timers.iter().take(self.num_timers) { let mut t =3D timer.borrow_mut(); =20 - t.cmp64 =3D t.calculate_cmp64(t.get_state().counter.get(), t.c= mp); + t.cmp64 =3D t.calculate_cmp64(t.get_state().counter.get(), t.r= egs.cmp); t.last =3D CLOCK_VIRTUAL.get_ns() - NANOSECONDS_PER_SECOND; } =20 @@ -926,6 +930,22 @@ impl ObjectImpl for HPETState { }) .build(); =20 +// In fact, version_id and minimum_version_id for HPETTimerRegisters are +// unrelated to HPETTimer's version IDs. Does not affect compatibility. +impl_vmstate_struct!( + HPETTimerRegisters, + VMStateDescriptionBuilder::::new() + .name(c"hpet_timer/regs") + .version_id(1) + .minimum_version_id(1) + .fields(vmstate_fields! { + vmstate_of!(HPETTimerRegisters, config), + vmstate_of!(HPETTimerRegisters, cmp), + vmstate_of!(HPETTimerRegisters, fsb), + }) + .build() +); + const VMSTATE_HPET_TIMER: VMStateDescription =3D VMStateDescriptionBuilder::::new() .name(c"hpet_timer") @@ -933,14 +953,13 @@ impl ObjectImpl for HPETState { .minimum_version_id(1) .fields(vmstate_fields! { vmstate_of!(HPETTimer, index), - vmstate_of!(HPETTimer, config), - vmstate_of!(HPETTimer, cmp), - vmstate_of!(HPETTimer, fsb), + vmstate_of!(HPETTimer, regs), vmstate_of!(HPETTimer, period), vmstate_of!(HPETTimer, wrap_flag), vmstate_of!(HPETTimer, qemu_timer), }) .build(); + impl_vmstate_struct!(HPETTimer, VMSTATE_HPET_TIMER); =20 const VALIDATE_TIMERS_NAME: &CStr =3D c"num_timers must match"; --=20 2.52.0