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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/8] target/s390x: Use explicit big-endian LD/ST API Date: Wed, 24 Dec 2025 17:20:29 +0100 Message-ID: <20251224162036.90404-3-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224162036.90404-1-philmd@linaro.org> References: <20251224162036.90404-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766593291519158500 The S390x architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change running: $ for a in uw w l q; do \ sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \ $(git grep -wlE '(ld|st)u?[wlq]_p' target/s390x/); done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Manos Pitsidianakis --- target/s390x/cpu-system.c | 2 +- target/s390x/kvm/kvm.c | 8 ++++---- target/s390x/mmu_helper.c | 3 ++- target/s390x/tcg/excp_helper.c | 16 ++++++++-------- target/s390x/tcg/mem_helper.c | 5 +++-- 5 files changed, 18 insertions(+), 16 deletions(-) diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index f3a9ffb2a27..b0c59b5676e 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -63,7 +63,7 @@ static void s390_cpu_load_normal(CPUState *s) uint64_t spsw; =20 if (!s390_is_pv()) { - spsw =3D ldq_phys(s->as, 0); + spsw =3D ldq_be_phys(s->as, 0); cpu->env.psw.mask =3D spsw & PSW_MASK_SHORT_CTRL; /* * Invert short psw indication, so SIE will report a specification diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 916dac1f14e..89911f356e4 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -1667,10 +1667,10 @@ static int handle_oper_loop(S390CPU *cpu, struct kv= m_run *run) CPUState *cs =3D CPU(cpu); PSW oldpsw, newpsw; =20 - newpsw.mask =3D ldq_phys(cs->as, cpu->env.psa + - offsetof(LowCore, program_new_psw)); - newpsw.addr =3D ldq_phys(cs->as, cpu->env.psa + - offsetof(LowCore, program_new_psw) + 8); + newpsw.mask =3D ldq_be_phys(cs->as, cpu->env.psa + + offsetof(LowCore, program_new_psw)); + newpsw.addr =3D ldq_be_phys(cs->as, cpu->env.psa + + offsetof(LowCore, program_new_psw) + 8); oldpsw.mask =3D run->psw_mask; oldpsw.addr =3D run->psw_addr; /* diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 3b1e75f7833..8c87b30a8e3 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -44,7 +44,8 @@ static void trigger_access_exception(CPUS390XState *env, = uint32_t type, } else { CPUState *cs =3D env_cpu(env); if (type !=3D PGM_ADDRESSING) { - stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code),= tec); + stq_be_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_cod= e), + tec); } trigger_pgm_exception(env, type); } diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index c6641280bc6..868efca3221 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -55,8 +55,8 @@ G_NORETURN void tcg_s390_data_exception(CPUS390XState *en= v, uint32_t dxc, g_assert(dxc <=3D 0xff); #if !defined(CONFIG_USER_ONLY) /* Store the DXC into the lowcore */ - stl_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, data_exc_code), dxc); + stl_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, data_exc_code), dxc); #endif =20 /* Store the DXC into the FPC if AFP is enabled */ @@ -72,8 +72,8 @@ G_NORETURN void tcg_s390_vector_exception(CPUS390XState *= env, uint32_t vxc, g_assert(vxc <=3D 0xff); #if !defined(CONFIG_USER_ONLY) /* Always store the VXC into the lowcore, without AFP it is undefined = */ - stl_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, data_exc_code), vxc); + stl_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, data_exc_code), vxc); #endif =20 /* Always store the VXC into the FPC, without AFP it is undefined */ @@ -651,10 +651,10 @@ void monitor_event(CPUS390XState *env, uint8_t monitor_class, uintptr_t ra) { /* Store the Monitor Code and the Monitor Class Number into the lowcor= e */ - stq_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, monitor_code), monitor_code); - stw_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, mon_class_num), monitor_class); + stq_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, monitor_code), monitor_code); + stw_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, mon_class_num), monitor_class= ); =20 tcg_s390_program_interrupt(env, PGM_MONITOR, ra); } diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 24675fc818d..0c7e099df21 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -958,8 +958,9 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, = uint32_t r1, uint32_t r2) inject_exc: #if !defined(CONFIG_USER_ONLY) if (exc !=3D PGM_ADDRESSING) { - stq_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, trans_exc_= code), - env->tlb_fill_tec); + stq_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, trans_exc_code), + env->tlb_fill_tec); } if (exc =3D=3D PGM_PAGE_TRANS) { stb_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, op_access_= id), --=20 2.52.0