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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/8] hw/s390x: Use explicit big-endian LD/ST API Date: Wed, 24 Dec 2025 17:20:28 +0100 Message-ID: <20251224162036.90404-2-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224162036.90404-1-philmd@linaro.org> References: <20251224162036.90404-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766593339624158500 The S390x architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change running: $ for a in uw w l q; do \ sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \ $(git grep -wlE '(ld|st)u?[wlq]_p' hw/s390x/); done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Farman Reviewed-by: Halil Pasic Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- hw/s390x/css.c | 24 +++++++++++------------- hw/s390x/s390-pci-bus.c | 4 ++-- hw/s390x/virtio-ccw.c | 24 ++++++++++++------------ 3 files changed, 25 insertions(+), 27 deletions(-) diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 53444f68288..4bc2253c182 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -1582,27 +1582,25 @@ static void css_update_chnmon(SubchDev *sch) /* Format 1, per-subchannel area. */ uint32_t count; =20 - count =3D address_space_ldl(&address_space_memory, - sch->curr_status.mba, - MEMTXATTRS_UNSPECIFIED, - NULL); + count =3D address_space_ldl_be(&address_space_memory, + sch->curr_status.mba, + MEMTXATTRS_UNSPECIFIED, NULL); count++; - address_space_stl(&address_space_memory, sch->curr_status.mba, cou= nt, - MEMTXATTRS_UNSPECIFIED, NULL); + address_space_stl_be(&address_space_memory, sch->curr_status.mba, = count, + MEMTXATTRS_UNSPECIFIED, NULL); } else { /* Format 0, global area. */ uint32_t offset; uint16_t count; =20 offset =3D sch->curr_status.pmcw.mbi << 5; - count =3D address_space_lduw(&address_space_memory, - channel_subsys.chnmon_area + offset, - MEMTXATTRS_UNSPECIFIED, - NULL); + count =3D address_space_lduw_be(&address_space_memory, + channel_subsys.chnmon_area + offset, + MEMTXATTRS_UNSPECIFIED, NULL); count++; - address_space_stw(&address_space_memory, - channel_subsys.chnmon_area + offset, count, - MEMTXATTRS_UNSPECIFIED, NULL); + address_space_stw_be(&address_space_memory, + channel_subsys.chnmon_area + offset, count, + MEMTXATTRS_UNSPECIFIED, NULL); } } =20 diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 52820894fa1..aeeed82955a 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -461,8 +461,8 @@ static uint64_t table_translate(S390IOTLBEntry *entry, = uint64_t to, int8_t ett, uint16_t err =3D 0; =20 tx =3D get_table_index(entry->iova, ett); - te =3D address_space_ldq(&address_space_memory, to + tx * sizeof(uint6= 4_t), - MEMTXATTRS_UNSPECIFIED, NULL); + te =3D address_space_ldq_be(&address_space_memory, to + tx * sizeof(ui= nt64_t), + MEMTXATTRS_UNSPECIFIED, NULL); =20 if (!te) { err =3D ERR_EVENT_INVALTE; diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 4a3ffb84f8f..9dd838c61e4 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -889,26 +889,26 @@ static void virtio_ccw_notify(DeviceState *d, uint16_= t vector) } } else { assert(vector < NR_CLASSIC_INDICATOR_BITS); - indicators =3D address_space_ldq(&address_space_memory, - dev->indicators->addr, - MEMTXATTRS_UNSPECIFIED, - NULL); + indicators =3D address_space_ldq_be(&address_space_memory, + dev->indicators->addr, + MEMTXATTRS_UNSPECIFIED, + NULL); indicators |=3D 1ULL << vector; - address_space_stq(&address_space_memory, dev->indicators->addr, - indicators, MEMTXATTRS_UNSPECIFIED, NULL); + address_space_stq_be(&address_space_memory, dev->indicators->a= ddr, + indicators, MEMTXATTRS_UNSPECIFIED, NULL); css_conditional_io_interrupt(sch); } } else { if (!dev->indicators2) { return; } - indicators =3D address_space_ldq(&address_space_memory, - dev->indicators2->addr, - MEMTXATTRS_UNSPECIFIED, - NULL); + indicators =3D address_space_ldq_be(&address_space_memory, + dev->indicators2->addr, + MEMTXATTRS_UNSPECIFIED, + NULL); indicators |=3D 1ULL; - address_space_stq(&address_space_memory, dev->indicators2->addr, - indicators, MEMTXATTRS_UNSPECIFIED, NULL); + address_space_stq_be(&address_space_memory, dev->indicators2->addr, + indicators, MEMTXATTRS_UNSPECIFIED, NULL); css_conditional_io_interrupt(sch); } } --=20 2.52.0 From nobody Mon Feb 9 05:13:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1766593290; cv=none; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/8] target/s390x: Use explicit big-endian LD/ST API Date: Wed, 24 Dec 2025 17:20:29 +0100 Message-ID: <20251224162036.90404-3-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224162036.90404-1-philmd@linaro.org> References: <20251224162036.90404-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766593291519158500 The S390x architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change running: $ for a in uw w l q; do \ sed -i -e "s/ld${a}_p(/ld${a}_be_p(/" \ $(git grep -wlE '(ld|st)u?[wlq]_p' target/s390x/); done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Farman Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- target/s390x/cpu-system.c | 2 +- target/s390x/kvm/kvm.c | 8 ++++---- target/s390x/mmu_helper.c | 3 ++- target/s390x/tcg/excp_helper.c | 16 ++++++++-------- target/s390x/tcg/mem_helper.c | 5 +++-- 5 files changed, 18 insertions(+), 16 deletions(-) diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index f3a9ffb2a27..b0c59b5676e 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -63,7 +63,7 @@ static void s390_cpu_load_normal(CPUState *s) uint64_t spsw; =20 if (!s390_is_pv()) { - spsw =3D ldq_phys(s->as, 0); + spsw =3D ldq_be_phys(s->as, 0); cpu->env.psw.mask =3D spsw & PSW_MASK_SHORT_CTRL; /* * Invert short psw indication, so SIE will report a specification diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 916dac1f14e..89911f356e4 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -1667,10 +1667,10 @@ static int handle_oper_loop(S390CPU *cpu, struct kv= m_run *run) CPUState *cs =3D CPU(cpu); PSW oldpsw, newpsw; =20 - newpsw.mask =3D ldq_phys(cs->as, cpu->env.psa + - offsetof(LowCore, program_new_psw)); - newpsw.addr =3D ldq_phys(cs->as, cpu->env.psa + - offsetof(LowCore, program_new_psw) + 8); + newpsw.mask =3D ldq_be_phys(cs->as, cpu->env.psa + + offsetof(LowCore, program_new_psw)); + newpsw.addr =3D ldq_be_phys(cs->as, cpu->env.psa + + offsetof(LowCore, program_new_psw) + 8); oldpsw.mask =3D run->psw_mask; oldpsw.addr =3D run->psw_addr; /* diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 3b1e75f7833..8c87b30a8e3 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -44,7 +44,8 @@ static void trigger_access_exception(CPUS390XState *env, = uint32_t type, } else { CPUState *cs =3D env_cpu(env); if (type !=3D PGM_ADDRESSING) { - stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code),= tec); + stq_be_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_cod= e), + tec); } trigger_pgm_exception(env, type); } diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index c6641280bc6..868efca3221 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -55,8 +55,8 @@ G_NORETURN void tcg_s390_data_exception(CPUS390XState *en= v, uint32_t dxc, g_assert(dxc <=3D 0xff); #if !defined(CONFIG_USER_ONLY) /* Store the DXC into the lowcore */ - stl_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, data_exc_code), dxc); + stl_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, data_exc_code), dxc); #endif =20 /* Store the DXC into the FPC if AFP is enabled */ @@ -72,8 +72,8 @@ G_NORETURN void tcg_s390_vector_exception(CPUS390XState *= env, uint32_t vxc, g_assert(vxc <=3D 0xff); #if !defined(CONFIG_USER_ONLY) /* Always store the VXC into the lowcore, without AFP it is undefined = */ - stl_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, data_exc_code), vxc); + stl_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, data_exc_code), vxc); #endif =20 /* Always store the VXC into the FPC, without AFP it is undefined */ @@ -651,10 +651,10 @@ void monitor_event(CPUS390XState *env, uint8_t monitor_class, uintptr_t ra) { /* Store the Monitor Code and the Monitor Class Number into the lowcor= e */ - stq_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, monitor_code), monitor_code); - stw_phys(env_cpu(env)->as, - env->psa + offsetof(LowCore, mon_class_num), monitor_class); + stq_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, monitor_code), monitor_code); + stw_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, mon_class_num), monitor_class= ); =20 tcg_s390_program_interrupt(env, PGM_MONITOR, ra); } diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 24675fc818d..0c7e099df21 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -958,8 +958,9 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, = uint32_t r1, uint32_t r2) inject_exc: #if !defined(CONFIG_USER_ONLY) if (exc !=3D PGM_ADDRESSING) { - stq_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, trans_exc_= code), - env->tlb_fill_tec); + stq_be_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, trans_exc_code), + env->tlb_fill_tec); } if (exc =3D=3D PGM_PAGE_TRANS) { stb_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, op_access_= id), --=20 2.52.0 From nobody Mon Feb 9 05:13:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/8] target/s390x: Replace gdb_get_regl() -> gdb_get_reg64() Date: Wed, 24 Dec 2025 17:20:30 +0100 Message-ID: <20251224162036.90404-4-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224162036.90404-1-philmd@linaro.org> References: <20251224162036.90404-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766593381712158500 We only build s390x targets as 64-bit: $ git grep BIT configs/targets/s390x-* configs/targets/s390x-linux-user.mak:6:TARGET_LONG_BITS=3D64 configs/targets/s390x-softmmu.mak:5:TARGET_LONG_BITS=3D64 Therefore gdb_get_regl() expands to gdb_get_reg64(). Use the latter which is more explicit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Farman Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- target/s390x/gdbstub.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6bca376f2b6..d1f02ea5ce4 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -34,11 +34,11 @@ int s390_cpu_gdb_read_register(CPUState *cs, GByteArray= *mem_buf, int n) =20 switch (n) { case S390_PSWM_REGNUM: - return gdb_get_regl(mem_buf, s390_cpu_get_psw_mask(env)); + return gdb_get_reg64(mem_buf, s390_cpu_get_psw_mask(env)); case S390_PSWA_REGNUM: - return gdb_get_regl(mem_buf, env->psw.addr); + return gdb_get_reg64(mem_buf, env->psw.addr); case S390_R0_REGNUM ... S390_R15_REGNUM: - return gdb_get_regl(mem_buf, env->regs[n - S390_R0_REGNUM]); + return gdb_get_reg64(mem_buf, env->regs[n - S390_R0_REGNUM]); } return 0; } @@ -190,7 +190,7 @@ static int cpu_read_c_reg(CPUState *cs, GByteArray *buf= , int n) =20 switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: - return gdb_get_regl(buf, env->cregs[n]); + return gdb_get_reg64(buf, env->cregs[n]); default: return 0; } @@ -227,13 +227,13 @@ static int cpu_read_virt_reg(CPUState *cs, GByteArray= *mem_buf, int n) =20 switch (n) { case S390_VIRT_CKC_REGNUM: - return gdb_get_regl(mem_buf, env->ckc); + return gdb_get_reg64(mem_buf, env->ckc); case S390_VIRT_CPUTM_REGNUM: - return gdb_get_regl(mem_buf, env->cputm); + return gdb_get_reg64(mem_buf, env->cputm); case S390_VIRT_BEA_REGNUM: - return gdb_get_regl(mem_buf, env->gbea); + return gdb_get_reg64(mem_buf, env->gbea); case S390_VIRT_PREFIX_REGNUM: - return gdb_get_regl(mem_buf, env->psa); + return gdb_get_reg64(mem_buf, env->psa); default: return 0; } @@ -279,13 +279,13 @@ static int cpu_read_virt_kvm_reg(CPUState *cs, GByteA= rray *mem_buf, int n) =20 switch (n) { case S390_VIRT_KVM_PP_REGNUM: - return gdb_get_regl(mem_buf, env->pp); + return gdb_get_reg64(mem_buf, env->pp); case S390_VIRT_KVM_PFT_REGNUM: - return gdb_get_regl(mem_buf, env->pfault_token); + return gdb_get_reg64(mem_buf, env->pfault_token); case S390_VIRT_KVM_PFS_REGNUM: - return gdb_get_regl(mem_buf, env->pfault_select); + return gdb_get_reg64(mem_buf, env->pfault_select); case S390_VIRT_KVM_PFC_REGNUM: - return gdb_get_regl(mem_buf, env->pfault_compare); + return gdb_get_reg64(mem_buf, env->pfault_compare); default: return 0; } @@ -330,7 +330,7 @@ static int cpu_read_gs_reg(CPUState *cs, GByteArray *bu= f, int n) S390CPU *cpu =3D S390_CPU(cs); CPUS390XState *env =3D &cpu->env; =20 - return gdb_get_regl(buf, env->gscb[n]); + return gdb_get_reg64(buf, env->gscb[n]); } =20 static int cpu_write_gs_reg(CPUState *cs, uint8_t *mem_buf, int n) --=20 2.52.0 From nobody Mon Feb 9 05:13:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1766593350; cv=none; d=zohomail.com; s=zohoarc; b=imvedAkb3kblSw2DE+zQkkF1hEYndpE0WfzFuQxkQQ/0h/O1lXSzpnk0ReWFovlKIgaBD1ivmnw+5GF6Stln2uUUYxe9zLN0KjYx0eKk/rUqvHhonrqaSeF74wO4pgcHY1WCmTZf40DgF09i1tl2MeAPiw9jnEIb2m0d75LN9m4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766593350; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MKnVNiuwp72AmXcaguYOR7UuTESAbdncIC//8KVj2SY=; b=UgvG6ao8bLvG4AJPL9LksGL+S1IwmErpyOf8TZdiUNXVJ3eWZ2sBPkeLk2V45f92WWg7/mBUdEqxLaEXC/Oi1ibDjDPFnTizFCjFA48NOZ8ONfZ7OwnySu+58w07u0QgPLo+96vB/SKLVXFMHY5OaVRf03hOJZ+EfeefwSQIijg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766593350862726.183935942479; Wed, 24 Dec 2025 08:22:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYRc6-0001LD-Or; Wed, 24 Dec 2025 11:21:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYRc4-0001Fi-3v for qemu-devel@nongnu.org; Wed, 24 Dec 2025 11:21:24 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vYRbz-0002eT-Qj for qemu-devel@nongnu.org; Wed, 24 Dec 2025 11:21:23 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-477aa218f20so37876115e9.0 for ; Wed, 24 Dec 2025 08:21:19 -0800 (PST) Received: from localhost.localdomain (188.171.88.92.rev.sfr.net. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/8] target/s390x: Replace MO_TE -> MO_BE Date: Wed, 24 Dec 2025 17:20:31 +0100 Message-ID: <20251224162036.90404-5-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224162036.90404-1-philmd@linaro.org> References: <20251224162036.90404-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766593351666158500 We only build the S390x target using big endianness order, therefore the MO_TE definitions expand to the big endian one. Use the latter which is more explicit. Mechanical change running: $ sed -i -e s/MO_TE/MO_BE/ \ $(git grep -wl MO_TE target/s390x/) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Farman Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- target/s390x/tcg/insn-data.h.inc | 54 +++++------ target/s390x/tcg/mem_helper.c | 8 +- target/s390x/tcg/translate.c | 138 ++++++++++++++-------------- target/s390x/tcg/translate_vx.c.inc | 38 ++++---- 4 files changed, 119 insertions(+), 119 deletions(-) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index ec730ee0919..baaafe922e9 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -42,10 +42,10 @@ C(0xb9d8, AHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, adds32) /* ADD IMMEDIATE */ C(0xc209, AFI, RIL_a, EI, r1, i2, new, r1_32, add, adds32) - D(0xeb6a, ASI, SIY, GIE, la1, i2, new, 0, asi, adds32, MO_TESL) + D(0xeb6a, ASI, SIY, GIE, la1, i2, new, 0, asi, adds32, MO_BESL) C(0xecd8, AHIK, RIE_d, DO, r3, i2, new, r1_32, add, adds32) C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64) - D(0xeb7a, AGSI, SIY, GIE, la1, i2, new, 0, asi, adds64, MO_TEUQ) + D(0xeb7a, AGSI, SIY, GIE, la1, i2, new, 0, asi, adds64, MO_BEUQ) C(0xecd9, AGHIK, RIE_d, DO, r3, i2, r1, 0, add, adds64) /* ADD IMMEDIATE HIGH */ C(0xcc08, AIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, adds32) @@ -74,9 +74,9 @@ C(0xc20b, ALFI, RIL_a, EI, r1_32u, i2_32u, new, r1_32, add, addu32) C(0xc20a, ALGFI, RIL_a, EI, r1, i2_32u, r1, 0, addu64, addu64) /* ADD LOGICAL WITH SIGNED IMMEDIATE */ - D(0xeb6e, ALSI, SIY, GIE, la1, i2_32u, new, 0, asi, addu32, MO_TE= UL) + D(0xeb6e, ALSI, SIY, GIE, la1, i2_32u, new, 0, asi, addu32, MO_BE= UL) C(0xecda, ALHSIK, RIE_d, DO, r3_32u, i2_32u, new, r1_32, add, addu32) - D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asiu64, addu64, MO_TEU= Q) + D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asiu64, addu64, MO_BEU= Q) C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, addu64, addu64) /* ADD LOGICAL WITH SIGNED IMMEDIATE HIGH */ C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, addu= 32) @@ -270,12 +270,12 @@ D(0xec7d, CLGIJ, RIE_c, GIE, r1_o, i2_8u, 0, 0, cj, 0, 1) =20 /* COMPARE AND SWAP */ - D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, MO_T= EUL) - D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, MO_T= EUL) - D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, MO_TEUQ) + D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, MO_B= EUL) + D(0xeb14, CSY, RSY_a, LD, r3_32u, r1_32u, new, r1_32, cs, 0, MO_B= EUL) + D(0xeb30, CSG, RSY_a, Z, r3_o, r1_o, new, r1, cs, 0, MO_BEUQ) /* COMPARE DOUBLE AND SWAP */ - D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEUQ) - D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEUQ) + D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= BEUQ) + D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= BEUQ) C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, 0, r1_D64, cdsg, 0) /* COMPARE AND SWAP AND STORE */ C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) @@ -443,20 +443,20 @@ /* LOAD ADDRESS RELATIVE LONG */ C(0xc000, LARL, RIL_b, Z, 0, ri2, 0, r1, mov2, 0) /* LOAD AND ADD */ - D(0xebf8, LAA, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, laa, adds32= , MO_TESL) - D(0xebe8, LAAG, RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_TE= UQ) + D(0xebf8, LAA, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, laa, adds32= , MO_BESL) + D(0xebe8, LAAG, RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_BE= UQ) /* LOAD AND ADD LOGICAL */ - D(0xebfa, LAAL, RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32= , MO_TEUL) - D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa_addu64, addu64= , MO_TEUQ) + D(0xebfa, LAAL, RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32= , MO_BEUL) + D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa_addu64, addu64= , MO_BEUQ) /* LOAD AND AND */ - D(0xebf4, LAN, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, = MO_TESL) - D(0xebe4, LANG, RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_TEUQ) + D(0xebf4, LAN, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, = MO_BESL) + D(0xebe4, LANG, RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_BEUQ) /* LOAD AND EXCLUSIVE OR */ - D(0xebf7, LAX, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lax, nz32, = MO_TESL) - D(0xebe7, LAXG, RSY_a, ILA, r3, a2, new, in2_r1, lax, nz64, MO_TEUQ) + D(0xebf7, LAX, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lax, nz32, = MO_BESL) + D(0xebe7, LAXG, RSY_a, ILA, r3, a2, new, in2_r1, lax, nz64, MO_BEUQ) /* LOAD AND OR */ - D(0xebf6, LAO, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lao, nz32, = MO_TESL) - D(0xebe6, LAOG, RSY_a, ILA, r3, a2, new, in2_r1, lao, nz64, MO_TEUQ) + D(0xebf6, LAO, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lao, nz32, = MO_BESL) + D(0xebe6, LAOG, RSY_a, ILA, r3, a2, new, in2_r1, lao, nz64, MO_BEUQ) /* LOAD AND TEST */ C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32) C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64) @@ -572,8 +572,8 @@ C(0xb9e0, LOCFHR, RRF_c, LOC2, r1_sr32, r2_sr32, new, r1_32h, loc, 0) C(0xebe0, LOCFH, RSY_b, LOC2, r1_sr32, m2_32u, new, r1_32h, loc, 0) /* LOAD PAIR DISJOINT */ - D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL) - D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEUQ) + D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_BEUL) + D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_BEUQ) /* LOAD PAIR FROM QUADWORD */ C(0xe38f, LPQ, RXY_a, Z, 0, a2, 0, r1_D64, lpq, 0) /* LOAD POSITIVE */ @@ -1333,8 +1333,8 @@ =20 #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ - E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, = IF_PRIV) - E(0xb98a, CSPG, RRE, DAT_ENH, r1_o, ra2, r1_P, 0, csp, 0, MO_TEUQ, = IF_PRIV) + E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_BEUL, = IF_PRIV) + E(0xb98a, CSPG, RRE, DAT_ENH, r1_o, ra2, r1_P, 0, csp, 0, MO_BEUQ, = IF_PRIV) /* DIAGNOSE (KVM hypercall) */ F(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0, IF_PRIV | IF_IO) /* INSERT STORAGE KEY EXTENDED */ @@ -1357,8 +1357,8 @@ F(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0, IF_PRIV) F(0xe303, LRAG, RXY_a, Z, 0, a2, r1, 0, lra, 0, IF_PRIV) /* LOAD USING REAL ADDRESS */ - E(0xb24b, LURA, RRE, Z, 0, ra2, new, r1_32, lura, 0, MO_TEUL, I= F_PRIV) - E(0xb905, LURAG, RRE, Z, 0, ra2, r1, 0, lura, 0, MO_TEUQ, IF_PRI= V) + E(0xb24b, LURA, RRE, Z, 0, ra2, new, r1_32, lura, 0, MO_BEUL, I= F_PRIV) + E(0xb905, LURAG, RRE, Z, 0, ra2, r1, 0, lura, 0, MO_BEUQ, IF_PRI= V) /* MOVE TO PRIMARY */ C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0) /* MOVE TO SECONDARY */ @@ -1411,8 +1411,8 @@ /* STORE THEN OR SYSTEM MASK */ F(0xad00, STOSM, SI, Z, la1, 0, 0, 0, stnosm, 0, IF_PRIV) /* STORE USING REAL ADDRESS */ - E(0xb246, STURA, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEUL, IF_= PRIV) - E(0xb925, STURG, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_TEUQ, IF_= PRIV) + E(0xb246, STURA, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_BEUL, IF_= PRIV) + E(0xb925, STURG, RRE, Z, r1_o, ra2, 0, 0, stura, 0, MO_BEUQ, IF_= PRIV) /* TEST BLOCK */ F(0xb22c, TB, RRE, Z, 0, r2_o, 0, 0, testblock, 0, IF_PRIV) /* TEST PROTECTION */ diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0c7e099df21..507eb7feac7 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1776,10 +1776,10 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, uint64_t a2, bool parallel) { uint32_t mem_idx =3D s390x_env_mmu_index(env, false); - MemOpIdx oi16 =3D make_memop_idx(MO_TE | MO_128, mem_idx); - MemOpIdx oi8 =3D make_memop_idx(MO_TE | MO_64, mem_idx); - MemOpIdx oi4 =3D make_memop_idx(MO_TE | MO_32, mem_idx); - MemOpIdx oi2 =3D make_memop_idx(MO_TE | MO_16, mem_idx); + MemOpIdx oi16 =3D make_memop_idx(MO_BE | MO_128, mem_idx); + MemOpIdx oi8 =3D make_memop_idx(MO_BE | MO_64, mem_idx); + MemOpIdx oi4 =3D make_memop_idx(MO_BE | MO_32, mem_idx); + MemOpIdx oi2 =3D make_memop_idx(MO_BE | MO_16, mem_idx); MemOpIdx oi1 =3D make_memop_idx(MO_8, mem_idx); uintptr_t ra =3D GETPC(); uint32_t fc =3D extract32(env->regs[0], 0, 8); diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 4d2b8c5e2be..db2276f1cfc 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1914,7 +1914,7 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps= *o) case 2: case 4: case 8: - mop =3D ctz32(l + 1) | MO_TE; + mop =3D ctz32(l + 1) | MO_BE; /* Do not update cc_src yet: loading cc_dst may cause an exception= . */ src =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_tl(src, o->addr1, get_mem_index(s), mop); @@ -2124,7 +2124,7 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps= *o) static DisasJumpType op_cvb(DisasContext *s, DisasOps *o) { TCGv_i64 t =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_BEUQ); gen_helper_cvb(tcg_env, tcg_constant_i32(get_field(s, r1)), t); return DISAS_NEXT; } @@ -2132,7 +2132,7 @@ static DisasJumpType op_cvb(DisasContext *s, DisasOps= *o) static DisasJumpType op_cvbg(DisasContext *s, DisasOps *o) { TCGv_i128 t =3D tcg_temp_new_i128(); - tcg_gen_qemu_ld_i128(t, o->addr1, get_mem_index(s), MO_TE | MO_128); + tcg_gen_qemu_ld_i128(t, o->addr1, get_mem_index(s), MO_BE | MO_128); gen_helper_cvbg(o->out, tcg_env, t); return DISAS_NEXT; } @@ -2143,7 +2143,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps= *o) TCGv_i32 t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, o->in1); gen_helper_cvd(t1, t2); - tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_BEUQ); return DISAS_NEXT; } =20 @@ -2151,7 +2151,7 @@ static DisasJumpType op_cvdg(DisasContext *s, DisasOp= s *o) { TCGv_i128 t =3D tcg_temp_new_i128(); gen_helper_cvdg(t, o->in1); - tcg_gen_qemu_st_i128(t, o->in2, get_mem_index(s), MO_TE | MO_128); + tcg_gen_qemu_st_i128(t, o->in2, get_mem_index(s), MO_BE | MO_128); return DISAS_NEXT; } =20 @@ -2413,7 +2413,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps= *o) switch (m3) { case 0xf: /* Effectively a 32-bit load. */ - tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUL); len =3D 32; goto one_insert; =20 @@ -2421,7 +2421,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps= *o) case 0x6: case 0x3: /* Effectively a 16-bit load. */ - tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUW); len =3D 16; goto one_insert; =20 @@ -2735,34 +2735,34 @@ static DisasJumpType op_ld8u(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_ld16s(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TESW); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BESW); return DISAS_NEXT; } =20 static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUW); return DISAS_NEXT; } =20 static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o) { tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), - MO_TESL | s->insn->data); + MO_BESL | s->insn->data); return DISAS_NEXT; } =20 static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o) { tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), - MO_TEUL | s->insn->data); + MO_BEUL | s->insn->data); return DISAS_NEXT; } =20 static DisasJumpType op_ld64(DisasContext *s, DisasOps *o) { tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), - MO_TEUQ | s->insn->data); + MO_BEUQ | s->insn->data); return DISAS_NEXT; } =20 @@ -2780,7 +2780,7 @@ static DisasJumpType op_lat(DisasContext *s, DisasOps= *o) static DisasJumpType op_lgat(DisasContext *s, DisasOps *o) { TCGLabel *lab =3D gen_new_label(); - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUQ); /* The value is stored even in case of trap. */ tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); gen_trap(s); @@ -2803,7 +2803,7 @@ static DisasJumpType op_llgfat(DisasContext *s, Disas= Ops *o) { TCGLabel *lab =3D gen_new_label(); =20 - tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUL); /* The value is stored even in case of trap. */ tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); gen_trap(s); @@ -2901,7 +2901,7 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOp= s *o) */ mask =3D tcg_temp_new_i64(); addr =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN= _8); + tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_BEUQ | MO_ALIGN= _8); tcg_gen_andi_i64(addr, mask, PSW_MASK_SHORT_ADDR); tcg_gen_andi_i64(mask, mask, PSW_MASK_SHORT_CTRL); tcg_gen_xori_i64(mask, mask, PSW_MASK_SHORTPSW); @@ -2918,9 +2918,9 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasO= ps *o) t1 =3D tcg_temp_new_i64(); t2 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), - MO_TEUQ | MO_ALIGN_8); + MO_BEUQ | MO_ALIGN_8); tcg_gen_addi_i64(o->in2, o->in2, 8); - tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_BEUQ); gen_helper_load_psw(tcg_env, t1, t2); return DISAS_NORETURN; } @@ -2944,7 +2944,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) /* Only one register to read. */ t1 =3D tcg_temp_new_i64(); if (unlikely(r1 =3D=3D r3)) { - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); store_reg32_i64(r1, t1); return DISAS_NEXT; } @@ -2952,9 +2952,9 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) /* First load the values of the first and last registers to trigger possible page faults. */ t2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); - tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_BEUL); store_reg32_i64(r1, t1); store_reg32_i64(r3, t2); =20 @@ -2969,7 +2969,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) while (r1 !=3D r3) { r1 =3D (r1 + 1) & 15; tcg_gen_add_i64(o->in2, o->in2, t2); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); store_reg32_i64(r1, t1); } return DISAS_NEXT; @@ -2984,7 +2984,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) /* Only one register to read. */ t1 =3D tcg_temp_new_i64(); if (unlikely(r1 =3D=3D r3)) { - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); store_reg32h_i64(r1, t1); return DISAS_NEXT; } @@ -2992,9 +2992,9 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) /* First load the values of the first and last registers to trigger possible page faults. */ t2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); - tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_BEUL); store_reg32h_i64(r1, t1); store_reg32h_i64(r3, t2); =20 @@ -3009,7 +3009,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) while (r1 !=3D r3) { r1 =3D (r1 + 1) & 15; tcg_gen_add_i64(o->in2, o->in2, t2); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL); store_reg32h_i64(r1, t1); } return DISAS_NEXT; @@ -3023,7 +3023,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOp= s *o) =20 /* Only one register to read. */ if (unlikely(r1 =3D=3D r3)) { - tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_BEUQ); return DISAS_NEXT; } =20 @@ -3031,9 +3031,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOp= s *o) possible page faults. */ t1 =3D tcg_temp_new_i64(); t2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUQ); tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15)); - tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_BEUQ); tcg_gen_mov_i64(regs[r1], t1); =20 /* Only two registers to read. */ @@ -3047,7 +3047,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOp= s *o) while (r1 !=3D r3) { r1 =3D (r1 + 1) & 15; tcg_gen_add_i64(o->in2, o->in2, t1); - tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_BEUQ); } return DISAS_NEXT; } @@ -3080,7 +3080,7 @@ static DisasJumpType op_lpq(DisasContext *s, DisasOps= *o) { o->out_128 =3D tcg_temp_new_i128(); tcg_gen_qemu_ld_i128(o->out_128, o->in2, get_mem_index(s), - MO_TE | MO_128 | MO_ALIGN); + MO_BE | MO_128 | MO_ALIGN); return DISAS_NEXT; } =20 @@ -3896,15 +3896,15 @@ static DisasJumpType op_soc(DisasContext *s, DisasO= ps *o) a =3D get_address(s, 0, get_field(s, b2), get_field(s, d2)); switch (s->insn->data) { case 1: /* STOCG */ - tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEUQ); break; case 0: /* STOC */ - tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEUL); break; case 2: /* STOCFH */ h =3D tcg_temp_new_i64(); tcg_gen_shri_i64(h, regs[r1], 32); - tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_BEUL); break; default: g_assert_not_reached(); @@ -4023,7 +4023,7 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOp= s *o) gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0); =20 /* load the third operand into r3 before modifying anything */ - tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_BEUQ); =20 /* subtract CPU timer from first operand and store in GR0 */ gen_helper_stpt(tmp, tcg_env); @@ -4101,9 +4101,9 @@ static DisasJumpType op_stcke(DisasContext *s, DisasO= ps *o) tcg_gen_shri_i64(c1, c1, 8); tcg_gen_ori_i64(c2, c2, 0x10000); tcg_gen_or_i64(c2, c2, todpr); - tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_BEUQ); tcg_gen_addi_i64(o->in2, o->in2, 8); - tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_BEUQ); /* ??? We don't implement clock states. */ gen_op_movi_cc(s, 0); return DISAS_NEXT; @@ -4361,21 +4361,21 @@ static DisasJumpType op_st8(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_st16(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_BEUW); return DISAS_NEXT; } =20 static DisasJumpType op_st32(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s), - MO_TEUL | s->insn->data); + MO_BEUL | s->insn->data); return DISAS_NEXT; } =20 static DisasJumpType op_st64(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), - MO_TEUQ | s->insn->data); + MO_BEUQ | s->insn->data); return DISAS_NEXT; } =20 @@ -4399,7 +4399,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOp= s *o) case 0xf: /* Effectively a 32-bit store. */ tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUL); break; =20 case 0xc: @@ -4407,7 +4407,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOp= s *o) case 0x3: /* Effectively a 16-bit store. */ tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUW); break; =20 case 0x8: @@ -4445,7 +4445,7 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps= *o) =20 while (1) { tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), - size =3D=3D 8 ? MO_TEUQ : MO_TEUL); + size =3D=3D 8 ? MO_BEUQ : MO_BEUL); if (r1 =3D=3D r3) { break; } @@ -4466,7 +4466,7 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOp= s *o) =20 while (1) { tcg_gen_shl_i64(t, regs[r1], t32); - tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_BEUL); if (r1 =3D=3D r3) { break; } @@ -4482,7 +4482,7 @@ static DisasJumpType op_stpq(DisasContext *s, DisasOp= s *o) =20 tcg_gen_concat_i64_i128(t16, o->out2, o->out); tcg_gen_qemu_st_i128(t16, o->in2, get_mem_index(s), - MO_TE | MO_128 | MO_ALIGN); + MO_BE | MO_128 | MO_ALIGN); return DISAS_NEXT; } =20 @@ -5284,49 +5284,49 @@ static void wout_m1_8(DisasContext *s, DisasOps *o) =20 static void wout_m1_16(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUW); } #define SPEC_wout_m1_16 0 =20 #ifndef CONFIG_USER_ONLY static void wout_m1_16a(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUW | MO_AL= IGN); + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUW | MO_AL= IGN); } #define SPEC_wout_m1_16a 0 #endif =20 static void wout_m1_32(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUL); } #define SPEC_wout_m1_32 0 =20 #ifndef CONFIG_USER_ONLY static void wout_m1_32a(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUL | MO_AL= IGN); + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUL | MO_AL= IGN); } #define SPEC_wout_m1_32a 0 #endif =20 static void wout_m1_64(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUQ); } #define SPEC_wout_m1_64 0 =20 #ifndef CONFIG_USER_ONLY static void wout_m1_64a(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ | MO_A= LIGN); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUQ | MO_A= LIGN); } #define SPEC_wout_m1_64a 0 #endif =20 static void wout_m2_32(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_BEUL); } #define SPEC_wout_m2_32 0 =20 @@ -5529,7 +5529,7 @@ static void in1_m1_16s(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESW); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESW); } #define SPEC_in1_m1_16s 0 =20 @@ -5537,7 +5537,7 @@ static void in1_m1_16u(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUW); } #define SPEC_in1_m1_16u 0 =20 @@ -5545,7 +5545,7 @@ static void in1_m1_32s(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESL); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESL); } #define SPEC_in1_m1_32s 0 =20 @@ -5553,7 +5553,7 @@ static void in1_m1_32u(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUL); } #define SPEC_in1_m1_32u 0 =20 @@ -5561,7 +5561,7 @@ static void in1_m1_64(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUQ); } #define SPEC_in1_m1_64 0 =20 @@ -5787,28 +5787,28 @@ static void in2_m2_8u(DisasContext *s, DisasOps *o) static void in2_m2_16s(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESW); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESW); } #define SPEC_in2_m2_16s 0 =20 static void in2_m2_16u(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUW); } #define SPEC_in2_m2_16u 0 =20 static void in2_m2_32s(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESL); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESL); } #define SPEC_in2_m2_32s 0 =20 static void in2_m2_32u(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUL); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL); } #define SPEC_in2_m2_32u 0 =20 @@ -5816,7 +5816,7 @@ static void in2_m2_32u(DisasContext *s, DisasOps *o) static void in2_m2_32ua(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_TEUL | MO_ALIG= N); + tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_BEUL | MO_ALIG= N); } #define SPEC_in2_m2_32ua 0 #endif @@ -5824,14 +5824,14 @@ static void in2_m2_32ua(DisasContext *s, DisasOps *= o) static void in2_m2_64(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUQ); } #define SPEC_in2_m2_64 0 =20 static void in2_m2_64w(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->in2, o->in2, 0); } #define SPEC_in2_m2_64w 0 @@ -5840,7 +5840,7 @@ static void in2_m2_64w(DisasContext *s, DisasOps *o) static void in2_m2_64a(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ | MO_ALI= GN); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUQ | MO_ALI= GN); } #define SPEC_in2_m2_64a 0 #endif @@ -5848,14 +5848,14 @@ static void in2_m2_64a(DisasContext *s, DisasOps *o) static void in2_mri2_16s(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TESW); + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_BESW); } #define SPEC_in2_mri2_16s 0 =20 static void in2_mri2_16u(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TEUW); + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_BEUW); } #define SPEC_in2_mri2_16u 0 =20 @@ -5863,7 +5863,7 @@ static void in2_mri2_32s(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), - MO_TESL | MO_ALIGN); + MO_BESL | MO_ALIGN); } #define SPEC_in2_mri2_32s 0 =20 @@ -5871,7 +5871,7 @@ static void in2_mri2_32u(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), - MO_TEUL | MO_ALIGN); + MO_BEUL | MO_ALIGN); } #define SPEC_in2_mri2_32u 0 =20 @@ -5879,7 +5879,7 @@ static void in2_mri2_64(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), - MO_TEUQ | MO_ALIGN); + MO_BEUQ | MO_ALIGN); } #define SPEC_in2_mri2_64 0 =20 diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/transla= te_vx.c.inc index f3b4b48ab7b..b53e9e52639 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -331,7 +331,7 @@ static DisasJumpType op_vge(DisasContext *s, DisasOps *= o) tcg_gen_add_i64(o->addr1, o->addr1, tmp); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); =20 - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); return DISAS_NEXT; } @@ -402,9 +402,9 @@ static DisasJumpType op_vl(DisasContext *s, DisasOps *o) TCGv_i64 t0 =3D tcg_temp_new_i64(); TCGv_i64 t1 =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); return DISAS_NEXT; @@ -427,7 +427,7 @@ static DisasJumpType op_vlrep(DisasContext *s, DisasOps= *o) } =20 tmp =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); gen_gvec_dup_i64(es, get_field(s, v1), tmp); return DISAS_NEXT; } @@ -561,7 +561,7 @@ static DisasJumpType op_vle(DisasContext *s, DisasOps *= o) } =20 tmp =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); return DISAS_NEXT; } @@ -595,9 +595,9 @@ static DisasJumpType op_vler(DisasContext *s, DisasOps = *o) TCGv_i64 t1 =3D tcg_temp_new_i64(); =20 /* Begin with the two doublewords swapped... */ - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_BEUQ); =20 /* ... then swap smaller elements within the doublewords as required. = */ switch (es) { @@ -693,7 +693,7 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps= *o) } =20 t =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_BE | es); gen_gvec_dup_imm(es, get_field(s, v1), 0); write_vec_element_i64(t, get_field(s, v1), enr, es); return DISAS_NEXT; @@ -717,16 +717,16 @@ static DisasJumpType op_vlm(DisasContext *s, DisasOps= *o) t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); gen_addi_and_wrap_i64(s, t0, o->addr1, (v3 - v1) * 16 + 8); - tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_BEUQ); =20 for (;; v1++) { - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); write_vec_element_i64(t1, v1, 0, ES_64); if (v1 =3D=3D v3) { break; } gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); write_vec_element_i64(t1, v1, 1, ES_64); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); } @@ -1009,7 +1009,7 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOp= s *o) gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0); =20 read_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); return DISAS_NEXT; } =20 @@ -1063,10 +1063,10 @@ static DisasJumpType op_vst(DisasContext *s, DisasO= ps *o) =20 tmp =3D tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); return DISAS_NEXT; } =20 @@ -1154,7 +1154,7 @@ static DisasJumpType op_vste(DisasContext *s, DisasOp= s *o) =20 tmp =3D tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BE | es); return DISAS_NEXT; } =20 @@ -1193,9 +1193,9 @@ static DisasJumpType op_vster(DisasContext *s, DisasO= ps *o) g_assert_not_reached(); } =20 - tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); - tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_BEUQ); return DISAS_NEXT; } =20 @@ -1217,10 +1217,10 @@ static DisasJumpType op_vstm(DisasContext *s, Disas= Ops *o) tmp =3D tcg_temp_new_i64(); for (;; v1++) { read_vec_element_i64(tmp, v1, 0, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); read_vec_element_i64(tmp, v1, 1, ES_64); - tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_BEUQ); if (v1 =3D=3D v3) { break; } --=20 2.52.0 From nobody Mon Feb 9 05:13:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/8] target/s390x: Inline cpu_ld{uw, l}_code() calls in EX opcode helper Date: Wed, 24 Dec 2025 17:20:32 +0100 Message-ID: <20251224162036.90404-6-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224162036.90404-1-philmd@linaro.org> References: <20251224162036.90404-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766593309451158500 In preparation of removing the cpu_lduw_code() and cpu_ldl_code() wrappers, inline them. Since S390x instructions are always stored in big-endian order, replace MO_TE -> MO_BE. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Farman Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 507eb7feac7..ce9ced8275f 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -2430,15 +2430,18 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t r= 1, uint64_t addr) */ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t a= ddr) { + CPUState *cs =3D env_cpu(env); uint64_t insn; uint8_t opc; + MemOpIdx oi; =20 /* EXECUTE targets must be at even addresses. */ if (addr & 1) { tcg_s390_program_interrupt(env, PGM_SPECIFICATION, GETPC()); } =20 - insn =3D cpu_lduw_code(env, addr); + oi =3D make_memop_idx(MO_BEUW, cpu_mmu_index(cs, true)); + insn =3D cpu_ldw_code_mmu(env, addr, oi, 0); opc =3D insn >> 8; =20 /* Or in the contents of R1[56:63]. */ @@ -2450,10 +2453,11 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, = uint64_t r1, uint64_t addr) case 2: break; case 4: - insn |=3D (uint64_t)cpu_lduw_code(env, addr + 2) << 32; + insn |=3D (uint64_t)cpu_ldw_code_mmu(env, addr + 2, oi, 0) << 32; break; case 6: - insn |=3D (uint64_t)(uint32_t)cpu_ldl_code(env, addr + 2) << 16; + oi =3D make_memop_idx(MO_BEUL, cpu_mmu_index(cs, true)); + insn |=3D (uint64_t)(uint32_t)cpu_ldl_code_mmu(env, addr + 2, oi, = 0) << 16; break; default: g_assert_not_reached(); --=20 2.52.0 From nobody Mon Feb 9 05:13:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1766593347; cv=none; d=zohomail.com; s=zohoarc; b=mxB06Xr+VJ9vkqAe8yJJLaqCx9QWE55FSX8BUHf1DDVbIMtqFZho6VOQpHV3NdrnF2eKUjBs8JYMlKhypgTkCIeaz7iJEUgifJVaengQwAASSBu3RVehg25H0HYQGmnme+i7f4CvHGv/zzCcTfU33blpRbf/m9yrev5SN+PwMJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766593347; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rc8PZ1471HKk1yGc0i0lwt+NI83rpaunL/zAVpAz/74=; b=lXSmf5GLaMgljxPrb0W6zj24DKekk9SBUYyhfcbhS34/pKuYd70rRKd3lZWNFdMNZjybxlZwE+fuoFxKf8CNfO2JBEyAQOZ5uQEEDDTteygH1VYXkmF6HUtEuRrsGgVqYrtLbWG9US8NLBiBxCS26+oFdVayPs9+DPCOyvr7jt8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176659334742235.98844970152959; Wed, 24 Dec 2025 08:22:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYRcm-0001t8-0w; Wed, 24 Dec 2025 11:22:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYRcL-0001hf-8E for qemu-devel@nongnu.org; Wed, 24 Dec 2025 11:21:43 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vYRcH-0002ky-Qk for qemu-devel@nongnu.org; Wed, 24 Dec 2025 11:21:39 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4779ce2a624so45137155e9.2 for ; Wed, 24 Dec 2025 08:21:37 -0800 (PST) Received: from localhost.localdomain (188.171.88.92.rev.sfr.net. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 6/8] target/s390x: Use big-endian variant of cpu_ld/st_data*() Date: Wed, 24 Dec 2025 17:20:33 +0100 Message-ID: <20251224162036.90404-7-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224162036.90404-1-philmd@linaro.org> References: <20251224162036.90404-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766593349755158501 We only build the S390x target using big endianness order, therefore the cpu_ld/st_data*() definitions expand to the big endian declarations. Use the explicit big-endian variants. Mechanical change running: $ tgt=3Ds390x; \ end=3Dbe; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Reviewed-by: Eric Farman Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 48 +++++++++++++++++------------------ target/s390x/tcg/vec_helper.c | 8 +++--- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index ce9ced8275f..8a7d78f9108 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -101,7 +101,7 @@ static inline uint64_t cpu_ldusize_data_ra(CPUS390XStat= e *env, uint64_t addr, case 1: return cpu_ldub_data_ra(env, addr, ra); case 2: - return cpu_lduw_data_ra(env, addr, ra); + return cpu_lduw_be_data_ra(env, addr, ra); default: abort(); } @@ -117,7 +117,7 @@ static inline void cpu_stsize_data_ra(CPUS390XState *en= v, uint64_t addr, cpu_stb_data_ra(env, addr, value, ra); break; case 2: - cpu_stw_data_ra(env, addr, value, ra); + cpu_stw_be_data_ra(env, addr, value, ra); break; default: abort(); @@ -865,7 +865,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) env->cc_op =3D 2; return; } - v =3D cpu_lduw_data_ra(env, str + len, ra); + v =3D cpu_lduw_be_data_ra(env, str + len, ra); if (v =3D=3D c) { /* Character found. Set R1 to the location; R2 is unmodified.= */ env->cc_op =3D 1; @@ -1023,7 +1023,7 @@ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uin= t64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - env->aregs[i] =3D cpu_ldl_data_ra(env, a2, ra); + env->aregs[i] =3D cpu_ldl_be_data_ra(env, a2, ra); a2 +=3D 4; =20 if (i =3D=3D r3) { @@ -1043,7 +1043,7 @@ void HELPER(stam)(CPUS390XState *env, uint32_t r1, ui= nt64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - cpu_stl_data_ra(env, a2, env->aregs[i], ra); + cpu_stl_be_data_ra(env, a2, env->aregs[i], ra); a2 +=3D 4; =20 if (i =3D=3D r3) { @@ -1364,7 +1364,7 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, =20 /* Process full words as available. */ for (len =3D 0; len + 4 <=3D max_len; len +=3D 4, src +=3D 4) { - cksm +=3D (uint32_t)cpu_ldl_data_ra(env, src, ra); + cksm +=3D (uint32_t)cpu_ldl_be_data_ra(env, src, ra); } =20 switch (max_len - len) { @@ -1373,11 +1373,11 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, len +=3D 1; break; case 2: - cksm +=3D cpu_lduw_data_ra(env, src, ra) << 16; + cksm +=3D cpu_lduw_be_data_ra(env, src, ra) << 16; len +=3D 2; break; case 3: - cksm +=3D cpu_lduw_data_ra(env, src, ra) << 16; + cksm +=3D cpu_lduw_be_data_ra(env, src, ra) << 16; cksm +=3D cpu_ldub_data_ra(env, src + 2, ra) << 8; len +=3D 3; break; @@ -1956,7 +1956,7 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - uint64_t val =3D cpu_ldq_data_ra(env, src, ra); + uint64_t val =3D cpu_ldq_be_data_ra(env, src, ra); if (env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { PERchanged =3D true; } @@ -1993,7 +1993,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, ui= nt64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - uint32_t val =3D cpu_ldl_data_ra(env, src, ra); + uint32_t val =3D cpu_ldl_be_data_ra(env, src, ra); uint64_t val64 =3D deposit64(env->cregs[i], 0, 32, val); if ((uint32_t)env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { PERchanged =3D true; @@ -2029,7 +2029,7 @@ void HELPER(stctg)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - cpu_stq_data_ra(env, dest, env->cregs[i], ra); + cpu_stq_be_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint64_t); =20 if (i =3D=3D r3) { @@ -2049,7 +2049,7 @@ void HELPER(stctl)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - cpu_stl_data_ra(env, dest, env->cregs[i], ra); + cpu_stl_be_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint32_t); =20 if (i =3D=3D r3) { @@ -2066,7 +2066,7 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64= _t real_addr) real_addr =3D wrap_address(env, real_addr) & TARGET_PAGE_MASK; =20 for (i =3D 0; i < TARGET_PAGE_SIZE; i +=3D 8) { - cpu_stq_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); } =20 return 0; @@ -2325,11 +2325,11 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, = uint64_t r2, uint32_t m4) for (i =3D 0; i < entries; i++) { /* addresses are not wrapped in 24/31bit mode but table index = is */ raddr =3D table + ((index + i) & 0x7ff) * sizeof(entry); - entry =3D cpu_ldq_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); + entry =3D cpu_ldq_be_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); if (!(entry & REGION_ENTRY_I)) { /* we are allowed to not store if already invalid */ entry |=3D REGION_ENTRY_I; - cpu_stq_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); } } } @@ -2356,9 +2356,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, u= int64_t vaddr, pte_addr +=3D VADDR_PAGE_TX(vaddr) * 8; =20 /* Mark the page table entry as invalid */ - pte =3D cpu_ldq_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); + pte =3D cpu_ldq_be_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); pte |=3D PAGE_ENTRY_I; - cpu_stq_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); =20 /* XXX we exploit the fact that Linux passes the exact virtual address here - it's not obliged to! */ @@ -2700,7 +2700,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 2) { return 0; } - s0 =3D cpu_lduw_data_ra(env, addr, ra); + s0 =3D cpu_lduw_be_data_ra(env, addr, ra); if ((s0 & 0xfc00) !=3D 0xd800) { /* one word character */ l =3D 2; @@ -2711,7 +2711,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 4) { return 0; } - s1 =3D cpu_lduw_data_ra(env, addr + 2, ra); + s1 =3D cpu_lduw_be_data_ra(env, addr + 2, ra); c =3D extract32(s0, 6, 4) + 1; c =3D (c << 6) | (s0 & 0x3f); c =3D (c << 10) | (s1 & 0x3ff); @@ -2735,7 +2735,7 @@ static int decode_utf32(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 4) { return 0; } - c =3D cpu_ldl_data_ra(env, addr, ra); + c =3D cpu_ldl_be_data_ra(env, addr, ra); if ((c >=3D 0xd800 && c <=3D 0xdbff) || c > 0x10ffff) { /* invalid unicode character */ return 2; @@ -2797,7 +2797,7 @@ static int encode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 2) { return 1; } - cpu_stw_data_ra(env, addr, c, ra); + cpu_stw_be_data_ra(env, addr, c, ra); *olen =3D 2; } else { /* two word character */ @@ -2807,8 +2807,8 @@ static int encode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, d1 =3D 0xdc00 | extract32(c, 0, 10); d0 =3D 0xd800 | extract32(c, 10, 6); d0 =3D deposit32(d0, 6, 4, extract32(c, 16, 5) - 1); - cpu_stw_data_ra(env, addr + 0, d0, ra); - cpu_stw_data_ra(env, addr + 2, d1, ra); + cpu_stw_be_data_ra(env, addr + 0, d0, ra); + cpu_stw_be_data_ra(env, addr + 2, d1, ra); *olen =3D 4; } =20 @@ -2821,7 +2821,7 @@ static int encode_utf32(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 4) { return 1; } - cpu_stl_data_ra(env, addr, c, ra); + cpu_stl_be_data_ra(env, addr, c, ra); *olen =3D 4; return -1; } diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c index 46ec4a947dd..304745c971b 100644 --- a/target/s390x/tcg/vec_helper.c +++ b/target/s390x/tcg/vec_helper.c @@ -45,9 +45,9 @@ void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t a= ddr, uint64_t bytes) if (likely(bytes >=3D 16)) { uint64_t t0, t1; =20 - t0 =3D cpu_ldq_data_ra(env, addr, GETPC()); + t0 =3D cpu_ldq_be_data_ra(env, addr, GETPC()); addr =3D wrap_address(env, addr + 8); - t1 =3D cpu_ldq_data_ra(env, addr, GETPC()); + t1 =3D cpu_ldq_be_data_ra(env, addr, GETPC()); s390_vec_write_element64(v1, 0, t0); s390_vec_write_element64(v1, 1, t1); } else { @@ -195,9 +195,9 @@ void HELPER(vstl)(CPUS390XState *env, const void *v1, u= int64_t addr, probe_write_access(env, addr, MIN(bytes, 16), GETPC()); =20 if (likely(bytes >=3D 16)) { - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC()= ); + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETP= C()); addr =3D wrap_address(env, addr + 8); - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC()= ); + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETP= C()); } else { int i; =20 --=20 2.52.0 From nobody Mon Feb 9 05:13:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 7/8] target/s390x: Inline translator_lduw() and translator_ldl() Date: Wed, 24 Dec 2025 17:20:34 +0100 Message-ID: <20251224162036.90404-8-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224162036.90404-1-philmd@linaro.org> References: <20251224162036.90404-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766593387861158500 translator_lduw() and translator_ldl() are defined in "exec/translator.h" as: 192 static inline uint16_t 193 translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc) 194 { 195 return translator_lduw_end(env, db, pc, MO_TE); 196 } 198 static inline uint32_t 199 translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc) 200 { 201 return translator_ldl_end(env, db, pc, MO_TE); 202 } Directly use the inlined form, expanding MO_TE -> MO_BE since we only build the S390x target as big-endian. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Farman Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index db2276f1cfc..e38607ee18c 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -365,13 +365,13 @@ static void update_cc_op(DisasContext *s) static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s, uint64_t pc) { - return (uint64_t)translator_lduw(env, &s->base, pc); + return (uint64_t) translator_lduw_end(env, &s->base, pc, MO_BE); } =20 static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s, uint64_t pc) { - return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc); + return (uint64_t)(uint32_t) translator_ldl_end(env, &s->base, pc, MO_B= E); } =20 static int get_mem_index(DisasContext *s) @@ -6408,7 +6408,7 @@ static void s390x_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) static target_ulong get_next_pc(CPUS390XState *env, DisasContext *s, uint64_t pc) { - uint64_t insn =3D translator_lduw(env, &s->base, pc); + uint64_t insn =3D translator_lduw_end(env, &s->base, pc, MO_BE); =20 return pc + get_ilen((insn >> 8) & 0xff); } --=20 2.52.0 From nobody Mon Feb 9 05:13:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1766593349; cv=none; d=zohomail.com; s=zohoarc; b=ZPjq1GtrQyr0PbaNg5ufQ8V4Fq3K6AaBu0L7anO6Kw/LnegIKIx5BXzeomSJGRRoEHVmS983A50ww59Hc1PP/uc2XdyvocCYDthlwQ6PrmDyHcXj/yEHnHGD1Zxz3OYsG50Xj/el7+6Z5LFbczd222spYuIpi0gLqswwVmsny78= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766593349; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ua60JEpQG58b3nrNlFkMCulo7Kh6kSjNov2Wuy5h9Qw=; b=H/OxB3QQ4/SQNzC7L72r4FxR2IciNDOt+41DqHH0xl/3Lb4VjOThf6bl0TSS3ey0BxQliJC3/zCYyyRa3Y8TEvr8WvZ5+7bwv8RjmU/3JTNpaHRqACVqH0UdlBzDAAzDwIoZLekPPKgnxaQg5tfrQ5C80b/QBXYIedMcLz2P1KY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766593349351807.7844795260863; Wed, 24 Dec 2025 08:22:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYRcq-0002Aj-9s; Wed, 24 Dec 2025 11:22:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYRcb-0001ps-Q0 for qemu-devel@nongnu.org; Wed, 24 Dec 2025 11:22:01 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vYRcZ-0002p5-M6 for qemu-devel@nongnu.org; Wed, 24 Dec 2025 11:21:56 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-477ba2c1ca2so61818235e9.2 for ; Wed, 24 Dec 2025 08:21:54 -0800 (PST) Received: from localhost.localdomain (188.171.88.92.rev.sfr.net. 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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 8/8] configs/targets: Forbid S390x to use legacy native endianness APIs Date: Wed, 24 Dec 2025 17:20:35 +0100 Message-ID: <20251224162036.90404-9-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224162036.90404-1-philmd@linaro.org> References: <20251224162036.90404-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766593349802158500 All S390x-related binaries are buildable without a single use of the legacy "native endian" API. Unset the transitional TARGET_USE_LEGACY_NATIVE_ENDIAN_API definition to forbid further uses of the legacy API. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Farman Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- configs/targets/s390x-linux-user.mak | 1 + configs/targets/s390x-softmmu.mak | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/targets/s390x-linux-user.mak b/configs/targets/s390x-l= inux-user.mak index 68c2f288724..e3723f5dc54 100644 --- a/configs/targets/s390x-linux-user.mak +++ b/configs/targets/s390x-linux-user.mak @@ -4,3 +4,4 @@ TARGET_SYSTBL=3Dsyscall.tbl TARGET_BIG_ENDIAN=3Dy TARGET_XML_FILES=3D gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/= s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml = gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=3D64 +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-soft= mmu.mak index 76dd5de6584..544657cfe2d 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -3,3 +3,4 @@ TARGET_BIG_ENDIAN=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/= s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml = gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=3D64 +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy --=20 2.52.0