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Use the latter which is more explicit. Mechanical change running: $ sed -i -e s/MO_TE/MO_LE/ \ $(git grep -wl MO_TE target/loongarch/) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- .../tcg/insn_trans/trans_atomic.c.inc | 80 +++++++++---------- .../tcg/insn_trans/trans_fmemory.c.inc | 32 ++++---- .../tcg/insn_trans/trans_memory.c.inc | 64 +++++++-------- .../loongarch/tcg/insn_trans/trans_vec.c.inc | 16 ++-- 4 files changed, 96 insertions(+), 96 deletions(-) diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/lo= ongarch/tcg/insn_trans/trans_atomic.c.inc index 77eeedbc42b..a1de389e51b 100644 --- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc @@ -69,43 +69,43 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a, return true; } =20 -TRANS(ll_w, ALL, gen_ll, MO_TESL) -TRANS(sc_w, ALL, gen_sc, MO_TESL) -TRANS(ll_d, 64, gen_ll, MO_TEUQ) -TRANS(sc_d, 64, gen_sc, MO_TEUQ) -TRANS(amswap_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL) -TRANS64(amswap_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) -TRANS(amadd_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL) -TRANS64(amadd_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) -TRANS(amand_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL) -TRANS64(amand_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) -TRANS(amor_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL) -TRANS64(amor_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) -TRANS(amxor_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL) -TRANS64(amxor_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) -TRANS(ammax_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL) -TRANS64(ammax_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) -TRANS(ammin_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL) -TRANS64(ammin_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) -TRANS(ammax_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL) -TRANS64(ammax_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) -TRANS(ammin_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL) -TRANS64(ammin_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) -TRANS(amswap_db_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL) -TRANS64(amswap_db_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) -TRANS(amadd_db_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL) -TRANS64(amadd_db_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) -TRANS(amand_db_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL) -TRANS64(amand_db_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) -TRANS(amor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL) -TRANS64(amor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) -TRANS(amxor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL) -TRANS64(amxor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) -TRANS(ammax_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL) -TRANS64(ammax_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) -TRANS(ammin_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL) -TRANS64(ammin_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) -TRANS(ammax_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL) -TRANS64(ammax_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) -TRANS(ammin_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL) -TRANS64(ammin_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) +TRANS(ll_w, ALL, gen_ll, MO_LESL) +TRANS(sc_w, ALL, gen_sc, MO_LESL) +TRANS(ll_d, 64, gen_ll, MO_LEUQ) +TRANS(sc_d, 64, gen_sc, MO_LEUQ) +TRANS(amswap_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_LESL) +TRANS64(amswap_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_LEUQ) +TRANS(amadd_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_LESL) +TRANS64(amadd_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_LEUQ) +TRANS(amand_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_LESL) +TRANS64(amand_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_LEUQ) +TRANS(amor_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_LESL) +TRANS64(amor_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_LEUQ) +TRANS(amxor_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_LESL) +TRANS64(amxor_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_LEUQ) +TRANS(ammax_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_LESL) +TRANS64(ammax_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_LEUQ) +TRANS(ammin_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_LESL) +TRANS64(ammin_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_LEUQ) +TRANS(ammax_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_LESL) +TRANS64(ammax_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_LEUQ) +TRANS(ammin_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_LESL) +TRANS64(ammin_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_LEUQ) +TRANS(amswap_db_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_LESL) +TRANS64(amswap_db_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_LEUQ) +TRANS(amadd_db_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_LESL) +TRANS64(amadd_db_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_LEUQ) +TRANS(amand_db_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_LESL) +TRANS64(amand_db_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_LEUQ) +TRANS(amor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_LESL) +TRANS64(amor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_LEUQ) +TRANS(amxor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_LESL) +TRANS64(amxor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_LEUQ) +TRANS(ammax_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_LESL) +TRANS64(ammax_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_LEUQ) +TRANS(ammin_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_LESL) +TRANS64(ammin_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_LEUQ) +TRANS(ammax_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_LESL) +TRANS64(ammax_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_LEUQ) +TRANS(ammin_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_LESL) +TRANS64(ammin_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_LEUQ) diff --git a/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc b/target/l= oongarch/tcg/insn_trans/trans_fmemory.c.inc index 79da4718a56..b863ba1dc21 100644 --- a/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc @@ -140,19 +140,19 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr = *a, MemOp mop) return true; } =20 -TRANS(fld_s, FP_SP, gen_fload_i, MO_TEUL) -TRANS(fst_s, FP_SP, gen_fstore_i, MO_TEUL) -TRANS(fld_d, FP_DP, gen_fload_i, MO_TEUQ) -TRANS(fst_d, FP_DP, gen_fstore_i, MO_TEUQ) -TRANS(fldx_s, FP_SP, gen_floadx, MO_TEUL) -TRANS(fldx_d, FP_DP, gen_floadx, MO_TEUQ) -TRANS(fstx_s, FP_SP, gen_fstorex, MO_TEUL) -TRANS(fstx_d, FP_DP, gen_fstorex, MO_TEUQ) -TRANS64(fldgt_s, FP_SP, gen_fload_gt, MO_TEUL) -TRANS64(fldgt_d, FP_DP, gen_fload_gt, MO_TEUQ) -TRANS64(fldle_s, FP_SP, gen_fload_le, MO_TEUL) -TRANS64(fldle_d, FP_DP, gen_fload_le, MO_TEUQ) -TRANS64(fstgt_s, FP_SP, gen_fstore_gt, MO_TEUL) -TRANS64(fstgt_d, FP_DP, gen_fstore_gt, MO_TEUQ) -TRANS64(fstle_s, FP_SP, gen_fstore_le, MO_TEUL) -TRANS64(fstle_d, FP_DP, gen_fstore_le, MO_TEUQ) +TRANS(fld_s, FP_SP, gen_fload_i, MO_LEUL) +TRANS(fst_s, FP_SP, gen_fstore_i, MO_LEUL) +TRANS(fld_d, FP_DP, gen_fload_i, MO_LEUQ) +TRANS(fst_d, FP_DP, gen_fstore_i, MO_LEUQ) +TRANS(fldx_s, FP_SP, gen_floadx, MO_LEUL) +TRANS(fldx_d, FP_DP, gen_floadx, MO_LEUQ) +TRANS(fstx_s, FP_SP, gen_fstorex, MO_LEUL) +TRANS(fstx_d, FP_DP, gen_fstorex, MO_LEUQ) +TRANS64(fldgt_s, FP_SP, gen_fload_gt, MO_LEUL) +TRANS64(fldgt_d, FP_DP, gen_fload_gt, MO_LEUQ) +TRANS64(fldle_s, FP_SP, gen_fload_le, MO_LEUL) +TRANS64(fldle_d, FP_DP, gen_fload_le, MO_LEUQ) +TRANS64(fstgt_s, FP_SP, gen_fstore_gt, MO_LEUL) +TRANS64(fstgt_d, FP_DP, gen_fstore_gt, MO_LEUQ) +TRANS64(fstle_s, FP_SP, gen_fstore_le, MO_LEUL) +TRANS64(fstle_d, FP_DP, gen_fstore_le, MO_LEUQ) diff --git a/target/loongarch/tcg/insn_trans/trans_memory.c.inc b/target/lo= ongarch/tcg/insn_trans/trans_memory.c.inc index 42f4e740126..90bb0815ff3 100644 --- a/target/loongarch/tcg/insn_trans/trans_memory.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_memory.c.inc @@ -151,44 +151,44 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a,= MemOp mop) } =20 TRANS(ld_b, ALL, gen_load, MO_SB) -TRANS(ld_h, ALL, gen_load, MO_TESW) -TRANS(ld_w, ALL, gen_load, MO_TESL) -TRANS(ld_d, 64, gen_load, MO_TEUQ) +TRANS(ld_h, ALL, gen_load, MO_LESW) +TRANS(ld_w, ALL, gen_load, MO_LESL) +TRANS(ld_d, 64, gen_load, MO_LEUQ) TRANS(st_b, ALL, gen_store, MO_UB) -TRANS(st_h, ALL, gen_store, MO_TEUW) -TRANS(st_w, ALL, gen_store, MO_TEUL) -TRANS(st_d, 64, gen_store, MO_TEUQ) +TRANS(st_h, ALL, gen_store, MO_LEUW) +TRANS(st_w, ALL, gen_store, MO_LEUL) +TRANS(st_d, 64, gen_store, MO_LEUQ) TRANS(ld_bu, ALL, gen_load, MO_UB) -TRANS(ld_hu, ALL, gen_load, MO_TEUW) -TRANS(ld_wu, 64, gen_load, MO_TEUL) +TRANS(ld_hu, ALL, gen_load, MO_LEUW) +TRANS(ld_wu, 64, gen_load, MO_LEUL) TRANS(ldx_b, 64, gen_loadx, MO_SB) -TRANS(ldx_h, 64, gen_loadx, MO_TESW) -TRANS(ldx_w, 64, gen_loadx, MO_TESL) -TRANS(ldx_d, 64, gen_loadx, MO_TEUQ) +TRANS(ldx_h, 64, gen_loadx, MO_LESW) +TRANS(ldx_w, 64, gen_loadx, MO_LESL) +TRANS(ldx_d, 64, gen_loadx, MO_LEUQ) TRANS(stx_b, 64, gen_storex, MO_UB) -TRANS(stx_h, 64, gen_storex, MO_TEUW) -TRANS(stx_w, 64, gen_storex, MO_TEUL) -TRANS(stx_d, 64, gen_storex, MO_TEUQ) +TRANS(stx_h, 64, gen_storex, MO_LEUW) +TRANS(stx_w, 64, gen_storex, MO_LEUL) +TRANS(stx_d, 64, gen_storex, MO_LEUQ) TRANS(ldx_bu, 64, gen_loadx, MO_UB) -TRANS(ldx_hu, 64, gen_loadx, MO_TEUW) -TRANS(ldx_wu, 64, gen_loadx, MO_TEUL) -TRANS(ldptr_w, 64, gen_ldptr, MO_TESL) -TRANS(stptr_w, 64, gen_stptr, MO_TEUL) -TRANS(ldptr_d, 64, gen_ldptr, MO_TEUQ) -TRANS(stptr_d, 64, gen_stptr, MO_TEUQ) +TRANS(ldx_hu, 64, gen_loadx, MO_LEUW) +TRANS(ldx_wu, 64, gen_loadx, MO_LEUL) +TRANS(ldptr_w, 64, gen_ldptr, MO_LESL) +TRANS(stptr_w, 64, gen_stptr, MO_LEUL) +TRANS(ldptr_d, 64, gen_ldptr, MO_LEUQ) +TRANS(stptr_d, 64, gen_stptr, MO_LEUQ) TRANS(ldgt_b, 64, gen_load_gt, MO_SB) -TRANS(ldgt_h, 64, gen_load_gt, MO_TESW) -TRANS(ldgt_w, 64, gen_load_gt, MO_TESL) -TRANS(ldgt_d, 64, gen_load_gt, MO_TEUQ) +TRANS(ldgt_h, 64, gen_load_gt, MO_LESW) +TRANS(ldgt_w, 64, gen_load_gt, MO_LESL) +TRANS(ldgt_d, 64, gen_load_gt, MO_LEUQ) TRANS(ldle_b, 64, gen_load_le, MO_SB) -TRANS(ldle_h, 64, gen_load_le, MO_TESW) -TRANS(ldle_w, 64, gen_load_le, MO_TESL) -TRANS(ldle_d, 64, gen_load_le, MO_TEUQ) +TRANS(ldle_h, 64, gen_load_le, MO_LESW) +TRANS(ldle_w, 64, gen_load_le, MO_LESL) +TRANS(ldle_d, 64, gen_load_le, MO_LEUQ) TRANS(stgt_b, 64, gen_store_gt, MO_UB) -TRANS(stgt_h, 64, gen_store_gt, MO_TEUW) -TRANS(stgt_w, 64, gen_store_gt, MO_TEUL) -TRANS(stgt_d, 64, gen_store_gt, MO_TEUQ) +TRANS(stgt_h, 64, gen_store_gt, MO_LEUW) +TRANS(stgt_w, 64, gen_store_gt, MO_LEUL) +TRANS(stgt_d, 64, gen_store_gt, MO_LEUQ) TRANS(stle_b, 64, gen_store_le, MO_UB) -TRANS(stle_h, 64, gen_store_le, MO_TEUW) -TRANS(stle_w, 64, gen_store_le, MO_TEUL) -TRANS(stle_d, 64, gen_store_le, MO_TEUQ) +TRANS(stle_h, 64, gen_store_le, MO_LEUW) +TRANS(stle_w, 64, gen_store_le, MO_LEUL) +TRANS(stle_d, 64, gen_store_le, MO_LEUQ) diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loong= arch/tcg/insn_trans/trans_vec.c.inc index 38bccf28386..ea7e705bab4 100644 --- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc @@ -5279,7 +5279,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a) =20 addr =3D make_address_i(ctx, addr, a->imm); =20 - tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); + tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_LE); tcg_gen_extr_i128_i64(rl, rh, val); set_vreg64(rh, a->vd, 1); set_vreg64(rl, a->vd, 0); @@ -5311,7 +5311,7 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a) get_vreg64(ah, a->vd, 1); get_vreg64(al, a->vd, 0); tcg_gen_concat_i64_i128(val, al, ah); - tcg_gen_qemu_st_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); + tcg_gen_qemu_st_i128(val, addr, ctx->mem_idx, MO_128 | MO_LE); =20 return true; } @@ -5337,7 +5337,7 @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *a) rh =3D tcg_temp_new_i64(); =20 addr =3D make_address_x(ctx, src1, src2); - tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); + tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_LE); tcg_gen_extr_i128_i64(rl, rh, val); set_vreg64(rh, a->vd, 1); set_vreg64(rl, a->vd, 0); @@ -5369,7 +5369,7 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a) get_vreg64(ah, a->vd, 1); get_vreg64(al, a->vd, 0); tcg_gen_concat_i64_i128(val, al, ah); - tcg_gen_qemu_st_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); + tcg_gen_qemu_st_i128(val, addr, ctx->mem_idx, MO_128 | MO_LE); =20 return true; } @@ -5478,12 +5478,12 @@ static void gen_xvld(DisasContext *ctx, int vreg, T= CGv addr) TCGv temp =3D tcg_temp_new(); TCGv dest =3D tcg_temp_new(); =20 - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEUQ); set_vreg64(dest, vreg, 0); =20 for (i =3D 1; i < 4; i++) { tcg_gen_addi_tl(temp, addr, 8 * i); - tcg_gen_qemu_ld_i64(dest, temp, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(dest, temp, ctx->mem_idx, MO_LEUQ); set_vreg64(dest, vreg, i); } } @@ -5495,12 +5495,12 @@ static void gen_xvst(DisasContext * ctx, int vreg, = TCGv addr) TCGv dest =3D tcg_temp_new(); =20 get_vreg64(dest, vreg, 0); - tcg_gen_qemu_st_i64(dest, addr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(dest, addr, ctx->mem_idx, MO_LEUQ); =20 for (i =3D 1; i < 4; i++) { tcg_gen_addi_tl(temp, addr, 8 * i); get_vreg64(dest, vreg, i); - tcg_gen_qemu_st_i64(dest, temp, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_i64(dest, temp, ctx->mem_idx, MO_LEUQ); } } =20 --=20 2.52.0