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Tsirkin" , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pierrick Bouvier , Brian Cain , Manos Pitsidianakis , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 2/8] hw/net/opencores: Clarify MMIO read/write handlers expect 32-bit access Date: Wed, 24 Dec 2025 14:46:38 +0100 Message-ID: <20251224134644.85582-3-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224134644.85582-1-philmd@linaro.org> References: <20251224134644.85582-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=philmd@linaro.org; helo=mail-wm1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766584204986158500 The read/write handlers access array of 32-bit register by index: 277 struct OpenEthState { .. 287 uint32_t regs[REG_MAX]; .. 291 }; 546 static uint64_t open_eth_reg_read(void *opaque, 547 hwaddr addr, unsigned int size) 548 { .. 551 OpenEthState *s =3D opaque; 552 unsigned idx =3D addr / 4; .. 559 v =3D s->regs[idx]; .. 563 return v; 564 } This is a 32-bit implementation. Make that explicit in the MemoryRegionOps structure (this doesn't change the maximum access size, which -- being unset -- is 64-bit). Move the structure just after the handlers to ease code review. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/net/opencores_eth.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/net/opencores_eth.c b/hw/net/opencores_eth.c index 7e955c01322..bc4565a9a49 100644 --- a/hw/net/opencores_eth.c +++ b/hw/net/opencores_eth.c @@ -682,6 +682,15 @@ static void open_eth_reg_write(void *opaque, } } =20 +static const MemoryRegionOps open_eth_reg_ops =3D { + .read =3D open_eth_reg_read, + .write =3D open_eth_reg_write, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + static uint64_t open_eth_desc_read(void *opaque, hwaddr addr, unsigned int size) { @@ -705,12 +714,6 @@ static void open_eth_desc_write(void *opaque, open_eth_check_start_xmit(s); } =20 - -static const MemoryRegionOps open_eth_reg_ops =3D { - .read =3D open_eth_reg_read, - .write =3D open_eth_reg_write, -}; - static const MemoryRegionOps open_eth_desc_ops =3D { .read =3D open_eth_desc_read, .write =3D open_eth_desc_write, --=20 2.52.0