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Tue, 23 Dec 2025 23:43:48 -0800 (PST) From: Jerry Zhang Jian To: alistair.francis@wdc.com, palmer@dabbelt.com, paul.walmsley@sifive.com, frank.chang@sifive.com, max.chou@sifve.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jerry Zhang Jian Subject: [PATCH] target/riscv: Add data type views for vector registers in GDB Date: Tue, 23 Dec 2025 23:43:35 -0800 Message-ID: <20251224074335.571933-1-jerry.zhangjian@sifive.com> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=jerry.zhangjian@sifive.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1766562295755158500 Content-Type: text/plain; charset="utf-8" Enhance the RISC-V GDB stub to support viewing vector registers in multiple data type formats. This allows GDB users to inspect vector register contents as different element types. New type views using GDB builtin type names: - Integer types: uint8, int8, uint16, int16, uint32, int32, uint64, int64, uint128, int128 - Float types (conditionally enabled based on extensions): - fp64 (Zve64d) - fp32 (Zve32f) - fp16 (Zvfhmin) - bf16 (Zvfbfmin) Backward-compatible aliases are preserved: - b, s, w, l, q Example GDB usage: (gdb) print $v0.uint32 (gdb) print $v0.f32 (gdb) print $v0.w Signed-off-by: Jerry Zhang Jian Reviewed-by: Daniel Henrique Barboza --- target/riscv/gdbstub.c | 120 +++++++++++++++++++++++++++++++---------- 1 file changed, 92 insertions(+), 28 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1934f919c0..89a3700508 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -21,30 +21,24 @@ #include "gdbstub/helpers.h" #include "cpu.h" =20 -struct TypeSize { - const char *gdb_type; - const char *id; - int size; - const char suffix; +/* + * Vector lane type definitions for GDB target description. + * Uses GDB's builtin type names (uint8, int8, ieee_half, etc.) + */ +enum RVVExtension { + RVV_EXT_NONE =3D 0, /* Zve32x (checked at call site) */ + RVV_EXT_ZVE64X, /* 64-bit integer elements */ + RVV_EXT_ZVE64D, /* Double-precision float */ + RVV_EXT_ZVE32F, /* Single-precision float */ + RVV_EXT_ZVFHMIN, /* Half-precision float */ + RVV_EXT_ZVFBFMIN, /* BFloat16 */ }; =20 -static const struct TypeSize vec_lanes[] =3D { - /* quads */ - { "uint128", "quads", 128, 'q' }, - /* 64 bit */ - { "uint64", "longs", 64, 'l' }, - /* 32 bit */ - { "uint32", "words", 32, 'w' }, - /* 16 bit */ - { "uint16", "shorts", 16, 's' }, - /* - * TODO: currently there is no reliable way of telling - * if the remote gdb actually understands ieee_half so - * we don't expose it in the target description for now. - * { "ieee_half", 16, 'h', 'f' }, - */ - /* bytes */ - { "uint8", "bytes", 8, 'b' }, +struct TypeSize { + const char *gdb_type; /* GDB builtin type name */ + const char *name; /* Short name for union field (NULL =3D u= se gdb_type) */ + int size; /* Element size in bits */ + enum RVVExtension required; /* Required extension, RVV_EXT_NONE if al= ways enabled */ }; =20 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) @@ -300,6 +294,53 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUSt= ate *cs, int base_reg) return &cpu->dyn_csr_feature; } =20 +/* + * Vector lane types using GDB's builtin type names. + * Float types are conditionally included based on extension availability. + */ +static const struct TypeSize vec_lanes[] =3D { + /* 128 bit - requires Zve64x */ + { "uint128", NULL, 128, RVV_EXT_ZVE64X }, + { "int128", NULL, 128, RVV_EXT_ZVE64X }, + /* 64 bit - requires Zve64x */ + { "uint64", NULL, 64, RVV_EXT_ZVE64X }, + { "int64", NULL, 64, RVV_EXT_ZVE64X }, + { "ieee_double", "fp64", 64, RVV_EXT_ZVE64D }, + /* 32 bit */ + { "uint32", NULL, 32, RVV_EXT_NONE }, + { "int32", NULL, 32, RVV_EXT_NONE }, + { "ieee_single", "fp32", 32, RVV_EXT_ZVE32F }, + /* 16 bit */ + { "uint16", NULL, 16, RVV_EXT_NONE }, + { "int16", NULL, 16, RVV_EXT_NONE }, + { "ieee_half", "fp16", 16, RVV_EXT_ZVFHMIN }, + { "bfloat16", "bf16", 16, RVV_EXT_ZVFBFMIN }, + /* 8 bit */ + { "uint8", NULL, 8, RVV_EXT_NONE }, + { "int8", NULL, 8, RVV_EXT_NONE }, +}; + +/* Check if a vector lane type should be included based on CPU extensions = */ +static bool riscv_gdb_vec_lane_enabled(RISCVCPU *cpu, const struct TypeSiz= e *ts) +{ + switch (ts->required) { + case RVV_EXT_NONE: + return true; + case RVV_EXT_ZVE64X: + return cpu->cfg.ext_zve64x; + case RVV_EXT_ZVE64D: + return cpu->cfg.ext_zve64d; + case RVV_EXT_ZVE32F: + return cpu->cfg.ext_zve32f; + case RVV_EXT_ZVFHMIN: + return cpu->cfg.ext_zvfhmin; + case RVV_EXT_ZVFBFMIN: + return cpu->cfg.ext_zvfbfmin; + default: + return false; + } +} + static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base= _reg) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -311,21 +352,44 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(C= PUState *cs, int base_reg) "org.gnu.gdb.riscv.vector", "riscv-vector.xml= ", base_reg); =20 - /* First define types and totals in a whole VL */ + /* Define vector types for each lane type */ for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { - int count =3D bitsize / vec_lanes[i].size; + const struct TypeSize *ts =3D &vec_lanes[i]; + if (!riscv_gdb_vec_lane_enabled(cpu, ts)) { + continue; + } gdb_feature_builder_append_tag( &builder, "", - vec_lanes[i].id, vec_lanes[i].gdb_type, count); + ts->gdb_type, ts->gdb_type, bitsize / ts->size); } =20 - /* Define unions */ + /* Create a single flat union with all type views */ gdb_feature_builder_append_tag(&builder, ""); for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { + const struct TypeSize *ts =3D &vec_lanes[i]; + const char *name =3D ts->name ? ts->name : ts->gdb_type; + if (!riscv_gdb_vec_lane_enabled(cpu, ts)) { + continue; + } gdb_feature_builder_append_tag(&builder, - "", - vec_lanes[i].suffix, vec_lanes[i].i= d); + "", + name, ts->gdb_type); } + + /* Add backward-compatible aliases for unsigned types */ + gdb_feature_builder_append_tag(&builder, + "= "); + gdb_feature_builder_append_tag(&builder, + ""); + gdb_feature_builder_append_tag(&builder, + ""); + if (cpu->cfg.ext_zve64x) { + gdb_feature_builder_append_tag(&builder, + ""); + gdb_feature_builder_append_tag(&builder, + ""); + } + gdb_feature_builder_append_tag(&builder, ""); =20 /* Define vector registers */ --=20 2.51.0