From nobody Tue Feb 10 13:36:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766548057797306.82590859538413; Tue, 23 Dec 2025 19:47:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYFqP-0008Qg-R4; Tue, 23 Dec 2025 22:47:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYFqO-0008Q6-Ki; Tue, 23 Dec 2025 22:47:24 -0500 Received: from zg8tmtyylji0my4xnjqumte4.icoremail.net ([162.243.164.118]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYFqL-0007tI-To; Tue, 23 Dec 2025 22:47:24 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwAnCCVFYktpnDURAg--.195S2; Wed, 24 Dec 2025 11:47:17 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwAXce4yYktpv0wOAA--.32229S10; Wed, 24 Dec 2025 11:47:13 +0800 (CST) From: Tao Tang To: Paolo Bonzini , Fabiano Rosas , Laurent Vivier , Eric Auger , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh , CLEMENT MATHIEU--DRIF , Tao Tang Subject: [RFC v8 7/7] tests/qtest: Add SMMUv3 bare-metal test using iommu-testdev Date: Wed, 24 Dec 2025 11:46:47 +0800 Message-Id: <20251224034647.2596434-8-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251224034647.2596434-1-tangtao1634@phytium.com.cn> References: <20251224034647.2596434-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwAXce4yYktpv0wOAA--.32229S10 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQAOBWlK96sBrQABsY Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoW3Jw1DCF13JF4rCw47Jr17Awb_yoW7Ar4xpF yDCa42kFW8Jr1fC3Z3Ga1vkr13tan3Aw15Gry7Grna9r4qy347trs7KFy7K3s7J3ykXF1U Za4vyFW5Gr18JaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=162.243.164.118; envelope-from=tangtao1634@phytium.com.cn; helo=zg8tmtyylji0my4xnjqumte4.icoremail.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766548061185158500 Content-Type: text/plain; charset="utf-8" Add a qtest suite that validates ARM SMMUv3 translation without guest firmware or OS. The tests leverage iommu-testdev to trigger DMA operations and the qos-smmuv3 library to configure IOMMU translation structures. This test suite targets the virt machine and covers: - Stage 1 only translation (VA -> PA via CD page tables) - Stage 2 only translation (IPA -> PA via STE S2 tables) - Nested translation (VA -> IPA -> PA, Stage 1 + Stage 2) - Design to extended to support multiple security spaces (Non-Secure, Secure, Root, Realm) Each test case follows this sequence: 1. Initialize SMMUv3 with appropriate command/event queues 2. Build translation tables (STE/CD/PTE) for the target scenario 3. Configure iommu-testdev with IOVA and DMA attributes via MMIO 4. Trigger DMA and validate successful translation 5. Verify data integrity through a deterministic write-read pattern This bare-metal approach provides deterministic IOMMU testing with minimal dependencies, making failures directly attributable to the SMMU translation path. Signed-off-by: Tao Tang Tested-by: Pierrick Bouvier Reviewed-by: Pierrick Bouvier Reviewed-by: Fabiano Rosas --- tests/qtest/iommu-smmuv3-test.c | 121 ++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 122 insertions(+) create mode 100644 tests/qtest/iommu-smmuv3-test.c diff --git a/tests/qtest/iommu-smmuv3-test.c b/tests/qtest/iommu-smmuv3-tes= t.c new file mode 100644 index 0000000000..b612f5ca6c --- /dev/null +++ b/tests/qtest/iommu-smmuv3-test.c @@ -0,0 +1,121 @@ +/* + * QTest for SMMUv3 with iommu-testdev + * + * This QTest file is used to test the SMMUv3 with iommu-testdev so that w= e can + * test SMMUv3 without any guest kernel or firmware. + * + * Copyright (c) 2025 Phytium Technology + * + * Author: + * Tao Tang + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqos/pci.h" +#include "libqos/generic-pcihost.h" +#include "hw/pci/pci_regs.h" +#include "hw/misc/iommu-testdev.h" +#include "libqos/qos-smmuv3.h" + +#define DMA_LEN 4 + +static void save_fn(QPCIDevice *dev, int devfn, void *data) +{ + QPCIDevice **pdev =3D (QPCIDevice **) data; + + *pdev =3D dev; +} + +static QPCIDevice *setup_qtest_pci_device(QTestState *qts, QGenericPCIBus = *gbus, + QPCIBar *bar) +{ + QPCIDevice *dev =3D NULL; + + qpci_init_generic(gbus, qts, NULL, false); + + qpci_device_foreach(&gbus->bus, IOMMU_TESTDEV_VENDOR_ID, + IOMMU_TESTDEV_DEVICE_ID, save_fn, &dev); + g_assert(dev); + + qpci_device_enable(dev); + *bar =3D qpci_iomap(dev, 0, NULL); + g_assert_false(bar->is_io); + + return dev; +} + +static void run_smmuv3_translation(const QSMMUTestConfig *cfg) +{ + QTestState *qts; + QGenericPCIBus gbus; + QPCIDevice *dev; + QPCIBar bar; + + /* Initialize QEMU environment for SMMU testing */ + qts =3D qtest_init("-machine virt,acpi=3Doff,gic-version=3D3,iommu=3Ds= mmuv3 " + "-smp 1 -m 512 -cpu max -net none " + "-device iommu-testdev"); + + /* Setup and configure PCI device */ + dev =3D setup_qtest_pci_device(qts, &gbus, &bar); + g_assert(dev); + + g_test_message("### SMMUv3 translation mode=3D%d sec_sid=3D%d ###", + cfg->trans_mode, cfg->sec_sid); + qsmmu_run_translation_case(qts, dev, bar, VIRT_SMMU_BASE, cfg); + qtest_quit(qts); +} + +static void test_smmuv3_ns_s1_only(void) +{ + QSMMUTestConfig cfg =3D { + .trans_mode =3D QSMMU_TM_S1_ONLY, + .sec_sid =3D QSMMU_SEC_SID_NONSECURE, + .dma_iova =3D QSMMU_IOVA, + .dma_len =3D DMA_LEN, + .expected_result =3D 0, + }; + + run_smmuv3_translation(&cfg); +} + +static void test_smmuv3_ns_s2_only(void) +{ + QSMMUTestConfig cfg =3D { + .trans_mode =3D QSMMU_TM_S2_ONLY, + .sec_sid =3D QSMMU_SEC_SID_NONSECURE, + .dma_iova =3D QSMMU_IOVA, + .dma_len =3D DMA_LEN, + .expected_result =3D 0, + }; + + run_smmuv3_translation(&cfg); +} + +static void test_smmuv3_ns_nested(void) +{ + QSMMUTestConfig cfg =3D { + .trans_mode =3D QSMMU_TM_NESTED, + .sec_sid =3D QSMMU_SEC_SID_NONSECURE, + .dma_iova =3D QSMMU_IOVA, + .dma_len =3D DMA_LEN, + .expected_result =3D 0, + }; + + run_smmuv3_translation(&cfg); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_func("/iommu-testdev/translation/ns-s1-only", + test_smmuv3_ns_s1_only); + qtest_add_func("/iommu-testdev/translation/ns-s2-only", + test_smmuv3_ns_s2_only); + qtest_add_func("/iommu-testdev/translation/ns-nested", + test_smmuv3_ns_nested); + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 669d07c06b..e2d2e68092 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -263,6 +263,7 @@ qtests_aarch64 =3D \ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test']= : []) + \ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : [])= + \ (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \ + (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') ? ['iommu-smmuv3-tes= t'] : []) + \ qtests_cxl + = \ ['arm-cpu-features', 'numa-test', --=20 2.34.1