From nobody Sun Feb 8 22:00:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540673; cv=none; d=zohomail.com; s=zohoarc; b=FcSeREI7GsRZE76f0SyHF2pCi9DUiabdjthgTQnnnXxHM4KMqU8BvvlfKST9/rAJ0EW1l9rC07sQ4w90NGKzUntp56XuXKnHLng1N3yNArZTpfmuJ3rvV7xf4eB5Nsy4yBdzaC/zQhR4hoZ1t3gfrWlluw8dED9F22eaH9R4w/8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766540673; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Q0up899WGSO7MwCMipoPHVXzbA1UBd5fQcgGlbARuYo=; b=E7gp5wUnMdv1Y3+b92cswZgdBPhWu1bc5QewtLfbRxEKEoDwNzflH6MjNJOcroKiDAzerS1o7eXoxfUawl6RfXXJNCdRKWEkMZb8+cp77mtJLrZU8xMzkYlEyUSfMFK/3mdev4rTDLmUs3AcsNYATOFDXGg8+f/Q7rAJZLwnE5s= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176654067360813.528598384416227; Tue, 23 Dec 2025 17:44:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYDug-00021K-0m; Tue, 23 Dec 2025 20:43:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDua-0001zE-C5; Tue, 23 Dec 2025 20:43:36 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDuY-00058k-Iz; Tue, 23 Dec 2025 20:43:36 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:09 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS Subject: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model Date: Wed, 24 Dec 2025 09:41:53 +0800 Message-ID: <20251224014203.756264-15-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540674851158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the I2C controller to the AST1700 model by mapping its MMIO region and wiring its interrupt line. This patch also adds a bus_label property to distinguish I2C buses on the BMC from those on external boards. This prevents user-specified I2C devices from being attached to the wrong bus when provided via CLI. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_ast1700.h | 2 ++ include/hw/arm/aspeed_soc.h | 2 ++ include/hw/i2c/aspeed_i2c.h | 1 + hw/arm/aspeed_ast1700.c | 18 ++++++++++++ hw/arm/aspeed_ast27x0.c | 51 +++++++++++++++++++++++++++++++-- hw/i2c/aspeed_i2c.c | 19 ++++++++++-- 6 files changed, 88 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 7ea6ff4c1a..d4b7abee7d 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -12,6 +12,7 @@ #include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" #include "hw/gpio/aspeed_gpio.h" +#include "hw/i2c/aspeed_i2c.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" #include "hw/char/serial-mm.h" @@ -34,6 +35,7 @@ struct AspeedAST1700SoCState { AspeedADCState adc; AspeedSCUState scu; AspeedGPIOState gpio; + AspeedI2CState i2c; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index b051d0eb3a..4ea2521041 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -290,6 +290,8 @@ enum { ASPEED_DEV_LTPI_CTRL2, ASPEED_DEV_LTPI_IO0, ASPEED_DEV_LTPI_IO1, + ASPEED_DEV_IOEXP0_I2C, + ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, }; diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 2daacc10ce..babbad5ed9 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -269,6 +269,7 @@ struct AspeedI2CState { uint32_t intr_status; uint32_t ctrl_global; uint32_t new_clk_divider; + char *bus_label; MemoryRegion pool_iomem; uint8_t share_pool[ASPEED_I2C_SHARE_POOL_SIZE]; =20 diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 9a6019908e..fad3b86e8d 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -22,6 +22,7 @@ enum { ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_GPIO, + ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -33,6 +34,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, + [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -108,6 +110,18 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0= )); =20 + /* I2C */ + snprintf(dev_name, sizeof(dev_name), "ioexp%d", s->board_idx); + qdev_prop_set_string(DEVICE(&s->i2c), "bus-label", dev_name); + object_property_set_link(OBJECT(&s->i2c), "dram", + OBJECT(&s->iomem), errp); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -141,6 +155,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio, "aspeed.gpio-ast2700"); =20 + /* I2C */ + object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c, + "aspeed.i2c-ast2700"); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index d998326536..ca3adf9a50 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -205,6 +205,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_ETH3] =3D 196, [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, + [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP1_I2C] =3D 200, }; =20 /* GICINT 128 */ @@ -267,6 +269,18 @@ static const int ast2700_gic133_gic197_intcmap[] =3D { [ASPEED_DEV_PECI] =3D 4, }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GICINT 198 */ +static const int ast2700_gic198_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ +}; + +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 200 */ +static const int ast2700_gic200_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ +}; + /* GICINT 128 ~ 136 */ /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { @@ -283,9 +297,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcm= ap[] =3D { {195, 1, 3, ast2700_gic131_gic195_intcmap}, {196, 1, 4, ast2700_gic132_gic196_intcmap}, {197, 1, 5, ast2700_gic133_gic197_intcmap}, - {198, 1, 6, NULL}, + {198, 2, 0, ast2700_gic198_intcmap}, {199, 1, 7, NULL}, - {200, 1, 8, NULL}, + {200, 3, 0, ast2700_gic200_intcmap}, {201, 1, 9, NULL}, {128, 0, 1, ast2700_gic128_gic192_intcmap}, {129, 0, 2, NULL}, @@ -327,14 +341,23 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(Aspe= edSoCState *s, int dev, int or_idx; int idx; int i; + OrIRQState *porgates; =20 for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) { assert(ast2700_gic_intcmap[i].ptr); or_idx =3D ast2700_gic_intcmap[i].orgate_idx; idx =3D ast2700_gic_intcmap[i].intc_idx; - return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), + if (idx < ASPEED_INTC_NUM) { + porgates =3D &a->intc[idx].orgates[or_idx]; + return qdev_get_gpio_in(DEVICE(porgates), + ast2700_gic_intcmap[i].ptr[dev] + inde= x); + } else { + idx -=3D ASPEED_INTC_NUM; + porgates =3D &a->intcioexp[idx].orgates[or_idx]; + return qdev_get_gpio_in(DEVICE(porgates), ast2700_gic_intcmap[i].ptr[dev] + inde= x); + } } } =20 @@ -1098,6 +1121,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) =20 /* IO Expander */ for (i =3D 0; i < sc->ioexp_num; i++) { + AspeedI2CClass *i2c_ctl; + qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { return; @@ -1128,6 +1153,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); =20 + /* I2C */ + i2c_ctl =3D ASPEED_I2C_GET_CLASS(&s->ioexp[i].i2c); + for (int j =3D 0; j < i2c_ctl->num_busses; j++) { + /* + * For I2C on AST1700: + * I2C bus interrupts are connected to the OR gate from bit 0 = to bit + * 15, and the OR gate output pin is connected to the input pi= n of + * GICINT192 of IO expander Interrupt controller (INTC2/3). Th= en, + * the output pin is connected to the INTC (CPU Die) input pin= , and + * its output pin is connected to the GIC. + * + * I2C bus 0 is connected to the OR gate at bit 0. + * I2C bus 15 is connected to the OR gate at bit 15. + */ + irq =3D aspeed_soc_ast2700_get_irq_index(s, + ASPEED_DEV_IOEXP0_I2C += i, + j); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].i2c.busses[j]), + 0, irq); + } } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 83fb906bdc..ca84068bb4 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -1261,6 +1261,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Erro= r **errp) static const Property aspeed_i2c_properties[] =3D { DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_STRING("bus-label", AspeedI2CState, bus_label), }; =20 static void aspeed_i2c_class_init(ObjectClass *klass, const void *data) @@ -1421,14 +1422,28 @@ static void aspeed_i2c_bus_realize(DeviceState *dev= , Error **errp) { AspeedI2CBus *s =3D ASPEED_I2C_BUS(dev); AspeedI2CClass *aic; - g_autofree char *name =3D g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s= ->id); - g_autofree char *pool_name =3D g_strdup_printf("%s.pool", name); + g_autofree char *name =3D NULL; + g_autofree char *pool_name =3D NULL; =20 if (!s->controller) { error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set"= ); return; } =20 + /* + * I2C bus naming: + * - Empty bus_label -> BMC internal controller, use default name. + * - Non-empty bus_label -> external/addon controller, prefix with l= abel + * to avoid conflicts and show bus origin. + */ + if (!s->controller->bus_label || (strlen(s->controller->bus_label) =3D= =3D 0)) { + name =3D g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id); + } else { + name =3D g_strdup_printf("aspeed.%s.i2c.bus.%d", + s->controller->bus_label, s->id); + } + pool_name =3D g_strdup_printf("%s.pool", name); + aic =3D ASPEED_I2C_GET_CLASS(s->controller); =20 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); --=20 2.43.0