From nobody Sun Feb 8 21:21:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540714; cv=none; d=zohomail.com; s=zohoarc; b=eK5MSdM6NtJk34FpzWo3t8YY/0lcO3MhEzaBars1bjpwepXhEx8fLZwLFgkvtpLRqGZiCUV1ne7qFL2eTdcdypz1aCj2uhMTtVrTZJzb+26cEKc+/8K4D+U9RI8sPSIcZtol5Ztxb2439YrBUhPrpCBCWOMBONzUevujxr9rNso= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766540714; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=YTJUOpF4zpsGy6QbI1isx7Z/aWNZ+RbUOyqlthO5gCs=; b=amR+6GM3BwEfuz6e8RI8xH14m/aCwFs5oHpnLFvZ3K6/6ei6H3gFuWHVcC02Ou8s5CYMAC63kDtP4Vt6Zi0v7WvXLqmEJZhZkr38IMmTLcpXOYtqCGJU2XfvXPFq40dYbCSzlHXpCzRnZhx+gt8yPp+huRWLCIt6SHzeKtWx+vw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766540714862616.2683784255092; Tue, 23 Dec 2025 17:45:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYDuI-0001jB-IA; Tue, 23 Dec 2025 20:43:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDuB-0001YC-3I; Tue, 23 Dec 2025 20:43:12 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDu9-00058k-KR; Tue, 23 Dec 2025 20:43:10 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:09 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 12/19] hw/arm/aspeed: Attach SCU device to AST1700 model Date: Wed, 24 Dec 2025 09:41:51 +0800 Message-ID: <20251224014203.756264-13-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540716439158500 From: Kane-Chen-AS Connect the SCU device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 3 +++ hw/arm/aspeed_ast1700.c | 17 +++++++++++++++++ hw/arm/aspeed_ast27x0.c | 2 ++ 3 files changed, 22 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 0c1216c4ba..12c57145c6 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -9,6 +9,7 @@ #define ASPEED_AST1700_H =20 #include "hw/sysbus.h" +#include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" @@ -23,12 +24,14 @@ struct AspeedAST1700SoCState { =20 MemoryRegion iomem; uint8_t board_idx; + uint32_t silicon_rev; =20 AspeedLTPIState ltpi; SerialMM uart; MemoryRegion sram; AspeedSMCState spi; AspeedADCState adc; + AspeedSCUState scu; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index e4d206045f..6494a5c4eb 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -20,6 +20,7 @@ enum { ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, + ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -29,6 +30,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, + [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -86,6 +88,16 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0)= ); =20 + /* SCU */ + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", + s->silicon_rev); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -111,6 +123,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-adc[*]", &s->adc, "aspeed.adc-ast2700"); =20 + /* SCU */ + object_initialize_child(obj, "ioexp-scu[*]", &s->scu, + TYPE_ASPEED_2700_SCU); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); @@ -120,6 +136,7 @@ static void aspeed_ast1700_instance_init(Object *obj) =20 static const Property aspeed_ast1700_props[] =3D { DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0), + DEFINE_PROP_UINT32("silicon-rev", AspeedAST1700SoCState, silicon_rev, = 0), }; =20 static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 84ff8b5557..6b9ad328dc 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -573,6 +573,8 @@ static void aspeed_soc_ast2700_init(Object *obj) /* AST1700 IOEXP */ object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], TYPE_ASPEED_AST1700); + qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev", + sc->silicon_rev); } =20 object_initialize_child(obj, "dpmcu", &s->dpmcu, --=20 2.43.0