From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540699; cv=none; d=zohomail.com; s=zohoarc; b=lqM/cr2FVdjOJ/Wo5m3GEs8epeStz0tPVEJ43Dqm17vaKUWd1cwdfLSthb2wZ0M+INBpectVtVvzOg50UepyB2W9jrp20m9x0xpVVtXn6Iur9k5YQChF87WPQHtVh25r+qgh4MfvpipHNlUcbtdeh9XVIoW6W3+gF0HcBsm6qZY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766540699; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Fha5DwQEwPNhyNfrYOERy7AVAu2JkYEtMqGKAtZjwWo=; b=H+XrsTET5idTw3yhHuGd7FnmfaLtiDMNgbvGA/8foUv8Ns9HGrrhJzfAfqYggyoi30LbkL01+rOnC41Az1zrRbC9rl+5gjCjvAY5wtLaUZwV/86TA6ht6/jG0CO117GBy4vcTSkVZgBnPBYxAPREj2IsMppWsZ2wKfMLNqLCTXE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766540699712829.8551427889292; Tue, 23 Dec 2025 17:44:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYDtm-0001H2-Q2; Tue, 23 Dec 2025 20:42:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDtb-0001Es-Nr; Tue, 23 Dec 2025 20:42:37 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDtZ-00058k-Ue; Tue, 23 Dec 2025 20:42:35 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS Subject: [PATCH v4 01/19] hw/misc: Add LTPI controller Date: Wed, 24 Dec 2025 09:41:40 +0800 Message-ID: <20251224014203.756264-2-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540700392158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM 2.0 specification: https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf LTPI is a protocol and physical interface for tunneling various low-speed signals between the HPM and SCM. As shown in Figure 2, the AST27x0 (left) integrates two LTPI controllers, allowing it to connect to up to two extended boards. This commit introduces a simple device model for the ASPEED LTPI controller in QEMU. The model includes basic MMIO read/write operations and sets default register values during reset to emulate a link-up state. Implements register space with read/write callbacks. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/misc/aspeed_ltpi.h | 33 ++++++ hw/misc/aspeed_ltpi.c | 193 ++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 227 insertions(+) create mode 100644 include/hw/misc/aspeed_ltpi.h create mode 100644 hw/misc/aspeed_ltpi.c diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h new file mode 100644 index 0000000000..e991afc666 --- /dev/null +++ b/include/hw/misc/aspeed_ltpi.h @@ -0,0 +1,33 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_LTPI_H +#define ASPEED_LTPI_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI) + +#define ASPEED_LTPI_TOTAL_SIZE 0x900 +#define ASPEED_LTPI_CTRL_SIZE 0x200 +#define ASPEED_LTPI_PHY_SIZE 0x100 +#define ASPEED_LTPI_TOP_SIZE 0x100 + +struct AspeedLTPIState { + SysBusDevice parent; + MemoryRegion mmio; + MemoryRegion mmio_ctrl; + MemoryRegion mmio_phy; + MemoryRegion mmio_top; + + uint32_t ctrl_regs[ASPEED_LTPI_CTRL_SIZE >> 2]; + uint32_t phy_regs[ASPEED_LTPI_PHY_SIZE >> 2]; + uint32_t top_regs[ASPEED_LTPI_TOP_SIZE >> 2]; +}; + +#endif /* ASPEED_LTPI_H */ diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c new file mode 100644 index 0000000000..131cea9c6b --- /dev/null +++ b/hw/misc/aspeed_ltpi.c @@ -0,0 +1,193 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/misc/aspeed_ltpi.h" + +#define ASPEED_LTPI_CTRL_BASE 0x000 +#define ASPEED_LTPI_PHY_BASE 0x200 +#define ASPEED_LTPI_TOP_BASE 0x800 + +#define LTPI_CTRL_LINK_MNG 0x42 +#define LTPI_PHY_MODE 0x0 + +static uint64_t aspeed_ltpi_top_read(void *opaque, hwaddr offset, unsigned= size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + return s->top_regs[idx]; +} + +static void aspeed_ltpi_top_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + switch (offset) { + default: + s->top_regs[idx] =3D (uint32_t)val; + break; + } +} + +static const MemoryRegionOps aspeed_ltpi_top_ops =3D { + .read =3D aspeed_ltpi_top_read, + .write =3D aspeed_ltpi_top_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static uint64_t aspeed_ltpi_phy_read(void *opaque, hwaddr offset, unsigned= size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + return s->phy_regs[idx]; +} + +static void aspeed_ltpi_phy_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + switch (offset) { + default: + s->phy_regs[idx] =3D (uint32_t)val; + break; + } +} + +static const MemoryRegionOps aspeed_ltpi_phy_ops =3D { + .read =3D aspeed_ltpi_phy_read, + .write =3D aspeed_ltpi_phy_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static uint64_t aspeed_ltpi_ctrl_read(void *opaque, + hwaddr offset, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + return s->ctrl_regs[idx]; +} + +static void aspeed_ltpi_ctrl_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + switch (offset) { + default: + s->ctrl_regs[idx] =3D (uint32_t)val; + break; + } +} + +static const MemoryRegionOps aspeed_ltpi_ctrl_ops =3D { + .read =3D aspeed_ltpi_ctrl_read, + .write =3D aspeed_ltpi_ctrl_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void aspeed_ltpi_reset(DeviceState *dev) +{ + AspeedLTPIState *s =3D ASPEED_LTPI(dev); + + memset(s->ctrl_regs, 0, sizeof(s->ctrl_regs)); + memset(s->phy_regs, 0, sizeof(s->phy_regs)); + memset(s->top_regs, 0, sizeof(s->top_regs)); + /* set default values */ + s->ctrl_regs[LTPI_CTRL_LINK_MNG] =3D 0x11900007; + s->phy_regs[LTPI_PHY_MODE] =3D 0x2; +} + + +static const VMStateDescription vmstate_aspeed_ltpi =3D { + .name =3D TYPE_ASPEED_LTPI, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(ctrl_regs, AspeedLTPIState, + ASPEED_LTPI_CTRL_SIZE >> 2), + VMSTATE_UINT32_ARRAY(phy_regs, AspeedLTPIState, + ASPEED_LTPI_PHY_SIZE >> 2), + VMSTATE_UINT32_ARRAY(top_regs, AspeedLTPIState, + ASPEED_LTPI_TOP_SIZE >> 2), + + VMSTATE_END_OF_LIST() + } +}; + +static void aspeed_ltpi_realize(DeviceState *dev, Error **errp) +{ + AspeedLTPIState *s =3D ASPEED_LTPI(dev); + + memory_region_init(&s->mmio, OBJECT(s), TYPE_ASPEED_LTPI, + ASPEED_LTPI_TOTAL_SIZE); + + memory_region_init_io(&s->mmio_ctrl, OBJECT(s), + &aspeed_ltpi_ctrl_ops, s, + "aspeed-ltpi-ctrl", ASPEED_LTPI_CTRL_SIZE); + + memory_region_init_io(&s->mmio_phy, OBJECT(s), + &aspeed_ltpi_phy_ops, s, + "aspeed-ltpi-phy", ASPEED_LTPI_PHY_SIZE); + + memory_region_init_io(&s->mmio_top, OBJECT(s), + &aspeed_ltpi_top_ops, s, + "aspeed-ltpi-top", ASPEED_LTPI_TOP_SIZE); + + memory_region_add_subregion(&s->mmio, + ASPEED_LTPI_CTRL_BASE, &s->mmio_ctrl); + memory_region_add_subregion(&s->mmio, + ASPEED_LTPI_PHY_BASE, &s->mmio_phy); + memory_region_add_subregion(&s->mmio, + ASPEED_LTPI_TOP_BASE, &s->mmio_top); + + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); +} + +static void aspeed_ltpi_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D aspeed_ltpi_realize; + dc->vmsd =3D &vmstate_aspeed_ltpi; + device_class_set_legacy_reset(dc, aspeed_ltpi_reset); +} + +static const TypeInfo aspeed_ltpi_info =3D { + .name =3D TYPE_ASPEED_LTPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedLTPIState), + .class_init =3D aspeed_ltpi_class_init, +}; + +static void aspeed_ltpi_register_types(void) +{ + type_register_static(&aspeed_ltpi_info); +} + +type_init(aspeed_ltpi_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b1d8d8e5d2..45b16e7797 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_hace.c', 'aspeed_i3c.c', 'aspeed_lpc.c', + 'aspeed_ltpi.c', 'aspeed_scu.c', 'aspeed_sbc.c', 'aspeed_sdmc.c', --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 24 Dec 2025 09:42:05 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 02/19] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Date: Wed, 24 Dec 2025 09:41:41 +0800 Message-ID: <20251224014203.756264-3-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540656600158500 From: Kane-Chen-AS Connect the LTPI controller device (representing the AST1700 I/O expander) to the AST27X0 SoC model. This patch sets up the memory mapping and device registration according to the AST2700 SoC design, where the LTPI controller is exposed at fixed MMIO regions. This change only handles device instantiation and integration, without implementing the controller's internal logic. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_soc.h | 5 +++++ hw/arm/aspeed_ast27x0.c | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 18ff961a38..bca10c387b 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -43,6 +43,7 @@ #include "hw/fsi/aspeed_apb2opb.h" #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" +#include "hw/misc/aspeed_ltpi.h" =20 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 @@ -55,6 +56,7 @@ #define ASPEED_UARTS_NUM 13 #define ASPEED_JTAG_NUM 2 #define ASPEED_PCIE_NUM 3 +#define ASPEED_IOEXP_NUM 2 =20 struct AspeedSoCState { DeviceState parent; @@ -112,6 +114,7 @@ struct AspeedSoCState { UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; + AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -279,6 +282,8 @@ enum { ASPEED_GIC_REDIST, ASPEED_DEV_IPC0, ASPEED_DEV_IPC1, + ASPEED_DEV_LTPI_CTRL1, + ASPEED_DEV_LTPI_CTRL2, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 70be3871bb..341b53189b 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -88,6 +88,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_UART10] =3D 0x14C33900, [ASPEED_DEV_UART11] =3D 0x14C33A00, [ASPEED_DEV_UART12] =3D 0x14C33B00, + [ASPEED_DEV_LTPI_CTRL1] =3D 0x14C34000, + [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, [ASPEED_DEV_LTPI] =3D 0x30000000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, @@ -556,6 +558,11 @@ static void aspeed_soc_ast2700_init(Object *obj) object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort= ); } =20 + for (i =3D 0; i < ASPEED_IOEXP_NUM; i++) { + object_initialize_child(obj, "ltpi-ctrl[*]", + &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); + } + object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "ltpi", &s->ltpi, @@ -1047,6 +1054,20 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) return; } =20 + /* LTPI controller */ + for (i =3D 0; i < ASPEED_IOEXP_NUM; i++) { + AspeedLTPIState *ltpi_ctrl; + hwaddr ltpi_base; + + ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[i]); + ltpi_base =3D sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i]; + + if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base= ); + } + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540595; cv=none; d=zohomail.com; s=zohoarc; b=TEf8qwAaYTAMvwgtHKXt7c+sYy0zvLTbMui35suJkhCh+EJV/EHHvvWiCzIcr2gHlYKaokTHDcjGIEhyW68bVGH9XxR0upMgq3UWwEq713jRAWE5mTKY+pJKk4XlYe0kDyomVOxrqPOTj9ky7JUW6oQ47RzRUbNVM3NmYNhHMA8= ARC-Message-Signature: i=1; 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Tue, 23 Dec 2025 20:43:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDti-0001G5-Un; Tue, 23 Dec 2025 20:42:44 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDtg-00058k-MF; Tue, 23 Dec 2025 20:42:42 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:05 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS Subject: [PATCH v4 03/19] hw/misc: Add basic Aspeed PWM model Date: Wed, 24 Dec 2025 09:41:42 +0800 Message-ID: <20251224014203.756264-4-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540596007158500 From: Kane-Chen-AS Add an initial PWM model for Aspeed SoCs, including device state, register definitions, and basic initialization as a sysbus device. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Kane-Chen-AS Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_soc.h | 3 +- include/hw/misc/aspeed_pwm.h | 31 +++++++++ hw/misc/aspeed_pwm.c | 121 +++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 4 ++ 5 files changed, 159 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/aspeed_pwm.h create mode 100644 hw/misc/aspeed_pwm.c diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index bca10c387b..7b08cca908 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -28,6 +28,7 @@ #include "hw/misc/aspeed_hace.h" #include "hw/misc/aspeed_sbc.h" #include "hw/misc/aspeed_sli.h" +#include "hw/misc/aspeed_pwm.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" @@ -88,6 +89,7 @@ struct AspeedSoCState { MemoryRegion secsram; UnimplementedDeviceState sbc_unimplemented; AspeedSDMCState sdmc; + AspeedPWMState pwm; AspeedWDTState wdt[ASPEED_WDTS_NUM]; FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; AspeedMiiState mii[ASPEED_MACS_NUM]; @@ -108,7 +110,6 @@ struct AspeedSoCState { UnimplementedDeviceState video; UnimplementedDeviceState emmc_boot_controller; UnimplementedDeviceState dpmcu; - UnimplementedDeviceState pwm; UnimplementedDeviceState espi; UnimplementedDeviceState udc; UnimplementedDeviceState ltpi; diff --git a/include/hw/misc/aspeed_pwm.h b/include/hw/misc/aspeed_pwm.h new file mode 100644 index 0000000000..13dc3ea45b --- /dev/null +++ b/include/hw/misc/aspeed_pwm.h @@ -0,0 +1,31 @@ +/* + * ASPEED PWM Controller + * + * Copyright (C) 2017-2021 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef ASPEED_PWM_H +#define ASPEED_PWM_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_PWM "aspeed.pwm" +#define ASPEED_PWM(obj) OBJECT_CHECK(AspeedPWMState, (obj), TYPE_ASPEED_PW= M) + +#define ASPEED_PWM_NR_REGS (0x10C >> 2) + +typedef struct AspeedPWMState { + /* */ + SysBusDevice parent; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq irq; + + uint32_t regs[ASPEED_PWM_NR_REGS]; +} AspeedPWMState; + +#endif /* _ASPEED_PWM_H_ */ diff --git a/hw/misc/aspeed_pwm.c b/hw/misc/aspeed_pwm.c new file mode 100644 index 0000000000..de209274af --- /dev/null +++ b/hw/misc/aspeed_pwm.c @@ -0,0 +1,121 @@ +/* + * ASPEED PWM Controller + * + * Copyright (C) 2017-2021 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/misc/aspeed_pwm.h" +#include "qapi/error.h" +#include "migration/vmstate.h" + +#include "trace.h" + +static uint64_t aspeed_pwm_read(void *opaque, hwaddr addr, + unsigned int size) +{ + AspeedPWMState *s =3D ASPEED_PWM(opaque); + uint64_t val =3D 0; + + addr >>=3D 2; + + if (addr >=3D ASPEED_PWM_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", + __func__, addr << 2); + } else { + val =3D s->regs[addr]; + } + + trace_aspeed_pwm_read(addr << 2, val); + + return val; +} + +static void aspeed_pwm_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + AspeedPWMState *s =3D ASPEED_PWM(opaque); + + trace_aspeed_pwm_write(addr, data); + + addr >>=3D 2; + + if (addr >=3D ASPEED_PWM_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, addr << 2); + return; + } + + s->regs[addr] =3D data; +} + +static const MemoryRegionOps aspeed_pwm_ops =3D { + .read =3D aspeed_pwm_read, + .write =3D aspeed_pwm_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void aspeed_pwm_reset(DeviceState *dev) +{ + struct AspeedPWMState *s =3D ASPEED_PWM(dev); + + memset(s->regs, 0, sizeof(s->regs)); +} + +static void aspeed_pwm_realize(DeviceState *dev, Error **errp) +{ + AspeedPWMState *s =3D ASPEED_PWM(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_pwm_ops, s, + TYPE_ASPEED_PWM, 0x1000); + + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription vmstate_aspeed_pwm =3D { + .name =3D TYPE_ASPEED_PWM, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedPWMState, ASPEED_PWM_NR_REGS), + VMSTATE_END_OF_LIST(), + } +}; + +static void aspeed_pwm_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_pwm_realize; + device_class_set_legacy_reset(dc, aspeed_pwm_reset); + dc->desc =3D "Aspeed PWM Controller"; + dc->vmsd =3D &vmstate_aspeed_pwm; +} + +static const TypeInfo aspeed_pwm_info =3D { + .name =3D TYPE_ASPEED_PWM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedPWMState), + .class_init =3D aspeed_pwm_class_init, +}; + +static void aspeed_pwm_register_types(void) +{ + type_register_static(&aspeed_pwm_info); +} + +type_init(aspeed_pwm_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 45b16e7797..7afe1d0009 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -137,6 +137,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_i3c.c', 'aspeed_lpc.c', 'aspeed_ltpi.c', + 'aspeed_pwm.c', 'aspeed_scu.c', 'aspeed_sbc.c', 'aspeed_sdmc.c', diff --git a/hw/misc/trace-events b/hw/misc/trace-events index eeb9243898..f7870babba 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -299,6 +299,10 @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C = write: offset 0x%" PRIx64 aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) = "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data)= "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 =20 +# aspeed_pwm.c +aspeed_pwm_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 = " data 0x%" PRIx64 +aspeed_pwm_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx6= 4 " data 0x%" PRIx64 + # aspeed_sdmc.c aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0= x%" PRIx64 aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x= %" PRIx64 --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 24 Dec 2025 09:42:05 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS Subject: [PATCH v4 04/19] hw/arm/aspeed: Add AST1700 LTPI expander device model Date: Wed, 24 Dec 2025 09:41:43 +0800 Message-ID: <20251224014203.756264-5-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540646443158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Introduce a minimal QEMU device model for the ASPEED AST1700, an MCU-less I/O expander used in the LTPI topology defined by the DC-SCM 2.0 specification (see figure 2): https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf This initial implementation includes: * Definition of aspeed.ast1700 as a SysBusDevice * Setup of a basic memory region to reserve I/O space for future peripheral modeling This stub establishes the foundation for LTPI-related device emulation, without implementing any functional peripherals at this stage. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 23 ++++++++++++++++ hw/arm/aspeed_ast1700.c | 47 +++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 71 insertions(+) create mode 100644 include/hw/arm/aspeed_ast1700.h create mode 100644 hw/arm/aspeed_ast1700.c diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h new file mode 100644 index 0000000000..2a95ebfe89 --- /dev/null +++ b/include/hw/arm/aspeed_ast1700.h @@ -0,0 +1,23 @@ +/* + * ASPEED AST1700 IO Expander + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_AST1700_H +#define ASPEED_AST1700_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_AST1700 "aspeed.ast1700" + +OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700) + +struct AspeedAST1700SoCState { + SysBusDevice parent_obj; + + MemoryRegion iomem; +}; + +#endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c new file mode 100644 index 0000000000..bb6ca2ce9e --- /dev/null +++ b/hw/arm/aspeed_ast1700.c @@ -0,0 +1,47 @@ +/* + * ASPEED AST1700 IO Expander + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/qdev-core.h" +#include "qom/object.h" +#include "hw/arm/aspeed_ast1700.h" + +#define AST2700_SOC_LTPI_SIZE 0x01000000 + +static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) +{ + AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + /* Occupy memory space for all controllers in AST1700 */ + memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, + AST2700_SOC_LTPI_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_ast1700_realize; +} + +static const TypeInfo aspeed_ast1700_info =3D { + .name =3D TYPE_ASPEED_AST1700, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedAST1700SoCState), + .class_init =3D aspeed_ast1700_class_init, +}; + +static void aspeed_ast1700_register_types(void) +{ + type_register_static(&aspeed_ast1700_info); +} + +type_init(aspeed_ast1700_register_types); diff --git a/hw/arm/meson.build b/hw/arm/meson.build index aeaf654790..175942263d 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -70,6 +70,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast10x0_evb.c', 'fby35.c')) arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: = files( + 'aspeed_ast1700.c', 'aspeed_ast27x0.c', 'aspeed_ast27x0_evb.c', 'aspeed_ast27x0-fc.c', --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766540628986591.933770098021; Tue, 23 Dec 2025 17:43:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYDu0-0001LC-4f; Tue, 23 Dec 2025 20:43:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDtn-0001IT-RK; Tue, 23 Dec 2025 20:42:48 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDtm-00058k-7t; Tue, 23 Dec 2025 20:42:47 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 05/19] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Date: Wed, 24 Dec 2025 09:41:44 +0800 Message-ID: <20251224014203.756264-6-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540630756158500 From: Kane-Chen-AS Connect the AST1700 device as a child of the AST27X0 model to reflect its role in DC-SCM 2.0 LTPI-based architectures. This patch wires the AST1700 device into the platform without introducing functional peripherals. This forms the base for LTPI expander emulation in QEMU using AST27X0 as the host controller. Note: ioexp_num is set to 0 at this stage. Once all related devices and interrupts are fully implemented, ioexp_num will be updated to its expected value. This ensures the machine remains functional at every commit and avoids potential compiler or build issues. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_soc.h | 7 +++++-- hw/arm/aspeed_ast27x0.c | 26 ++++++++++++++++++-------- 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 7b08cca908..f19bab3457 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -45,6 +45,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/arm/aspeed_ast1700.h" =20 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 @@ -112,10 +113,10 @@ struct AspeedSoCState { UnimplementedDeviceState dpmcu; UnimplementedDeviceState espi; UnimplementedDeviceState udc; - UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; + AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM]; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -178,6 +179,7 @@ struct AspeedSoCClass { int macs_num; int uarts_num; int uarts_base; + int ioexp_num; const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; @@ -190,7 +192,6 @@ enum { ASPEED_DEV_IOMEM, ASPEED_DEV_IOMEM0, ASPEED_DEV_IOMEM1, - ASPEED_DEV_LTPI, ASPEED_DEV_UART0, ASPEED_DEV_UART1, ASPEED_DEV_UART2, @@ -285,6 +286,8 @@ enum { ASPEED_DEV_IPC1, ASPEED_DEV_LTPI_CTRL1, ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_LTPI_IO0, + ASPEED_DEV_LTPI_IO1, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 341b53189b..de39a3e7eb 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -26,7 +26,6 @@ #define AST2700_SOC_IO_SIZE 0x00FE0000 #define AST2700_SOC_IOMEM_SIZE 0x01000000 #define AST2700_SOC_DPMCU_SIZE 0x00040000 -#define AST2700_SOC_LTPI_SIZE 0x01000000 =20 static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_VBOOTROM] =3D 0x00000000, @@ -91,7 +90,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL1] =3D 0x14C34000, [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, - [ASPEED_DEV_LTPI] =3D 0x30000000, + [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, @@ -563,10 +563,14 @@ static void aspeed_soc_ast2700_init(Object *obj) &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); } =20 + for (i =3D 0; i < sc->ioexp_num; i++) { + /* AST1700 IOEXP */ + object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], + TYPE_ASPEED_AST1700); + } + object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); - object_initialize_child(obj, "ltpi", &s->ltpi, - TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem0", &s->iomem0, @@ -1068,14 +1072,19 @@ static void aspeed_soc_ast2700_realize(DeviceState = *dev, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base= ); } =20 + /* IO Expander */ + for (i =3D 0; i < sc->ioexp_num; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0, + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); + } + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], AST2700_SOC_DPMCU_SIZE); - aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi), - "aspeed.ltpi", - sc->memmap[ASPEED_DEV_LTPI], - AST2700_SOC_LTPI_SIZE); aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", sc->memmap[ASPEED_DEV_IOMEM], @@ -1143,6 +1152,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->macs_num =3D 3; sc->uarts_num =3D 13; sc->num_cpus =3D 4; + sc->ioexp_num =3D 0; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; sc->memmap =3D aspeed_soc_ast2700_memmap; --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540631; cv=none; d=zohomail.com; s=zohoarc; b=Cxl2G+8ZQVMlOJ3ZIS/TH447B4WWuqAevSQfJ6Jth3QaRxwac/Dh/UscvgBTSfKi6M65OrV5tP1XSTL+oqHcFwUBPn+nGNjTnC1woIIojYWe4CtkztU3SQjTvalR5crbGsy+uamvnhGvh474h/SPO6f8DRlAyN6I6ZqzVEmHdyk= ARC-Message-Signature: i=1; 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Tue, 23 Dec 2025 20:43:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDtr-0001Jt-2i; Tue, 23 Dec 2025 20:42:52 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDtp-00058k-8i; Tue, 23 Dec 2025 20:42:50 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS Subject: [PATCH v4 06/19] hw/arm/aspeed: Integrate interrupt controller for AST1700 Date: Wed, 24 Dec 2025 09:41:45 +0800 Message-ID: <20251224014203.756264-7-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Kane-Chen-AS Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling the propagation of AST1700-originated interrupts to the host SoC. This patch does not implement interrupt sources in AST1700 itself, only the wiring into AST27X0. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_soc.h | 6 +++- include/hw/intc/aspeed_intc.h | 2 ++ hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++ hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++ 4 files changed, 104 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index f19bab3457..b051d0eb3a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -58,6 +58,7 @@ #define ASPEED_UARTS_NUM 13 #define ASPEED_JTAG_NUM 2 #define ASPEED_PCIE_NUM 3 +#define ASPEED_INTC_NUM 2 #define ASPEED_IOEXP_NUM 2 =20 struct AspeedSoCState { @@ -146,7 +147,8 @@ struct Aspeed27x0SoCState { AspeedSoCState parent; =20 ARMCPU cpu[ASPEED_CPUS_NUM]; - AspeedINTCState intc[2]; + AspeedINTCState intc[ASPEED_INTC_NUM]; + AspeedINTCState intcioexp[ASPEED_IOEXP_NUM]; GICv3State gic; MemoryRegion dram_empty; }; @@ -288,6 +290,8 @@ enum { ASPEED_DEV_LTPI_CTRL2, ASPEED_DEV_LTPI_IO0, ASPEED_DEV_LTPI_IO1, + ASPEED_DEV_IOEXP0_INTCIO, + ASPEED_DEV_IOEXP1_INTCIO, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 51288384a5..4565bbab84 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -15,6 +15,8 @@ #define TYPE_ASPEED_INTC "aspeed.intc" #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700" +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "ast2700-ioexp1" +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "ast2700-ioexp2" #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp" #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp" #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp" diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index de39a3e7eb..678d4eb6d9 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -91,7 +91,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_IOEXP0_INTCIO] =3D 0x30C18000, [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, + [ASPEED_DEV_IOEXP1_INTCIO] =3D 0x50C18000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, @@ -511,6 +513,10 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INT= C); object_initialize_child(obj, "intcio", &a->intc[1], TYPE_ASPEED_2700_INTCIO); + object_initialize_child(obj, "intcioexp0", &a->intcioexp[0], + TYPE_ASPEED_2700_INTCIOEXP1); + object_initialize_child(obj, "intcioexp1", &a->intcioexp[1], + TYPE_ASPEED_2700_INTCIOEXP2); =20 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "adc", &s->adc, typename); @@ -755,6 +761,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0, sc->memmap[ASPEED_DEV_INTCIO]); =20 + /* INTCIOEXP0 */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) { + return; + } + + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]), 0, + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]); + + /* INTCIOEXP1 */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) { + return; + } + + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]), 0, + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]); + /* irq sources -> orgates -> INTC */ for (i =3D 0; i < ic->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, @@ -1079,6 +1101,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0, sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); + + icio =3D ASPEED_INTC_GET_CLASS(&a->intcioexp[i]); + /* INTC_IOEXP internal: orgate[i] -> input[i] */ + for (int j =3D 0; j < icio->num_inpins; j++) { + irq =3D qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j); + qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]), 0, + irq); + } + + /* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */ + for (int j =3D 0; j < icio->num_outpins; j++) { + irq =3D qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j); + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j, + irq); + } } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 5cd786dee6..a04005ee7c 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -924,6 +924,64 @@ static const TypeInfo aspeed_2700_intc_info =3D { .class_init =3D aspeed_2700_intc_class_init, }; =20 +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP2 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp2_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp2_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp2_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP2, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp2_class_init, +}; + +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP1 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp1_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp1_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp1_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP1, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp1_class_init, +}; + static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] =3D { {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS}, {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS}, @@ -1099,6 +1157,8 @@ static void aspeed_intc_register_types(void) type_register_static(&aspeed_intc_info); type_register_static(&aspeed_2700_intc_info); type_register_static(&aspeed_2700_intcio_info); + type_register_static(&aspeed_2700_intcioexp1_info); + type_register_static(&aspeed_2700_intcioexp2_info); type_register_static(&aspeed_2700ssp_intc_info); type_register_static(&aspeed_2700ssp_intcio_info); type_register_static(&aspeed_2700tsp_intc_info); --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540713; cv=none; d=zohomail.com; s=zohoarc; b=cV17yRr/ikp5SZswcwDOhaVO93wTJj4KhAFQXAwhjezGrF/kT7saNSm4Ux6mi6n/OjbsnFSl9uFadHfMs9SSh/CuNgDYncJPpektXKwHSze/OidDPT67o+vcivGogEoOVCMJJy0SJQhqYFhbkrqQlaxkH7OsoVmg0btknTH91Ok= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Tue, 23 Dec 2025 20:43:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDtz-0001Kv-8x; Tue, 23 Dec 2025 20:43:00 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDts-00058k-3N; Tue, 23 Dec 2025 20:42:55 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:07 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS Subject: [PATCH v4 07/19] hw/arm/aspeed: Attach LTPI controller to AST1700 model Date: Wed, 24 Dec 2025 09:41:46 +0800 Message-ID: <20251224014203.756264-8-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Kane-Chen-AS Connect the LTPI controller to the AST1700 model by mapping its MMIO region. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 3 +++ hw/arm/aspeed_ast1700.c | 27 +++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 2a95ebfe89..b9ee4952d0 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -9,6 +9,7 @@ #define ASPEED_AST1700_H =20 #include "hw/sysbus.h" +#include "hw/misc/aspeed_ltpi.h" =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" =20 @@ -18,6 +19,8 @@ struct AspeedAST1700SoCState { SysBusDevice parent_obj; =20 MemoryRegion iomem; + + AspeedLTPIState ltpi; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index bb6ca2ce9e..eeb586102f 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -14,6 +14,14 @@ =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 =20 +enum { + ASPEED_AST1700_DEV_LTPI_CTRL, +}; + +static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, +}; + static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); @@ -23,8 +31,26 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); + + /* LTPI controller */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_C= TRL], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0= )); } =20 +static void aspeed_ast1700_instance_init(Object *obj) +{ + AspeedAST1700SoCState *s =3D ASPEED_AST1700(obj); + + /* LTPI controller */ + object_initialize_child(obj, "ltpi-ctrl", + &s->ltpi, TYPE_ASPEED_LTPI); + + return; +} static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -37,6 +63,7 @@ static const TypeInfo aspeed_ast1700_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(AspeedAST1700SoCState), .class_init =3D aspeed_ast1700_class_init, + .instance_init =3D aspeed_ast1700_instance_init, }; =20 static void aspeed_ast1700_register_types(void) --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540706; cv=none; d=zohomail.com; s=zohoarc; b=cOUzo7KqyJXhY4n+pQpq+1DDSiL1W/W9IsJ8qy0ZCWp/J0gTmcmRU3bzI+kpVsEnzLBKqIo8poeaH/+O/MEIRJwv9zKC4u3wBeoH4fDhdokX3ujCMh0JweQbw2ahyQmzoDT/ScSJa9dm8K6dHbagVCrkvG1VaQ2rSm3KgXcArYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766540706; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 23 Dec 2025 20:43:01 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:07 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 08/19] hw/arm/aspeed: Attach UART device to AST1700 model Date: Wed, 24 Dec 2025 09:41:47 +0800 Message-ID: <20251224014203.756264-9-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540708315158500 From: Kane-Chen-AS Connect the UART controller to the AST1700 model by mapping its MMIO region. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index b9ee4952d0..a0d6b3ae44 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -10,6 +10,7 @@ =20 #include "hw/sysbus.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/char/serial-mm.h" =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" =20 @@ -21,6 +22,7 @@ struct AspeedAST1700SoCState { MemoryRegion iomem; =20 AspeedLTPIState ltpi; + SerialMM uart; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index eeb586102f..f444582795 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -10,15 +10,18 @@ #include "hw/boards.h" #include "hw/qdev-core.h" #include "qom/object.h" +#include "hw/qdev-properties.h" #include "hw/arm/aspeed_ast1700.h" =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 =20 enum { + ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, }; =20 @@ -32,6 +35,17 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); =20 + /* UART */ + qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2); + qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400); + qdev_prop_set_uint8(DEVICE(&s->uart), "endianness", DEVICE_LITTLE_ENDI= AN); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12= ], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0= )); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -45,6 +59,10 @@ static void aspeed_ast1700_instance_init(Object *obj) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(obj); =20 + /* UART */ + object_initialize_child(obj, "uart[*]", &s->uart, + TYPE_SERIAL_MM); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540632; cv=none; d=zohomail.com; s=zohoarc; b=eQUtBG/uDSp1aQAEwbhrGkWKPWbypwGsYKzZq6W/fGeW30FCyNIzKfcMenZVOijyYbnC6siGviNU+WcMcnnbnisau/RtkwU2BTZPi+1yXQq2q44mlhWF4dufKc+pXQPmVQ1/y4HxJOVl2LkdMzf//EKeTt8+X0AP+Xhy/kyzZCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766540632; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 23 Dec 2025 20:43:03 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:07 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 09/19] hw/arm/aspeed: Attach SRAM device to AST1700 model Date: Wed, 24 Dec 2025 09:41:48 +0800 Message-ID: <20251224014203.756264-10-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540634076158500 From: Kane-Chen-AS Map the SRAM device to AST1700 model Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 18 ++++++++++++++++++ hw/arm/aspeed_ast27x0.c | 1 + 3 files changed, 21 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index a0d6b3ae44..23588f7a81 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -20,9 +20,11 @@ struct AspeedAST1700SoCState { SysBusDevice parent_obj; =20 MemoryRegion iomem; + uint8_t board_idx; =20 AspeedLTPIState ltpi; SerialMM uart; + MemoryRegion sram; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index f444582795..cb07d94054 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -14,13 +14,16 @@ #include "hw/arm/aspeed_ast1700.h" =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 +#define AST1700_SOC_SRAM_SIZE 0x00040000 =20 enum { + ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, }; @@ -29,12 +32,21 @@ static void aspeed_ast1700_realize(DeviceState *dev, Er= ror **errp) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + char dev_name[32]; =20 /* Occupy memory space for all controllers in AST1700 */ memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); =20 + /* SRAM */ + snprintf(dev_name, sizeof(dev_name), "aspeed.ioexp-sram.%d", s->board_= idx); + memory_region_init_ram(&s->sram, OBJECT(s), dev_name, + AST1700_SOC_SRAM_SIZE, errp); + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SR= AM], + &s->sram); + /* UART */ qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2); qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400); @@ -69,11 +81,17 @@ static void aspeed_ast1700_instance_init(Object *obj) =20 return; } + +static const Property aspeed_ast1700_props[] =3D { + DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0), +}; + static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D aspeed_ast1700_realize; + device_class_set_props(dc, aspeed_ast1700_props); } =20 static const TypeInfo aspeed_ast1700_info =3D { diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 678d4eb6d9..f2418e0e45 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1096,6 +1096,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) =20 /* IO Expander */ for (i =3D 0; i < sc->ioexp_num; i++) { + qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { return; } --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540695; cv=none; d=zohomail.com; s=zohoarc; b=ARXSxrChh/cGeq0YKAw2Y4W63UvSnGzUzf30IFrGYVSEQ9DBVlJGHxV47KugfZJqxfhHxAZIhM5TWZTUvhSjf4gkGnnmEYl3SEpKvznJAikjvYgfVki5xzRRBDDkJf26kQ/+nPLNQtvRqR0YbIGqf0a/EiiDtm9gCWTpN3cGNi8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766540695; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 23 Dec 2025 20:43:06 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:08 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 10/19] hw/arm/aspeed: Attach SPI device to AST1700 model Date: Wed, 24 Dec 2025 09:41:49 +0800 Message-ID: <20251224014203.756264-11-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540696565158500 From: Kane-Chen-AS Connect the SPI device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 23588f7a81..5b120dd11a 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -10,6 +10,7 @@ =20 #include "hw/sysbus.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/ssi/aspeed_smc.h" #include "hw/char/serial-mm.h" =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" @@ -25,6 +26,7 @@ struct AspeedAST1700SoCState { AspeedLTPIState ltpi; SerialMM uart; MemoryRegion sram; + AspeedSMCState spi; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index cb07d94054..fc09bb1aed 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -17,15 +17,19 @@ #define AST1700_SOC_SRAM_SIZE 0x00040000 =20 enum { + ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, + ASPEED_AST1700_DEV_SPI0_MEM, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, + [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, }; =20 static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) @@ -58,6 +62,20 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12= ], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0= )); =20 + /* SPI */ + object_property_set_link(OBJECT(&s->spi), "dram", + OBJECT(&s->iomem), errp); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 0)= ); + + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_M= EM], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -75,6 +93,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "uart[*]", &s->uart, TYPE_SERIAL_MM); =20 + /* SPI */ + object_initialize_child(obj, "ioexp-spi[*]", &s->spi, + "aspeed.spi0-ast2700"); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540632; cv=none; d=zohomail.com; s=zohoarc; b=cxh0wkZ2mTRly3GE56MzyRzOW364vdPpUAxEAuX3hn4NBjY8+cJrg5WP1NDCpiOWGY6v+++DXLhhwUx94G9q6DkNcCwJbHr/yR3FPpwrOoPxVB6GCt4xD0gaHNjmLsgILgp72PbF3fxbcbr2hBehtj5UyX644V95qxibif4fy/Y= ARC-Message-Signature: i=1; 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Tue, 23 Dec 2025 20:43:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDu8-0001Uw-QM; Tue, 23 Dec 2025 20:43:10 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDu7-00058k-Az; Tue, 23 Dec 2025 20:43:08 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:08 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 11/19] hw/arm/aspeed: Attach ADC device to AST1700 model Date: Wed, 24 Dec 2025 09:41:50 +0800 Message-ID: <20251224014203.756264-12-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540634073158500 From: Kane-Chen-AS Connect the ADC device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 14 ++++++++++++++ hw/arm/aspeed_ast27x0.c | 5 +++++ 3 files changed, 21 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 5b120dd11a..0c1216c4ba 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -9,6 +9,7 @@ #define ASPEED_AST1700_H =20 #include "hw/sysbus.h" +#include "hw/adc/aspeed_adc.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" #include "hw/char/serial-mm.h" @@ -27,6 +28,7 @@ struct AspeedAST1700SoCState { SerialMM uart; MemoryRegion sram; AspeedSMCState spi; + AspeedADCState adc; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index fc09bb1aed..e4d206045f 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -19,6 +19,7 @@ enum { ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, + ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -27,6 +28,7 @@ enum { static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, + [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -76,6 +78,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_M= EM], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1)= ); =20 + /* ADC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -97,6 +107,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-spi[*]", &s->spi, "aspeed.spi0-ast2700"); =20 + /* ADC */ + object_initialize_child(obj, "ioexp-adc[*]", &s->adc, + "aspeed.adc-ast2700"); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index f2418e0e45..84ff8b5557 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1117,6 +1117,11 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j, irq); } + + /* ADC */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC)); + } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540714; cv=none; d=zohomail.com; s=zohoarc; b=eK5MSdM6NtJk34FpzWo3t8YY/0lcO3MhEzaBars1bjpwepXhEx8fLZwLFgkvtpLRqGZiCUV1ne7qFL2eTdcdypz1aCj2uhMTtVrTZJzb+26cEKc+/8K4D+U9RI8sPSIcZtol5Ztxb2439YrBUhPrpCBCWOMBONzUevujxr9rNso= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766540714; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 23 Dec 2025 20:43:10 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:09 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 12/19] hw/arm/aspeed: Attach SCU device to AST1700 model Date: Wed, 24 Dec 2025 09:41:51 +0800 Message-ID: <20251224014203.756264-13-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540716439158500 From: Kane-Chen-AS Connect the SCU device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 3 +++ hw/arm/aspeed_ast1700.c | 17 +++++++++++++++++ hw/arm/aspeed_ast27x0.c | 2 ++ 3 files changed, 22 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 0c1216c4ba..12c57145c6 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -9,6 +9,7 @@ #define ASPEED_AST1700_H =20 #include "hw/sysbus.h" +#include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" @@ -23,12 +24,14 @@ struct AspeedAST1700SoCState { =20 MemoryRegion iomem; uint8_t board_idx; + uint32_t silicon_rev; =20 AspeedLTPIState ltpi; SerialMM uart; MemoryRegion sram; AspeedSMCState spi; AspeedADCState adc; + AspeedSCUState scu; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index e4d206045f..6494a5c4eb 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -20,6 +20,7 @@ enum { ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, + ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -29,6 +30,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, + [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -86,6 +88,16 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0)= ); =20 + /* SCU */ + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", + s->silicon_rev); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -111,6 +123,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-adc[*]", &s->adc, "aspeed.adc-ast2700"); =20 + /* SCU */ + object_initialize_child(obj, "ioexp-scu[*]", &s->scu, + TYPE_ASPEED_2700_SCU); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); @@ -120,6 +136,7 @@ static void aspeed_ast1700_instance_init(Object *obj) =20 static const Property aspeed_ast1700_props[] =3D { DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0), + DEFINE_PROP_UINT32("silicon-rev", AspeedAST1700SoCState, silicon_rev, = 0), }; =20 static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 84ff8b5557..6b9ad328dc 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -573,6 +573,8 @@ static void aspeed_soc_ast2700_init(Object *obj) /* AST1700 IOEXP */ object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], TYPE_ASPEED_AST1700); + qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev", + sc->silicon_rev); } =20 object_initialize_child(obj, "dpmcu", &s->dpmcu, --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540676; cv=none; d=zohomail.com; s=zohoarc; b=d5LnUMB8xZho8uolE4/zjcsSsrtuwoei9YLttEYSQMsFjKms0ZquqhwHLjSXUSEkzL1SeI63FjpCRpEj8J2STW+RAundEIeD5eQTG3Iex3oPnKtQBu5GxPHM1uA6rcGXksUa4eU8Cp2Vl6/dzF0tv+09z6lGy4u6V6D0gmZ79OA= ARC-Message-Signature: i=1; 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Tue, 23 Dec 2025 20:43:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDuD-0001ag-Cx; Tue, 23 Dec 2025 20:43:13 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDuB-00058k-Sy; Tue, 23 Dec 2025 20:43:13 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:09 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 13/19] hw/arm/aspeed: Attach GPIO device to AST1700 model Date: Wed, 24 Dec 2025 09:41:52 +0800 Message-ID: <20251224014203.756264-14-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540678231158500 From: Kane-Chen-AS Connect the GPIO controller to the AST1700 model by mapping its MMIO region and wiring its interrupt line. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 14 ++++++++++++++ hw/arm/aspeed_ast27x0.c | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 12c57145c6..7ea6ff4c1a 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -11,6 +11,7 @@ #include "hw/sysbus.h" #include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" +#include "hw/gpio/aspeed_gpio.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" #include "hw/char/serial-mm.h" @@ -32,6 +33,7 @@ struct AspeedAST1700SoCState { AspeedSMCState spi; AspeedADCState adc; AspeedSCUState scu; + AspeedGPIOState gpio; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 6494a5c4eb..9a6019908e 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -21,6 +21,7 @@ enum { ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, + ASPEED_AST1700_DEV_GPIO, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -31,6 +32,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, + [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -98,6 +100,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Er= ror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0)= ); =20 + /* GPIO */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0= )); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -127,6 +137,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-scu[*]", &s->scu, TYPE_ASPEED_2700_SCU); =20 + /* GPIO */ + object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio, + "aspeed.gpio-ast2700"); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6b9ad328dc..d998326536 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1124,6 +1124,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC)); =20 + /* GPIO */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); + } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540673; cv=none; d=zohomail.com; s=zohoarc; b=FcSeREI7GsRZE76f0SyHF2pCi9DUiabdjthgTQnnnXxHM4KMqU8BvvlfKST9/rAJ0EW1l9rC07sQ4w90NGKzUntp56XuXKnHLng1N3yNArZTpfmuJ3rvV7xf4eB5Nsy4yBdzaC/zQhR4hoZ1t3gfrWlluw8dED9F22eaH9R4w/8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766540673; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 23 Dec 2025 20:43:36 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:09 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS Subject: [PATCH v4 14/19] hw/arm/aspeed: attach I2C device to AST1700 model Date: Wed, 24 Dec 2025 09:41:53 +0800 Message-ID: <20251224014203.756264-15-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Kane-Chen-AS Connect the I2C controller to the AST1700 model by mapping its MMIO region and wiring its interrupt line. This patch also adds a bus_label property to distinguish I2C buses on the BMC from those on external boards. This prevents user-specified I2C devices from being attached to the wrong bus when provided via CLI. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_ast1700.h | 2 ++ include/hw/arm/aspeed_soc.h | 2 ++ include/hw/i2c/aspeed_i2c.h | 1 + hw/arm/aspeed_ast1700.c | 18 ++++++++++++ hw/arm/aspeed_ast27x0.c | 51 +++++++++++++++++++++++++++++++-- hw/i2c/aspeed_i2c.c | 19 ++++++++++-- 6 files changed, 88 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 7ea6ff4c1a..d4b7abee7d 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -12,6 +12,7 @@ #include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" #include "hw/gpio/aspeed_gpio.h" +#include "hw/i2c/aspeed_i2c.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" #include "hw/char/serial-mm.h" @@ -34,6 +35,7 @@ struct AspeedAST1700SoCState { AspeedADCState adc; AspeedSCUState scu; AspeedGPIOState gpio; + AspeedI2CState i2c; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index b051d0eb3a..4ea2521041 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -290,6 +290,8 @@ enum { ASPEED_DEV_LTPI_CTRL2, ASPEED_DEV_LTPI_IO0, ASPEED_DEV_LTPI_IO1, + ASPEED_DEV_IOEXP0_I2C, + ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, }; diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 2daacc10ce..babbad5ed9 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -269,6 +269,7 @@ struct AspeedI2CState { uint32_t intr_status; uint32_t ctrl_global; uint32_t new_clk_divider; + char *bus_label; MemoryRegion pool_iomem; uint8_t share_pool[ASPEED_I2C_SHARE_POOL_SIZE]; =20 diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 9a6019908e..fad3b86e8d 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -22,6 +22,7 @@ enum { ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_GPIO, + ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -33,6 +34,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, + [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -108,6 +110,18 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0= )); =20 + /* I2C */ + snprintf(dev_name, sizeof(dev_name), "ioexp%d", s->board_idx); + qdev_prop_set_string(DEVICE(&s->i2c), "bus-label", dev_name); + object_property_set_link(OBJECT(&s->i2c), "dram", + OBJECT(&s->iomem), errp); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -141,6 +155,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio, "aspeed.gpio-ast2700"); =20 + /* I2C */ + object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c, + "aspeed.i2c-ast2700"); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index d998326536..ca3adf9a50 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -205,6 +205,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_ETH3] =3D 196, [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, + [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP1_I2C] =3D 200, }; =20 /* GICINT 128 */ @@ -267,6 +269,18 @@ static const int ast2700_gic133_gic197_intcmap[] =3D { [ASPEED_DEV_PECI] =3D 4, }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GICINT 198 */ +static const int ast2700_gic198_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ +}; + +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 200 */ +static const int ast2700_gic200_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ +}; + /* GICINT 128 ~ 136 */ /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { @@ -283,9 +297,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcm= ap[] =3D { {195, 1, 3, ast2700_gic131_gic195_intcmap}, {196, 1, 4, ast2700_gic132_gic196_intcmap}, {197, 1, 5, ast2700_gic133_gic197_intcmap}, - {198, 1, 6, NULL}, + {198, 2, 0, ast2700_gic198_intcmap}, {199, 1, 7, NULL}, - {200, 1, 8, NULL}, + {200, 3, 0, ast2700_gic200_intcmap}, {201, 1, 9, NULL}, {128, 0, 1, ast2700_gic128_gic192_intcmap}, {129, 0, 2, NULL}, @@ -327,14 +341,23 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(Aspe= edSoCState *s, int dev, int or_idx; int idx; int i; + OrIRQState *porgates; =20 for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) { assert(ast2700_gic_intcmap[i].ptr); or_idx =3D ast2700_gic_intcmap[i].orgate_idx; idx =3D ast2700_gic_intcmap[i].intc_idx; - return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), + if (idx < ASPEED_INTC_NUM) { + porgates =3D &a->intc[idx].orgates[or_idx]; + return qdev_get_gpio_in(DEVICE(porgates), + ast2700_gic_intcmap[i].ptr[dev] + inde= x); + } else { + idx -=3D ASPEED_INTC_NUM; + porgates =3D &a->intcioexp[idx].orgates[or_idx]; + return qdev_get_gpio_in(DEVICE(porgates), ast2700_gic_intcmap[i].ptr[dev] + inde= x); + } } } =20 @@ -1098,6 +1121,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) =20 /* IO Expander */ for (i =3D 0; i < sc->ioexp_num; i++) { + AspeedI2CClass *i2c_ctl; + qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { return; @@ -1128,6 +1153,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); =20 + /* I2C */ + i2c_ctl =3D ASPEED_I2C_GET_CLASS(&s->ioexp[i].i2c); + for (int j =3D 0; j < i2c_ctl->num_busses; j++) { + /* + * For I2C on AST1700: + * I2C bus interrupts are connected to the OR gate from bit 0 = to bit + * 15, and the OR gate output pin is connected to the input pi= n of + * GICINT192 of IO expander Interrupt controller (INTC2/3). Th= en, + * the output pin is connected to the INTC (CPU Die) input pin= , and + * its output pin is connected to the GIC. + * + * I2C bus 0 is connected to the OR gate at bit 0. + * I2C bus 15 is connected to the OR gate at bit 15. + */ + irq =3D aspeed_soc_ast2700_get_irq_index(s, + ASPEED_DEV_IOEXP0_I2C += i, + j); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].i2c.busses[j]), + 0, irq); + } } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 83fb906bdc..ca84068bb4 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -1261,6 +1261,7 @@ static void aspeed_i2c_realize(DeviceState *dev, Erro= r **errp) static const Property aspeed_i2c_properties[] =3D { DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_STRING("bus-label", AspeedI2CState, bus_label), }; =20 static void aspeed_i2c_class_init(ObjectClass *klass, const void *data) @@ -1421,14 +1422,28 @@ static void aspeed_i2c_bus_realize(DeviceState *dev= , Error **errp) { AspeedI2CBus *s =3D ASPEED_I2C_BUS(dev); AspeedI2CClass *aic; - g_autofree char *name =3D g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s= ->id); - g_autofree char *pool_name =3D g_strdup_printf("%s.pool", name); + g_autofree char *name =3D NULL; + g_autofree char *pool_name =3D NULL; =20 if (!s->controller) { error_setg(errp, TYPE_ASPEED_I2C_BUS ": 'controller' link not set"= ); return; } =20 + /* + * I2C bus naming: + * - Empty bus_label -> BMC internal controller, use default name. + * - Non-empty bus_label -> external/addon controller, prefix with l= abel + * to avoid conflicts and show bus origin. + */ + if (!s->controller->bus_label || (strlen(s->controller->bus_label) =3D= =3D 0)) { + name =3D g_strdup_printf(TYPE_ASPEED_I2C_BUS ".%d", s->id); + } else { + name =3D g_strdup_printf("aspeed.%s.i2c.bus.%d", + s->controller->bus_label, s->id); + } + pool_name =3D g_strdup_printf("%s.pool", name); + aic =3D ASPEED_I2C_GET_CLASS(s->controller); =20 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 24 Dec 2025 09:42:10 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 15/19] hw/arm/aspeed: Attach WDT device to AST1700 model Date: Wed, 24 Dec 2025 09:41:54 +0800 Message-ID: <20251224014203.756264-16-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540706329158500 From: Kane-Chen-AS Connect the WDT device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 4 ++++ hw/arm/aspeed_ast1700.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index d4b7abee7d..f43c0c5475 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -15,8 +15,11 @@ #include "hw/i2c/aspeed_i2c.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" +#include "hw/watchdog/wdt_aspeed.h" #include "hw/char/serial-mm.h" =20 +#define AST1700_WDT_NUM 9 + #define TYPE_ASPEED_AST1700 "aspeed.ast1700" =20 OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700) @@ -36,6 +39,7 @@ struct AspeedAST1700SoCState { AspeedSCUState scu; AspeedGPIOState gpio; AspeedI2CState i2c; + AspeedWDTState wdt[AST1700_WDT_NUM]; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index fad3b86e8d..9fb84dd159 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -25,6 +25,7 @@ enum { ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, + ASPEED_AST1700_DEV_WDT, ASPEED_AST1700_DEV_SPI0_MEM, }; =20 @@ -37,6 +38,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, + [ASPEED_AST1700_DEV_WDT] =3D 0x00C37000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, }; =20 @@ -129,6 +131,22 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) memory_region_add_subregion(&s->iomem, aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_C= TRL], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0= )); + /* WDT */ + for (int i =3D 0; i < AST1700_WDT_NUM; i++) { + AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); + hwaddr wdt_offset =3D aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_= WDT] + + i * awc->iosize; + + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), + errp); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + wdt_offset, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]),= 0)); + } + } =20 static void aspeed_ast1700_instance_init(Object *obj) @@ -163,6 +181,12 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); =20 + /* WDT */ + for (int i =3D 0; i < AST1700_WDT_NUM; i++) { + object_initialize_child(obj, "ioexp-wdt[*]", + &s->wdt[i], "aspeed.wdt-ast2700"); + } + return; } =20 --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766540705; cv=none; d=zohomail.com; s=zohoarc; b=Lkp6478ygQM7bqEExlmG23T4OvnuSk3uqiuisXud7GWGAiA+bvzGPmo/T5xgh1+JwopKWk2xHRyOyaxrKfygvfc3iW1uhEuu89vKyuHPJz0P9yYtZmbSof5t6COk5kCkU0LO86dktRyY40fpt6lvicjbCCyqkXwZVxGT9qiMqGo= ARC-Message-Signature: i=1; a=rsa-sha256; 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Tue, 23 Dec 2025 20:43:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDug-00022s-I0; Tue, 23 Dec 2025 20:43:43 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDuf-0006HF-7R; Tue, 23 Dec 2025 20:43:42 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:10 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 16/19] hw/arm/aspeed: Attach PWM device to AST1700 model Date: Wed, 24 Dec 2025 09:41:55 +0800 Message-ID: <20251224014203.756264-17-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540706318158500 From: Kane-Chen-AS Connect the PWM device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index f43c0c5475..7292719dc2 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -14,6 +14,7 @@ #include "hw/gpio/aspeed_gpio.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/misc/aspeed_pwm.h" #include "hw/ssi/aspeed_smc.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/char/serial-mm.h" @@ -39,6 +40,7 @@ struct AspeedAST1700SoCState { AspeedSCUState scu; AspeedGPIOState gpio; AspeedI2CState i2c; + AspeedPWMState pwm; AspeedWDTState wdt[AST1700_WDT_NUM]; }; =20 diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 9fb84dd159..5a2552aa25 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -18,6 +18,7 @@ =20 enum { ASPEED_AST1700_DEV_SPI0, + ASPEED_AST1700_DEV_PWM, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, @@ -31,6 +32,7 @@ enum { =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, + [ASPEED_AST1700_DEV_PWM] =3D 0x000C0000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, @@ -124,6 +126,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0)= ); =20 + /* PWM */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_PWM], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pwm), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -177,6 +187,9 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c, "aspeed.i2c-ast2700"); =20 + /* PWM */ + object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766540697732259.2432326055605; Tue, 23 Dec 2025 17:44:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vYDuk-00026C-B8; Tue, 23 Dec 2025 20:43:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDui-00025P-Qd; Tue, 23 Dec 2025 20:43:45 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vYDuh-0006HF-AR; Tue, 23 Dec 2025 20:43:44 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Dec 2025 09:42:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 17/19] hw/arm/aspeed: Attach SGPIOM device to AST1700 model Date: Wed, 24 Dec 2025 09:41:56 +0800 Message-ID: <20251224014203.756264-18-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540706326158500 From: Kane-Chen-AS Connect the SGPIOM device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 3 +++ hw/arm/aspeed_ast1700.c | 21 +++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 7292719dc2..490f2a3b05 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -12,6 +12,7 @@ #include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" #include "hw/gpio/aspeed_gpio.h" +#include "hw/gpio/aspeed_sgpio.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/misc/aspeed_pwm.h" @@ -19,6 +20,7 @@ #include "hw/watchdog/wdt_aspeed.h" #include "hw/char/serial-mm.h" =20 +#define AST1700_SGPIO_NUM 2 #define AST1700_WDT_NUM 9 =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" @@ -39,6 +41,7 @@ struct AspeedAST1700SoCState { AspeedADCState adc; AspeedSCUState scu; AspeedGPIOState gpio; + AspeedSGPIOState sgpiom[AST1700_SGPIO_NUM]; AspeedI2CState i2c; AspeedPWMState pwm; AspeedWDTState wdt[AST1700_WDT_NUM]; diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 5a2552aa25..ca0ce4e2c2 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -23,6 +23,8 @@ enum { ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_GPIO, + ASPEED_AST1700_DEV_SGPIOM0, + ASPEED_AST1700_DEV_SGPIOM1, ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, @@ -37,6 +39,8 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, + [ASPEED_AST1700_DEV_SGPIOM0] =3D 0x00C0C000, + [ASPEED_AST1700_DEV_SGPIOM1] =3D 0x00C0D000, [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, @@ -141,6 +145,17 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) memory_region_add_subregion(&s->iomem, aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_C= TRL], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0= )); + + /* SGPIOM */ + for (int i =3D 0; i < AST1700_SGPIO_NUM; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SGPIOM0 + = i], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom[i]), = 0)); + } + /* WDT */ for (int i =3D 0; i < AST1700_WDT_NUM; i++) { AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); @@ -194,6 +209,12 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); =20 + /* SGPIOM */ + for (int i =3D 0; i < AST1700_SGPIO_NUM; i++) { + object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom[i], + "aspeed.sgpio-ast2700"); + } + /* WDT */ for (int i =3D 0; i < AST1700_WDT_NUM; i++) { object_initialize_child(obj, "ioexp-wdt[*]", --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 24 Dec 2025 09:42:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS Subject: [PATCH v4 18/19] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Date: Wed, 24 Dec 2025 09:41:57 +0800 Message-ID: <20251224014203.756264-19-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540688375158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS AST1700 exposes more I3C buses than the current dummy I3C model provides. When Linux probes the I3C devices on AST1700 this mismatch can trigger a kernel panic. Model the I3C block as an unimplemented device to make the missing functionality explicit and avoid unexpected side effects. This wires up the I3C interrupt lines for the IO expanders and adds the corresponding device entries for the AST1700 model. No functional I3C emulation is provided yet; this only prevents crashes and documents the missing piece. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 3 +++ include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed_ast1700.c | 15 +++++++++++++++ hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++-- 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 490f2a3b05..874b4d63fe 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -19,6 +19,7 @@ #include "hw/ssi/aspeed_smc.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/char/serial-mm.h" +#include "hw/misc/unimp.h" =20 #define AST1700_SGPIO_NUM 2 #define AST1700_WDT_NUM 9 @@ -45,6 +46,8 @@ struct AspeedAST1700SoCState { AspeedI2CState i2c; AspeedPWMState pwm; AspeedWDTState wdt[AST1700_WDT_NUM]; + + UnimplementedDeviceState i3c; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 4ea2521041..b185b04186 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -294,6 +294,8 @@ enum { ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, + ASPEED_DEV_IOEXP0_I3C, + ASPEED_DEV_IOEXP1_I3C, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index ca0ce4e2c2..5f3c56e6cc 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -15,6 +15,7 @@ =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 #define AST1700_SOC_SRAM_SIZE 0x00040000 +#define AST1700_SOC_I3C_SIZE 0x00010000 =20 enum { ASPEED_AST1700_DEV_SPI0, @@ -26,6 +27,7 @@ enum { ASPEED_AST1700_DEV_SGPIOM0, ASPEED_AST1700_DEV_SGPIOM1, ASPEED_AST1700_DEV_I2C, + ASPEED_AST1700_DEV_I3C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_WDT, @@ -42,6 +44,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SGPIOM0] =3D 0x00C0C000, [ASPEED_AST1700_DEV_SGPIOM1] =3D 0x00C0D000, [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, + [ASPEED_AST1700_DEV_I3C] =3D 0x00C20000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_WDT] =3D 0x00C37000, @@ -172,6 +175,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]),= 0)); } =20 + /* I3C */ + qdev_prop_set_string(DEVICE(&s->i3c), "name", "ioexp-i3c"); + qdev_prop_set_uint64(DEVICE(&s->i3c), "size", AST1700_SOC_I3C_SIZE); + sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp); + memory_region_add_subregion_overlap(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I3C], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i3c), 0), + -1000); } =20 static void aspeed_ast1700_instance_init(Object *obj) @@ -221,6 +232,10 @@ static void aspeed_ast1700_instance_init(Object *obj) &s->wdt[i], "aspeed.wdt-ast2700"); } =20 + /* I3C */ + object_initialize_child(obj, "ioexp-i3c[*]", &s->i3c, + TYPE_UNIMPLEMENTED_DEVICE); + return; } =20 diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index ca3adf9a50..0807481162 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -206,7 +206,9 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP0_I3C] =3D 199, [ASPEED_DEV_IOEXP1_I2C] =3D 200, + [ASPEED_DEV_IOEXP1_I3C] =3D 201, }; =20 /* GICINT 128 */ @@ -275,12 +277,24 @@ static const int ast2700_gic198_intcmap[] =3D { [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GINTC 199 */ +static const int ast2700_gic199_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I3C] =3D 0, /* 0 - 15 */ +}; + /* Secondary AST1700 Interrupts */ /* A1: GINTC 200 */ static const int ast2700_gic200_intcmap[] =3D { [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ }; =20 +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 201 */ +static const int ast2700_gic201_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I3C] =3D 0, /* 0 - 15 */ +}; + /* GICINT 128 ~ 136 */ /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { @@ -298,9 +312,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcm= ap[] =3D { {196, 1, 4, ast2700_gic132_gic196_intcmap}, {197, 1, 5, ast2700_gic133_gic197_intcmap}, {198, 2, 0, ast2700_gic198_intcmap}, - {199, 1, 7, NULL}, + {199, 2, 1, ast2700_gic199_intcmap}, {200, 3, 0, ast2700_gic200_intcmap}, - {201, 1, 9, NULL}, + {201, 3, 1, ast2700_gic201_intcmap}, {128, 0, 1, ast2700_gic128_gic192_intcmap}, {129, 0, 2, NULL}, {130, 0, 3, ast2700_gic130_gic194_intcmap}, --=20 2.43.0 From nobody Sat Feb 7 05:48:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 24 Dec 2025 09:42:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Dec 2025 09:42:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Kane-Chen-AS Subject: [PATCH v4 19/19] hw/arm/aspeed: Enable AST1700 IO expander support Date: Wed, 24 Dec 2025 09:41:58 +0800 Message-ID: <20251224014203.756264-20-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251224014203.756264-1-kane_chen@aspeedtech.com> References: <20251224014203.756264-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766540682282158500 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Set ioexp_num to 2 to enable AST1700 IO expander support. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- hw/arm/aspeed_ast27x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 0807481162..2eb857b8e0 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1260,7 +1260,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->macs_num =3D 3; sc->uarts_num =3D 13; sc->num_cpus =3D 4; - sc->ioexp_num =3D 0; + sc->ioexp_num =3D 2; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; sc->memmap =3D aspeed_soc_ast2700_memmap; --=20 2.43.0