From nobody Wed Feb 11 00:37:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766407611231560.0998264068493; Mon, 22 Dec 2025 04:46:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vXfIq-0006R2-Mv; Mon, 22 Dec 2025 07:46:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vXfIR-0006J7-DA; Mon, 22 Dec 2025 07:45:55 -0500 Received: from zg8tmtyylji0my4xnjqumte4.icoremail.net ([162.243.164.118]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vXfIO-00073u-5z; Mon, 22 Dec 2025 07:45:54 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwBnbZl7PUlpvOwsBA--.117S2; Mon, 22 Dec 2025 20:45:47 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwBXr+xyPUlpieINAA--.25982S8; Mon, 22 Dec 2025 20:45:45 +0800 (CST) From: Tao Tang To: Paolo Bonzini , Fabiano Rosas , Laurent Vivier , Eric Auger , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh , CLEMENT MATHIEU--DRIF , Tao Tang Subject: [RFC v7 5/7] hw/arm/smmuv3-common: Add STE/CD set helpers for repeated field setup Date: Mon, 22 Dec 2025 20:45:15 +0800 Message-Id: <20251222124517.3948679-6-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251222124517.3948679-1-tangtao1634@phytium.com.cn> References: <20251222124517.3948679-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwBXr+xyPUlpieINAA--.25982S8 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQAMBWlIVJoHawAAsL Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoWxuF43Cr4kJrWkWry3ZrWxCrg_yoWrtF4Dpr yxAryDXw17CF12kw1fJF4UKFsxZrn2q34DGryxKrsrC3ZxJrn7WFZ7KFWrJFyUuanYqFy0 krsIgrWUWa9rCrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=162.243.164.118; envelope-from=tangtao1634@phytium.com.cn; helo=zg8tmtyylji0my4xnjqumte4.icoremail.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1766407616138158500 Content-Type: text/plain; charset="utf-8" This change introduces STE_SET_* and CD_SET_* helpers to centralize and simplify repeated field setting logic. Signed-off-by: Tao Tang Reviewed-by: Pierrick Bouvier --- include/hw/arm/smmuv3-common.h | 79 ++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index 7f7dd02221..0c6c162288 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -100,6 +100,37 @@ REG32(STE_7, 28) #define STE_CFG_ABORT(config) (!(config & 0x4)) #define STE_CFG_BYPASS(config) (config =3D=3D 0x4) =20 +/* Update STE fields */ +#define STE_SET_VALID(ste, v) = \ + ((ste)->word[0] =3D FIELD_DP32((ste)->word[0], STE_0, VALID, (v))) +#define STE_SET_CONFIG(ste, v) = \ + ((ste)->word[0] =3D FIELD_DP32((ste)->word[0], STE_0, CONFIG, (v))) + +#define STE_SET_CTXPTR(ste, v) do { = \ + (ste)->word[0] =3D FIELD_DP32((ste)->word[0], STE_0, CTXPTR_LO, (v) >>= 6); \ + (ste)->word[1] =3D FIELD_DP32((ste)->word[1], STE_1, CTXPTR_HI, (v) >>= 32); \ +} while (0) +#define STE_SET_S2T0SZ(ste, v) = \ + ((ste)->word[5] =3D FIELD_DP32((ste)->word[5], STE_5, S2T0SZ, (v))) +#define STE_SET_S2SL0(ste, v) = \ + ((ste)->word[5] =3D FIELD_DP32((ste)->word[5], STE_5, S2SL0, (v))) +#define STE_SET_S2TG(ste, v) = \ + ((ste)->word[5] =3D FIELD_DP32((ste)->word[5], STE_5, S2TG, (v))) +#define STE_SET_S2PS(ste, v) = \ + ((ste)->word[5] =3D FIELD_DP32((ste)->word[5], STE_5, S2PS, (v))) +#define STE_SET_S2AA64(ste, v) = \ + ((ste)->word[5] =3D FIELD_DP32((ste)->word[5], STE_5, S2AA64, (v))) +#define STE_SET_S2ENDI(ste, v) = \ + ((ste)->word[5] =3D FIELD_DP32((ste)->word[5], STE_5, S2ENDI, (v))) +#define STE_SET_S2AFFD(ste, v) = \ + ((ste)->word[5] =3D FIELD_DP32((ste)->word[5], STE_5, S2AFFD, (v))) +#define STE_SET_S2S(ste, v) = \ + ((ste)->word[5] =3D FIELD_DP32((ste)->word[5], STE_5, S2S, (v))) +#define STE_SET_S2TTB(ste, v) do { = \ + (ste)->word[6] =3D FIELD_DP32((ste)->word[6], STE_6, S2TTB_LO, (v) >> = 4); \ + (ste)->word[7] =3D FIELD_DP32((ste)->word[7], STE_7, S2TTB_HI, (v) >> = 32); \ +} while (0) + /* CD fields */ =20 REG32(CD_0, 0) @@ -169,6 +200,54 @@ REG32(CD_5, 20) (((uint64_t)FIELD_EX32((x)->word[3], CD_3, TTB0_HI) << 32) | \ ((uint64_t)FIELD_EX32((x)->word[2], CD_2, TTB0_LO) << 4))) =20 +/* Update CD fields */ +#define CD_SET_VALID(cd, v) = \ + ((cd)->word[0] =3D FIELD_DP32((cd)->word[0], CD_0, VALID, (v))) +#define CD_SET_ASID(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, ASID, (v))) +#define CD_SET_TTB(cd, sel, v) do { = \ + if (sel) { = \ + (cd)->word[4] =3D FIELD_DP32((cd)->word[4], CD_4, TTB1_LO, (v) >> = 4); \ + (cd)->word[5] =3D FIELD_DP32((cd)->word[5], CD_5, TTB1_HI, (v) >> = 32); \ + } else { = \ + (cd)->word[2] =3D FIELD_DP32((cd)->word[2], CD_2, TTB0_LO, (v) >> = 4); \ + (cd)->word[3] =3D FIELD_DP32((cd)->word[3], CD_3, TTB0_HI, (v) >> = 32); \ + } = \ +} while (0) + +#define CD_SET_TSZ(cd, sel, v) = \ + ((cd)->word[0] =3D (sel) ? FIELD_DP32((cd)->word[0], CD_0, TSZ1, (v)) = : \ + FIELD_DP32((cd)->word[0], CD_0, TSZ0, (v))) +#define CD_SET_TG(cd, sel, v) = \ + ((cd)->word[0] =3D (sel) ? FIELD_DP32((cd)->word[0], CD_0, TG1, (v)) := \ + FIELD_DP32((cd)->word[0], CD_0, TG0, (v))) +#define CD_SET_EPD(cd, sel, v) = \ + ((cd)->word[0] =3D (sel) ? FIELD_DP32((cd)->word[0], CD_0, EPD1, (v)) = : \ + FIELD_DP32((cd)->word[0], CD_0, EPD0, (v))) +#define CD_SET_ENDI(cd, v) = \ + ((cd)->word[0] =3D FIELD_DP32((cd)->word[0], CD_0, ENDI, (v))) +#define CD_SET_IPS(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, IPS, (v))) +#define CD_SET_AFFD(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, AFFD, (v))) +#define CD_SET_TBI(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, TBI, (v))) +#define CD_SET_HD(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, HD, (v))) +#define CD_SET_HA(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, HA, (v))) +#define CD_SET_S(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, S, (v))) +#define CD_SET_R(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, R, (v))) +#define CD_SET_A(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, A, (v))) +#define CD_SET_AARCH64(cd, v) = \ + ((cd)->word[1] =3D FIELD_DP32((cd)->word[1], CD_1, AARCH64, (v))) +#define CD_SET_NSCFG(cd, sel, v) = \ + ((sel) ? ((cd)->word[4] =3D FIELD_DP32((cd)->word[4], CD_4, NSCFG1, (v= ))) : \ + ((cd)->word[2] =3D FIELD_DP32((cd)->word[2], CD_2, NSCFG0, (v= )))) + /* MMIO Registers */ =20 REG32(IDR0, 0x0) --=20 2.34.1