From nobody Sat Feb 7 05:32:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766326969; cv=none; d=zohomail.com; s=zohoarc; b=PH9HNJpuiWJsqR7rq+fke5XOSeCPmF0VCeH7KB/FM9DTqERneRbwoiBeOACsDKL61WbvT4ht+/apIUzMtrRIgA0zt2ZSgsoEsQ3H50XXOyaHrevZMKE+aclwyoD1tWNwh+iojuqRWpCOCHpTMDPLzjFs6pVRfGSUDyyXurS99ZE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766326969; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Yuqz5F8k2afpuMuB2VmoqlA/DV3peZ8kzfMWUl+iSUk=; b=V7tAr8kUNq5gckPcyiBPWLDlTDIeMPXek79gtojE8XhKsoM+9Uqh3TgAcLeyC2PtpaCfbzXKRdqb7DydZNAdBmf20dZmTZcCQfTInzvE/MfJfTVfnrVInRPYvJlV34QBhX3rcbUfKaacVwv1D2ZhO4AroFVXO3L92SPc1+41Tho= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766326969351172.62077065789538; Sun, 21 Dec 2025 06:22:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vXKJj-0004A8-Sb; Sun, 21 Dec 2025 09:21:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vXKIu-0003Ej-96 for qemu-devel@nongnu.org; Sun, 21 Dec 2025 09:21:04 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vXKIs-0000cg-MY for qemu-devel@nongnu.org; Sun, 21 Dec 2025 09:21:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=Yuqz5F8k2afpuMuB2VmoqlA/DV3peZ8kzfMWUl+iSUk=; b=EyWb6kiREgPewz7 SExfhmoaSklvlf7EDCc17BN1K/m0ccSQvYFAAKQFaRguK1KGG/U9T+mKqIHZ4bhVQkIpoP3EiR3sR UdNeapUQcAdNUrVZYcs15zR+G6jjtaAUYekniAj7MRBYL45izKzTtbtJVjwhsqD+qkSDikjnM4Ieo 4g=; Date: Sun, 21 Dec 2025 15:23:11 +0100 Subject: [PATCH v2 07/14] target/riscv: Replace TYPE_RISCV_CPU_BASE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-hw-riscv-cpu-int-v2-7-eb49d72c5b2f@rev.ng> References: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> In-Reply-To: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326969614158500 TYPE_RISCV_CPU_BASE is used only to initialize the correct default machine for 3 machines. Replace it with a runtime check. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- include/hw/riscv/virt.h | 11 +++++++++++ target/riscv/cpu.h | 6 ------ hw/riscv/microblaze-v-generic.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 2 +- 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7b4c2c8b7d..3a17641078 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,6 +19,7 @@ #ifndef HW_RISCV_VIRT_H #define HW_RISCV_VIRT_H =20 +#include "qemu/target-info.h" #include "hw/boards.h" #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" @@ -137,6 +138,16 @@ bool virt_is_iommu_sys_enabled(RISCVVirtState *s); void virt_acpi_setup(RISCVVirtState *vms); uint32_t imsic_num_bits(uint32_t count); =20 +static inline const char *virt_default_cpu_type(void) +{ + if (target_riscv64()) { + return TYPE_RISCV_CPU_BASE64; + } else { + return TYPE_RISCV_CPU_BASE32; + } +} + + /* * The virt machine physical address space used by some of the devices * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616406f07f..da2bc554d3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -39,12 +39,6 @@ typedef struct CPUArchState CPURISCVState; =20 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU =20 -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - /* * b0: Whether a instruction always raise a store AMO or not. */ diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index 0df276f9fb..0222ff0c06 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -26,6 +26,7 @@ #include "hw/char/xilinx_uartlite.h" #include "hw/misc/unimp.h" #include "hw/riscv/machines-qom.h" +#include "hw/riscv/virt.h" =20 #define LMB_BRAM_SIZE (128 * KiB) #define MEMORY_BASEADDR 0x80000000 @@ -183,7 +184,7 @@ static void mb_v_generic_machine_init(MachineClass *mc) mc->init =3D mb_v_generic_init; mc->min_cpus =3D 1; mc->max_cpus =3D 1; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D virt_default_cpu_type(); mc->default_cpus =3D 1; } =20 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 69eb3dfc24..7d1a642a78 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -34,6 +34,7 @@ #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/riscv/machines-qom.h" +#include "hw/riscv/virt.h" #include "hw/char/riscv_htif.h" #include "hw/intc/riscv_aclint.h" #include "chardev/char.h" @@ -351,7 +352,7 @@ static void spike_machine_class_init(ObjectClass *oc, c= onst void *data) mc->init =3D spike_board_init; mc->max_cpus =3D SPIKE_CPUS_MAX; mc->is_default =3D true; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D virt_default_cpu_type(); mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f42fffb223..6f6164e05d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1922,7 +1922,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->desc =3D "RISC-V VirtIO board"; mc->init =3D virt_machine_init; mc->max_cpus =3D VIRT_CPUS_MAX; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D virt_default_cpu_type(); mc->block_default_type =3D IF_VIRTIO; mc->no_cdrom =3D 1; mc->pci_allow_0_address =3D true; --=20 2.51.0