From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766326856; cv=none; d=zohomail.com; s=zohoarc; b=PN3hkFCdgk0MalSZoFn9cmdST6j0rhHTPv9pR0h/lcjCVPMAhDVoPNdCemMJwIJjptx43Fgf9S5VMj6GdLyvRcgFTBmtdcJ4zLNOT11zIjkQMuHo4p+7ApUz/QpH6GGV7AmvZmsAmJ1oy4WV8d2o+uZq1UXZr8YV+7mf5my8Ks8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766326856; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=FuTwyO7LpL4N7aVC0QhERrGffYKhjy9Ll3iBxAHD1to=; b=XvAEcDXyIJuXqDhmqzdC+VKr6hLQtko3YzecFMCh/NKhgNzLRkHnXLbvSjumEmU6RrImnO0N8YhW8IPaE2GdW3Q4vt7vR1h+J+j/vAYBoX7X8WYdw5Vy6bY94JU7uKI4uXVUQeRw19zW98MAttCg5RPwMOrjv52yUJHiabEKpqU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766326856180239.57781022959125; Sun, 21 Dec 2025 06:20:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vXKIK-0002qv-4y; Sun, 21 Dec 2025 09:20:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vXKID-0002jf-3Z for qemu-devel@nongnu.org; Sun, 21 Dec 2025 09:20:21 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vXKIB-0000X9-OX for qemu-devel@nongnu.org; Sun, 21 Dec 2025 09:20:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=FuTwyO7LpL4N7aVC0QhERrGffYKhjy9Ll3iBxAHD1to=; b=wkQd6ydpegdvnRp u9Ud4uiH/kRRKdB3OjU56lteOyUHd+LCtlwBANWswQezyxuwPCFxUKn44YD7LzQ+j5WzyGDuOQcc6 gh50HVk1J88xI2FSvqoMSgHDv0broiPeFdbWzhcMq2xW/tDyLzHbtcRWt4FiqsPX7r6EmScWHliVh zg=; Date: Sun, 21 Dec 2025 15:23:05 +0100 Subject: [PATCH v2 01/14] hw/riscv: Register generic riscv[32|64] QOM interfaces MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-hw-riscv-cpu-int-v2-1-eb49d72c5b2f@rev.ng> References: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> In-Reply-To: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326857288158500 Defines generic 32- and 64-bit riscv machine interfaces for machines to implement. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- include/hw/riscv/machines-qom.h | 20 ++++++++++++++++++++ target-info-qom.c | 9 +++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qo= m.h new file mode 100644 index 0000000000..6e2c542c87 --- /dev/null +++ b/include/hw/riscv/machines-qom.h @@ -0,0 +1,20 @@ +/* + * QOM type definitions for riscv32 / riscv64 machines + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_RISCV_MACHINES_QOM_H +#define HW_RISCV_MACHINES_QOM_H + +#include "hw/boards.h" + +#define TYPE_TARGET_RISCV32_MACHINE \ + "target-info-riscv32-machine" + +#define TYPE_TARGET_RISCV64_MACHINE \ + "target-info-riscv64-machine" + +#endif diff --git a/target-info-qom.c b/target-info-qom.c index 7fd58d2481..aaaebd55c7 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qom/object.h" #include "hw/arm/machines-qom.h" +#include "hw/riscv/machines-qom.h" =20 static const TypeInfo target_info_types[] =3D { { @@ -19,6 +20,14 @@ static const TypeInfo target_info_types[] =3D { .name =3D TYPE_TARGET_AARCH64_MACHINE, .parent =3D TYPE_INTERFACE, }, + { + .name =3D TYPE_TARGET_RISCV32_MACHINE, + .parent =3D TYPE_INTERFACE, + }, + { + .name =3D TYPE_TARGET_RISCV64_MACHINE, + .parent =3D TYPE_INTERFACE, + }, }; =20 DEFINE_TYPES(target_info_types) --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766326840; cv=none; d=zohomail.com; s=zohoarc; b=IXkKiLSeE1RKcfaXUu6mHlW0NvwjQjcAAxcNF95LpZYo8GUQ7WK5Y8/hTsHeF1UTStlWi4FnRhVA2s4iYz83/rMRfFYE1gXFNGy1gD9rifzSurwhk1kkSLERqmYeb9E+weEUzArjaqU0TUKp2NRdGuzaDomUlrfLdQ7BjCiPNHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766326840; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ZSd74nI47x+VGZXv4Sf8+9YzvaVsfHTY/tOLcQHDpBs=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326841400158500 Adds macros and global interfaces for defining machines available only in qemu-system-riscv32, qemu-system-riscv64, or both. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- include/hw/riscv/machines-qom.h | 26 ++++++++++++++++++++++++++ target/riscv/machine.c | 17 +++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qo= m.h index 6e2c542c87..2254b2dbcc 100644 --- a/include/hw/riscv/machines-qom.h +++ b/include/hw/riscv/machines-qom.h @@ -17,4 +17,30 @@ #define TYPE_TARGET_RISCV64_MACHINE \ "target-info-riscv64-machine" =20 +/* + * Interfaces specifiying wether a given QOM object is available in + * qemu-system-riscv32, qemu-riscv-riscv64, or both. + */ + +extern InterfaceInfo riscv32_machine_interfaces[]; +extern InterfaceInfo riscv64_machine_interfaces[]; +extern InterfaceInfo riscv32_64_machine_interfaces[]; + +/* + * Helper macros for defining machines available in qemu-system-riscv32, + * qemu-system-riscv64, or both. + */ + +#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv32_machine_interfaces) + +#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv64_machine_interfaces) + +#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv32_64_machine_interfaces) + #endif diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 13eb292c4a..3d2e3968fd 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -23,6 +23,7 @@ #include "migration/cpu.h" #include "exec/icount.h" #include "target/riscv/debug.h" +#include "hw/riscv/machines-qom.h" =20 static bool pmp_needed(void *opaque) { @@ -503,3 +504,19 @@ const VMStateDescription vmstate_riscv_cpu =3D { NULL } }; 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Date: Sun, 21 Dec 2025 15:23:07 +0100 Subject: [PATCH v2 03/14] hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-hw-riscv-cpu-int-v2-3-eb49d72c5b2f@rev.ng> References: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> In-Reply-To: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326899483158500 Register machines able to run in qemu-system-riscv32, qemu-system-riscv64, or both. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- hw/riscv/microblaze-v-generic.c | 3 ++- hw/riscv/microchip_pfsoc.c | 2 ++ hw/riscv/opentitan.c | 2 ++ hw/riscv/shakti_c.c | 2 ++ hw/riscv/sifive_e.c | 2 ++ hw/riscv/sifive_u.c | 2 ++ hw/riscv/spike.c | 2 ++ hw/riscv/virt.c | 3 +++ hw/riscv/xiangshan_kmh.c | 2 ++ 9 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index e863c50cbc..0df276f9fb 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -25,6 +25,7 @@ #include "system/address-spaces.h" #include "hw/char/xilinx_uartlite.h" #include "hw/misc/unimp.h" +#include "hw/riscv/machines-qom.h" =20 #define LMB_BRAM_SIZE (128 * KiB) #define MEMORY_BASEADDR 0x80000000 @@ -186,4 +187,4 @@ static void mb_v_generic_machine_init(MachineClass *mc) mc->default_cpus =3D 1; } =20 -DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init) +DEFINE_MACHINE_RISCV32_64("amd-microblaze-v-generic", mb_v_generic_machine= _init) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index bc4f409c19..51b53121c5 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -49,6 +49,7 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/machines-qom.h" #include "hw/riscv/microchip_pfsoc.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -748,6 +749,7 @@ static const TypeInfo microchip_icicle_kit_machine_type= info =3D { .class_init =3D microchip_icicle_kit_machine_class_init, .instance_init =3D microchip_icicle_kit_machine_instance_init, .instance_size =3D sizeof(MicrochipIcicleKitState), + .interfaces =3D riscv64_machine_interfaces, }; =20 static void microchip_icicle_kit_machine_init_register_types(void) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index d369a8a7dc..e8c6829365 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -26,6 +26,7 @@ #include "hw/boards.h" #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "qemu/units.h" #include "system/system.h" #include "system/address-spaces.h" @@ -335,6 +336,7 @@ static const TypeInfo open_titan_types[] =3D { .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(OpenTitanState), .class_init =3D opentitan_machine_class_init, + .interfaces =3D riscv32_machine_interfaces, } }; =20 diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 3e7f441172..d4cf72de3e 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "hw/boards.h" #include "hw/riscv/shakti_c.h" +#include "hw/riscv/machines-qom.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/intc/sifive_plic.h" @@ -92,6 +93,7 @@ static const TypeInfo shakti_c_machine_type_info =3D { .class_init =3D shakti_c_machine_class_init, .instance_init =3D shakti_c_machine_instance_init, .instance_size =3D sizeof(ShaktiCMachineState), + .interfaces =3D riscv64_machine_interfaces, }; =20 static void shakti_c_machine_type_info_register(void) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 7baed1958e..7ed419cf69 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -40,6 +40,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -167,6 +168,7 @@ static const TypeInfo sifive_e_machine_typeinfo =3D { .class_init =3D sifive_e_machine_class_init, .instance_init =3D sifive_e_machine_instance_init, .instance_size =3D sizeof(SiFiveEState), + .interfaces =3D riscv32_64_machine_interfaces, }; =20 static void sifive_e_machine_init_register_types(void) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2d27e925e8..2ff2059bb9 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -51,6 +51,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -742,6 +743,7 @@ static const TypeInfo sifive_u_machine_typeinfo =3D { .class_init =3D sifive_u_machine_class_init, .instance_init =3D sifive_u_machine_instance_init, .instance_size =3D sizeof(SiFiveUState), + .interfaces =3D riscv32_64_machine_interfaces, }; =20 static void sifive_u_machine_init_register_types(void) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ce190f6c62..69eb3dfc24 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -33,6 +33,7 @@ #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/riscv_htif.h" #include "hw/intc/riscv_aclint.h" #include "chardev/char.h" @@ -374,6 +375,7 @@ static const TypeInfo spike_machine_typeinfo =3D { .class_init =3D spike_machine_class_init, .instance_init =3D spike_machine_instance_init, .instance_size =3D sizeof(SpikeState), + .interfaces =3D riscv32_64_machine_interfaces, }; =20 static void spike_machine_init_register_types(void) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index aa4dd91325..f42fffb223 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -36,6 +36,7 @@ #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/riscv/numa.h" #include "kvm/kvm_riscv.h" #include "hw/firmware/smbios.h" @@ -1989,6 +1990,8 @@ static const TypeInfo virt_machine_typeinfo =3D { .instance_size =3D sizeof(RISCVVirtState), .interfaces =3D (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, { } }, }; diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index a95fd6174f..4d7e191098 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -41,6 +41,7 @@ #include "hw/riscv/boot.h" #include "hw/riscv/xiangshan_kmh.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/machines-qom.h" #include "system/system.h" =20 static const MemMapEntry xiangshan_kmh_memmap[] =3D { @@ -211,6 +212,7 @@ static const TypeInfo xiangshan_kmh_machine_info =3D { .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(XiangshanKmhState), .class_init =3D xiangshan_kmh_machine_class_init, + .interfaces =3D riscv64_machine_interfaces, }; =20 static void xiangshan_kmh_machine_register_types(void) --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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bh=OjzAigogEAv0CrfjDAeEcEi2p6Uk8nGYiUhFSHcR+rE=; b=DJdmIkiP6Xlc622 kBMg7VwOz505bDajtJWg42rfTdOJp6Bt2qLyr0TvlsbEA1HaY4Cxa3ccy2hDcqR+qm3NJoQxmzBGu HCu+M7EbwOltaNKuBV2/ir/1oM2jA7c4/mBOB/kZix4hqxWFpgZAd+0FntGOC6W46oIQVC0cd3z++ Hs=; Date: Sun, 21 Dec 2025 15:23:08 +0100 Subject: [PATCH v2 04/14] hw/core: Add riscv[32|64] to "none" machine MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-hw-riscv-cpu-int-v2-4-eb49d72c5b2f@rev.ng> References: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> In-Reply-To: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326907531158500 Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- hw/core/null-machine.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 67b769bd3e..77e4ed60e6 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -17,6 +17,7 @@ #include "system/address-spaces.h" #include "hw/core/cpu.h" #include "hw/arm/machines-qom.h" +#include "hw/riscv/machines-qom.h" =20 static void machine_none_init(MachineState *mch) { @@ -59,4 +60,6 @@ static void machine_none_machine_init(MachineClass *mc) DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init, { TYPE_TARGET_AARCH64_MACHINE }, { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, { }) --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326911393158500 Defines TargetInfo for 32- and 64-bit riscv binaries. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++++++++++ configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++++++++++ configs/targets/meson.build | 1 + 3 files changed, 53 insertions(+) diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-so= ftmmu.c new file mode 100644 index 0000000000..897c93594b --- /dev/null +++ b/configs/targets/riscv32-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv32) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" + +static const TargetInfo target_info_riscv32_system =3D { + .target_name =3D "riscv32", + .target_arch =3D SYS_EMU_TARGET_RISCV32, + .long_bits =3D 32, + .cpu_type =3D TYPE_RISCV_CPU, + .machine_typename =3D TYPE_TARGET_RISCV32_MACHINE, + .endianness =3D ENDIAN_MODE_LITTLE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_riscv32_system; +} diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-so= ftmmu.c new file mode 100644 index 0000000000..d2e4520d76 --- /dev/null +++ b/configs/targets/riscv64-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv64) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" + +static const TargetInfo target_info_riscv64_system =3D { + .target_name =3D "riscv64", + .target_arch =3D SYS_EMU_TARGET_RISCV64, + .long_bits =3D 64, + .cpu_type =3D TYPE_RISCV_CPU, + .machine_typename =3D TYPE_TARGET_RISCV64_MACHINE, + .endianness =3D ENDIAN_MODE_LITTLE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_riscv64_system; +} diff --git a/configs/targets/meson.build b/configs/targets/meson.build index cca2514eb5..2ab4d27eaf 100644 --- a/configs/targets/meson.build +++ b/configs/targets/meson.build @@ -1,5 +1,6 @@ foreach target : [ 'arm-softmmu', 'aarch64-softmmu', + 'riscv32-softmmu', 'riscv64-softmmu' ] config_target_info +=3D {target : files(target + '.c')} endforeach --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326927519158500 Adds a helper function to tell if the binary is targeting riscv64 or not. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 6235962223..a4853ad4bb 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -71,4 +71,11 @@ bool target_arm(void); */ bool target_aarch64(void); =20 +/** + * target_riscv64: + * + * Returns whether the target architecture is riscv64 + */ +bool target_riscv64(void); + #endif diff --git a/target-info.c b/target-info.c index 24696ff411..6cc78e25c8 100644 --- a/target-info.c +++ b/target-info.c @@ -73,3 +73,8 @@ bool target_aarch64(void) { return target_arch() =3D=3D SYS_EMU_TARGET_AARCH64; } + +bool target_riscv64(void) +{ + return target_arch() =3D=3D SYS_EMU_TARGET_RISCV64; +} --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326969614158500 TYPE_RISCV_CPU_BASE is used only to initialize the correct default machine for 3 machines. Replace it with a runtime check. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- include/hw/riscv/virt.h | 11 +++++++++++ target/riscv/cpu.h | 6 ------ hw/riscv/microblaze-v-generic.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 2 +- 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7b4c2c8b7d..3a17641078 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,6 +19,7 @@ #ifndef HW_RISCV_VIRT_H #define HW_RISCV_VIRT_H =20 +#include "qemu/target-info.h" #include "hw/boards.h" #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" @@ -137,6 +138,16 @@ bool virt_is_iommu_sys_enabled(RISCVVirtState *s); void virt_acpi_setup(RISCVVirtState *vms); uint32_t imsic_num_bits(uint32_t count); =20 +static inline const char *virt_default_cpu_type(void) +{ + if (target_riscv64()) { + return TYPE_RISCV_CPU_BASE64; + } else { + return TYPE_RISCV_CPU_BASE32; + } +} + + /* * The virt machine physical address space used by some of the devices * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616406f07f..da2bc554d3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -39,12 +39,6 @@ typedef struct CPUArchState CPURISCVState; =20 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU =20 -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - /* * b0: Whether a instruction always raise a store AMO or not. */ diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index 0df276f9fb..0222ff0c06 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -26,6 +26,7 @@ #include "hw/char/xilinx_uartlite.h" #include "hw/misc/unimp.h" #include "hw/riscv/machines-qom.h" +#include "hw/riscv/virt.h" =20 #define LMB_BRAM_SIZE (128 * KiB) #define MEMORY_BASEADDR 0x80000000 @@ -183,7 +184,7 @@ static void mb_v_generic_machine_init(MachineClass *mc) mc->init =3D mb_v_generic_init; mc->min_cpus =3D 1; mc->max_cpus =3D 1; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D virt_default_cpu_type(); mc->default_cpus =3D 1; } =20 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 69eb3dfc24..7d1a642a78 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -34,6 +34,7 @@ #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/riscv/machines-qom.h" +#include "hw/riscv/virt.h" #include "hw/char/riscv_htif.h" #include "hw/intc/riscv_aclint.h" #include "chardev/char.h" @@ -351,7 +352,7 @@ static void spike_machine_class_init(ObjectClass *oc, c= onst void *data) mc->init =3D spike_board_init; mc->max_cpus =3D SPIKE_CPUS_MAX; mc->is_default =3D true; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D virt_default_cpu_type(); mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f42fffb223..6f6164e05d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1922,7 +1922,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->desc =3D "RISC-V VirtIO board"; mc->init =3D virt_machine_init; mc->max_cpus =3D VIRT_CPUS_MAX; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D virt_default_cpu_type(); mc->block_default_type =3D IF_VIRTIO; mc->no_cdrom =3D 1; mc->pci_allow_0_address =3D true; --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326903485158500 KVM fields of CPURISCVState are now always exposed as CONFIG_KVM cannot be used in common code. riscv_cpu_mxl() is changed to return CPURISCVState::misa_mxl unconditionally, as use of target_riscv64() would result in an extra load and compare with TargetInfo::target_arch. We might as well just perform a single load. Likewise, for cpu_recompute_xl(), cpu_address_xl(), and riscv_cpu_sxl(), we opt for returning the corresponding CPURISCVState field with ifdefs for system mode adding extra conditions. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 36 ++++++++---------------------------- 1 file changed, 8 insertions(+), 28 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index da2bc554d3..946665d9ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -497,14 +497,12 @@ struct CPUArchState { hwaddr kernel_addr; hwaddr fdt_addr; =20 -#ifdef CONFIG_KVM /* kvm timer */ bool kvm_timer_dirty; uint64_t kvm_timer_time; uint64_t kvm_timer_compare; uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; -#endif /* CONFIG_KVM */ =20 /* RNMI */ uint64_t mnscratch; @@ -703,14 +701,10 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) FIELD(TB_FLAGS, PM_PMM, 29, 2) FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) =20 -#ifdef TARGET_RISCV32 -#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) { return env->misa_mxl; } -#endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) @@ -754,9 +748,6 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, p= rivilege_mode_t mode) } #endif =20 -#if defined(TARGET_RISCV32) -#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) { #if !defined(CONFIG_USER_ONLY) @@ -765,43 +756,32 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState= *env) return env->misa_mxl; #endif } -#endif =20 -#if defined(TARGET_RISCV32) -#define cpu_address_xl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL cpu_address_xl(CPURISCVState *env) { -#ifdef CONFIG_USER_ONLY - return env->xl; -#else - int mode =3D cpu_address_mode(env); - - return cpu_get_xl(env, mode); +#ifndef CONFIG_USER_ONLY + if (target_riscv64()) { + int mode =3D cpu_address_mode(env); + return cpu_get_xl(env, mode); + } #endif + return env->xl; } -#endif =20 static inline int riscv_cpu_xlen(CPURISCVState *env) { return 16 << env->xl; } =20 -#ifdef TARGET_RISCV32 -#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) { -#ifdef CONFIG_USER_ONLY - return env->misa_mxl; -#else +#ifndef CONFIG_USER_ONLY if (env->misa_mxl !=3D MXL_RV32) { return get_field(env->mstatus, MSTATUS64_SXL); } #endif - return MXL_RV32; + return env->misa_mxl; } -#endif =20 static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg, uint32_t priv_ver, --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326929483158500 IRQ_LOCAL_GUEST_MAX depends on TARGET_LONG_BITS and is used in hw/intc/riscv_imsic.c. The macro is replaced by a field in RISCVCPUDef initialized in riscv_cpu_class_base_init(). Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 2 -- hw/intc/riscv_imsic.c | 4 +++- target/riscv/cpu.c | 14 ++++++++++++-- 4 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 946665d9ed..3573581f0c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -563,6 +563,7 @@ typedef struct RISCVCPUDef { int32_t vext_spec; RISCVCPUConfig cfg; bool bare; + uint8_t irq_local_guest_max; const RISCVCSR *custom_csrs; } RISCVCPUDef; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b62dd82fe7..13e052bce2 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -809,8 +809,6 @@ typedef enum RISCVException { #define IRQ_S_GEXT 12 #define IRQ_PMU_OVF 13 #define IRQ_LOCAL_MAX 64 -/* -1 is due to bit zero of hgeip and hgeie being ROZ. */ -#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 /* RNMI causes */ #define RNMI_MAX 16 diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 9274a1e842..3d32198468 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -453,13 +453,15 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t= hartid, bool mmode, { DeviceState *dev =3D qdev_new(TYPE_RISCV_IMSIC); CPUState *cpu =3D cpu_by_arch_id(hartid); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(RISCV_CPU(cpu)); uint32_t i; =20 assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1))); if (mmode) { assert(num_pages =3D=3D 1); } else { - assert(num_pages >=3D 1 && num_pages <=3D (IRQ_LOCAL_GUEST_MAX + 1= )); + assert(num_pages >=3D 1 && + num_pages <=3D (mcc->def->irq_local_guest_max + 1)); } assert(IMSIC_MIN_ID <=3D num_ids); assert(num_ids <=3D IMSIC_MAX_ID); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7a8b8d736e..dd58e63ecd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1019,6 +1019,7 @@ void riscv_add_satp_mode_properties(Object *obj) =20 static void riscv_cpu_set_irq(void *opaque, int irq, int level) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(opaque); RISCVCPU *cpu =3D RISCV_CPU(opaque); CPURISCVState *env =3D &cpu->env; =20 @@ -1053,7 +1054,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) default: g_assert_not_reached(); } - } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { + } else if (irq < (IRQ_LOCAL_MAX + mcc->def->irq_local_guest_max)) { /* Require H-extension for handling guest local interrupts */ if (!riscv_has_ext(env, RVH)) { g_assert_not_reached(); @@ -1100,7 +1101,7 @@ static void riscv_cpu_init(Object *obj) =20 #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, - IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); + IRQ_LOCAL_MAX + mcc->def->irq_local_guest_max); qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, "riscv.cpu.rnmi", RNMI_MAX); #endif /* CONFIG_USER_ONLY */ @@ -2791,6 +2792,15 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) mcc->def =3D g_new0(RISCVCPUDef, 1); } =20 + /* + * RISCVCPUDef::irq_local_guest_max is initialized to=20 + * `target_long_bits()-1` due to bit zero of hgeip and hgeie + * being ROZ. + * + * This value does not vary between CPU types. + */ + mcc->def->irq_local_guest_max =3D target_long_bits() - 1; + if (data) { const RISCVCPUDef *def =3D data; mcc->def->bare |=3D def->bare; --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766326969313945.7295006576963; Sun, 21 Dec 2025 06:22:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vXKJt-0004Xh-OR; Sun, 21 Dec 2025 09:22:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vXKJ6-0003LU-4S for qemu-devel@nongnu.org; Sun, 21 Dec 2025 09:21:17 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vXKJ4-0000hd-K1 for qemu-devel@nongnu.org; Sun, 21 Dec 2025 09:21:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=9V+zSRmfapyIIdsQiy/9w4+DSrY3i+wfbXF4IxIKDGQ=; b=vBbOqFwXv/2AxyP 3NjfN7TZXiJI6HVZZoO92elsynfl4QWoEIsIkUlJEWrabvB/DqDBwTHptvpr+taHyBEzBd6pt2A57 /F9bM2Dk9NOoEaXkcy3ltWKIYK7Tffb3Ja2Jt8DmEu01Oy99BrAvRZ1dQcwgXTgRMGKDXRNORzkqH ao=; Date: Sun, 21 Dec 2025 15:23:14 +0100 Subject: [PATCH v2 10/14] target/riscv: Move riscv_pmu_read_ctr() to internal csr.h header MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-hw-riscv-cpu-int-v2-10-eb49d72c5b2f@rev.ng> References: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> In-Reply-To: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326969578158500 The function depends on target_ulong and is via the pmu.h header exposed to hw/riscv, this function is only used internally in pmu.c and csr.c, so move it to the internal csr.h header. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- target/riscv/csr.h | 3 +++ target/riscv/pmu.h | 2 -- target/riscv/pmu.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.h b/target/riscv/csr.h index 3752a0ef43..e6a6f2e85f 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -90,4 +90,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_= index, target_ulong val); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); =20 +/* PMU CSRs */ +RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, + bool upper_half, uint32_t ctr_idx); #endif /* RISCV_CSR_H */ diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3853d0e262..ca40cfeed6 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -36,7 +36,5 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t va= lue, uint32_t ctr_idx); void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, bool new_virt); -RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, - bool upper_half, uint32_t ctr_idx); =20 #endif /* RISCV_PMU_H */ diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 708f2ec7aa..9701c8cba6 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -22,6 +22,7 @@ #include "qemu/timer.h" #include "cpu.h" #include "pmu.h" +#include "target/riscv/csr.h" #include "exec/icount.h" #include "system/device_tree.h" =20 --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766326921; cv=none; d=zohomail.com; s=zohoarc; b=ltuidOCcIIF0pQSe7N/Lb52/q6yR7PkXzo9opCu95hfW97GUqwK5ugZQhcbcdp0gXupmmXDQd3p/XhJTdnqKsiNwWcCm8qkgoLemkKXPio+rPoaJ/d+nHJLnTYhKPAFQ0nT/+no8XMH8vGyuSGTKa0786b+fnJ2H4lfCWUGai9Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Date: Sun, 21 Dec 2025 15:23:15 +0100 Subject: [PATCH v2 11/14] target/riscv: Make pmu.h target-agnostic MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-hw-riscv-cpu-int-v2-11-eb49d72c5b2f@rev.ng> References: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> In-Reply-To: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326923446158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- target/riscv/pmu.h | 2 +- target/riscv/pmu.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index ca40cfeed6..273d8f3f94 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -34,7 +34,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_even= t_idx event_idx); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); -void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, +void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newp= riv, bool new_virt); =20 #endif /* RISCV_PMU_H */ diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 9701c8cba6..d818c2f8f6 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -115,7 +115,8 @@ static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, ui= nt32_t ctr_idx) * new priv and new virt values are passed in as arguments. */ static void riscv_pmu_icount_update_priv(CPURISCVState *env, - target_ulong newpriv, bool new_vi= rt) + privilege_mode_t newpriv, + bool new_virt) { uint64_t *snapshot_prev, *snapshot_new; uint64_t current_icount; @@ -155,7 +156,8 @@ static void riscv_pmu_icount_update_priv(CPURISCVState = *env, } =20 static void riscv_pmu_cycle_update_priv(CPURISCVState *env, - target_ulong newpriv, bool new_vir= t) + privilege_mode_t newpriv, + bool new_virt) { uint64_t *snapshot_prev, *snapshot_new; uint64_t current_ticks; @@ -190,7 +192,7 @@ static void riscv_pmu_cycle_update_priv(CPURISCVState *= env, counter_arr[env->priv] +=3D delta; } =20 -void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, +void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newp= riv, bool new_virt) { riscv_pmu_cycle_update_priv(env, newpriv, new_virt); --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1766326948; cv=none; d=zohomail.com; s=zohoarc; b=F48pJ2DaOkuLDolCgPVjvDK+vM6cRJ8pJY7t3aEfP+wZPiVrgm/BihcgsOHozNFPwqXQAnM2xkoE/tSsQDmOWlk6z8r6wA1K78hQP4pf5GUfFDlZ96UpwYaSBcntH7Swf9ErGpwPYGJnIELaUdSjneYvgkQ4OCD9UGaovXTF9CU= ARC-Message-Signature: i=1; a=rsa-sha256; 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Date: Sun, 21 Dec 2025 15:23:16 +0100 Subject: [PATCH v2 12/14] target/riscv: Stub out kvm functions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-hw-riscv-cpu-int-v2-12-eb49d72c5b2f@rev.ng> References: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> In-Reply-To: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326949530158500 Functions used externally by hw/riscv are stubbed out for non-kvm configurations, allowing a single compilation of hw/riscv. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- target/riscv/kvm/kvm-stub.c | 23 +++++++++++++++++++++++ target/riscv/kvm/meson.build | 1 + 2 files changed, 24 insertions(+) diff --git a/target/riscv/kvm/kvm-stub.c b/target/riscv/kvm/kvm-stub.c new file mode 100644 index 0000000000..64e39c96d8 --- /dev/null +++ b/target/riscv/kvm/kvm-stub.c @@ -0,0 +1,23 @@ +/* + * QEMU RISCV specific KVM stubs + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "target/riscv/kvm/kvm_riscv.h" + +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num) +{ + g_assert_not_reached(); +} + +uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) +{ + g_assert_not_reached(); +} diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build index 7e92415091..d3f395f431 100644 --- a/target/riscv/kvm/meson.build +++ b/target/riscv/kvm/meson.build @@ -1 +1,2 @@ +riscv_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c')) --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=3NZIUDzncXS/ABiVLpfXYHfk+qKOZAkW4KHzDEB9STE=; b=aM04ImAjtBwdH1l XT6fyDOO2coZe+bK09vMISEaT1m4+iW/WU3YiFIFkJlAdIOaxkzoBOsxoyTiJoAiQR+dmk22QKOqG SDmRphFBPK7tAKDi4qWfrnDB1y3qi3pgvt4OGFh7P0DpSy8HePGMV2lXYc/4jKL3erZlJHGlQABqm f0=; Date: Sun, 21 Dec 2025 15:23:17 +0100 Subject: [PATCH v2 13/14] hw/riscv: Define SiFive E/U CPUs using runtime conditions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251221-hw-riscv-cpu-int-v2-13-eb49d72c5b2f@rev.ng> References: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> In-Reply-To: <20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326939537158500 Macros are removed and replaced with inlined ternary statements. The now empty sifive_cpu.h header is then removed. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- include/hw/riscv/sifive_cpu.h | 31 ------------------------------- include/hw/riscv/sifive_e.h | 1 - include/hw/riscv/sifive_u.h | 1 - hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 7 +++++-- 5 files changed, 7 insertions(+), 36 deletions(-) diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h deleted file mode 100644 index 136799633a..0000000000 --- a/include/hw/riscv/sifive_cpu.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * SiFive CPU types - * - * Copyright (c) 2017 SiFive, Inc. - * Copyright (c) 2019 Bin Meng - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ - -#ifndef HW_SIFIVE_CPU_H -#define HW_SIFIVE_CPU_H - -#if defined(TARGET_RISCV32) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif - -#endif /* HW_SIFIVE_CPU_H */ diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 31180a680e..ff42ca9c9c 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -20,7 +20,6 @@ #define HW_SIFIVE_E_H =20 #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_cpu.h" #include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_e_aon.h" #include "hw/boards.h" diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 0696f85942..5a735bd128 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -24,7 +24,6 @@ #include "hw/dma/sifive_pdma.h" #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_cpu.h" #include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 7ed419cf69..20433ac6ce 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -151,7 +151,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc= , const void *data) mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; mc->init =3D sifive_e_machine_init; mc->max_cpus =3D 1; - mc->default_cpu_type =3D SIFIVE_E_CPU; + mc->default_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_E51 + : TYPE_RISCV_CPU_SIFIVE_E31; mc->default_ram_id =3D "riscv.sifive.e.ram"; mc->default_ram_size =3D sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2ff2059bb9..b3b739bc37 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -723,7 +723,8 @@ static void sifive_u_machine_class_init(ObjectClass *oc= , const void *data) mc->init =3D sifive_u_machine_init; mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpu_type =3D SIFIVE_U_CPU; + mc->default_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_U54 + : TYPE_RISCV_CPU_SIFIVE_U34; mc->default_cpus =3D mc->min_cpus; mc->default_ram_id =3D "riscv.sifive.u.ram"; mc->auto_create_sdcard =3D true; @@ -756,6 +757,8 @@ type_init(sifive_u_machine_init_register_types) static void sifive_u_soc_instance_init(Object *obj) { SiFiveUSoCState *s =3D RISCV_U_SOC(obj); + const char *e_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_= E51 + : TYPE_RISCV_CPU_SIFIVE_E3= 1; =20 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUS= TER); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); @@ -764,7 +767,7 @@ static void sifive_u_soc_instance_init(Object *obj) TYPE_RISCV_HART_ARRAY); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); - qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); + qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", e_cpu_type); qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); =20 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUS= TER); --=20 2.51.0 From nobody Mon Feb 9 19:10:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1766326937500158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson --- hw/riscv/meson.build | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 2a8d5b136c..7bb13f7270 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -1,18 +1,18 @@ -riscv_ss =3D ss.source_set() -riscv_ss.add(files('boot.c')) -riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) -riscv_ss.add(files('riscv_hart.c')) -riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) -riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) -riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) -riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( +riscv_common_ss =3D ss.source_set() +riscv_common_ss.add(files('boot.c')) +riscv_common_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) +riscv_common_ss.add(files('riscv_hart.c')) +riscv_common_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'= )) +riscv_common_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_common_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) +riscv_common_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) +riscv_common_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) +riscv_common_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) +riscv_common_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microc= hip_pfsoc.c')) +riscv_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c= ')) +riscv_common_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( 'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-h= pm.c')) -riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-gen= eric.c')) -riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan= _kmh.c')) +riscv_common_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaz= e-v-generic.c')) +riscv_common_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xi= angshan_kmh.c')) =20 -hw_arch +=3D {'riscv': riscv_ss} +hw_common_arch +=3D {'riscv': riscv_common_ss} --=20 2.51.0