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Signed-off-by: Mirsad Ostrakovic Signed-off-by: Ruslan Ruslichenko --- include/hw/qdev-core.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 2caa0cbd26..e3862279da 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -366,6 +366,26 @@ typedef struct BusChild { typedef QTAILQ_HEAD(, BusChild) BusChildHead; typedef QLIST_ENTRY(BusState) BusStateEntry; =20 +/** + * struct BusIOMMUOps: callbacks structure for specific IOMMU handlers + * of a bus + */ +typedef struct BusIOMMUOps { + /** + * @get_address_space: get the address space for a set of devices + * on a bus. + * + * Mandatory callback which returns a pointer to an #AddressSpace + * + * @bus: the #Bus being accessed. + * + * @opaque: the data passed to bus_setup_iommu(). + * + * @devif: device identification number + */ + AddressSpace * (*get_address_space)(BusState *bus, void *opaque, int d= evid); +} BusIOMMUOps; + /** * struct BusState: * @obj: parent object @@ -376,6 +396,8 @@ typedef QLIST_ENTRY(BusState) BusStateEntry; * @realized: is the bus itself realized? * @full: is the bus full? * @num_children: current number of child buses + * @iommu_ops: TODO + * @iommu_opaque: TODO */ struct BusState { /* private: */ @@ -388,6 +410,8 @@ struct BusState { bool realized; bool full; int num_children; + const BusIOMMUOps *iommu_ops; + void *iommu_opaque; =20 /** * @children: an RCU protected QTAILQ, thus readers must use RCU --=20 2.43.0 From nobody Mon Feb 9 15:00:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1766183142; cv=none; d=zohomail.com; s=zohoarc; b=SSa2jV5pnWGsaJJPL0EinKoLzBeyKNnKEZ0KKbasiaXPn0/3Jg7k6U59bYPDcRXY0CSdC/ekQm+o/atHC53EIDS7aURj0wQAPh6PjBZ2Qnlx8zwnEmT0Wb0e191+MyMKsagNM7UMXU36mliZBWF5gfNABjdkXvnCGV/7nc6mWd8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766183142; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PsjIGYpY3rtNIwVVB461L5eAVGLk+UOcl2XZVc+t3W0=; b=awVOeYUW+1SlMudCttzTWme79ECdau8Erk5eifMHtbRb05c4x8R1et+Eqers7U120KoU8Ev+nb67a3pp5jZiQDhd9HomwCxdCjgKhte8N6+hEvyWnfr0thtZdOZCL6e0qXZCpmtVqKN3jjoH65CEE7vnI4v8yoUv+wqmXhSLMPs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766183142745165.66599808896774; Fri, 19 Dec 2025 14:25:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vWiua-0001jz-6j; Fri, 19 Dec 2025 17:25:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vWiuO-0001gR-SI for qemu-devel@nongnu.org; Fri, 19 Dec 2025 17:25:14 -0500 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vWiuM-0004yX-6v for qemu-devel@nongnu.org; Fri, 19 Dec 2025 17:25:11 -0500 Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-649e28dccadso3352052a12.3 for ; Fri, 19 Dec 2025 14:25:09 -0800 (PST) Received: from thinkpad-t470s.. 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This patch adds support to assotiate SMMU with simple bus in case SMMU created with type: 'generic-primary-bus'. The 'primary-bus' is now renamed to 'pci-primary-bus' to avoid confusion. Signed-off-by: Mirsad Ostrakovic Signed-off-by: Ruslan Ruslichenko --- hw/arm/smmu-common.c | 69 ++++++++++++++++++++++++++++++------ hw/arm/virt.c | 2 +- hw/core/bus.c | 13 +++++++ include/hw/arm/smmu-common.h | 22 +++++++++--- include/hw/qdev-core.h | 12 +++++++ 5 files changed, 103 insertions(+), 15 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 62a7612184..52ef49d7f6 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -25,6 +25,7 @@ #include "qapi/error.h" #include "qemu/jhash.h" #include "qemu/module.h" +#include "hw/qdev-core.h" =20 #include "qemu/error-report.h" #include "hw/arm/smmu-common.h" @@ -824,7 +825,7 @@ SMMUTLBEntry *smmu_translate(SMMUState *bs, SMMUTransCf= g *cfg, dma_addr_t addr, /** * The bus number is used for lookup when SID based invalidation occurs. * In that case we lazily populate the SMMUPciBus array from the bus hash - * table. At the time the SMMUPciBus is created (smmu_find_add_as), the bus + * table. At the time the SMMUPciBus is created (pci_smmu_find_add_as), th= e bus * numbers may not be always initialized yet. */ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num) @@ -847,7 +848,7 @@ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t= bus_num) return NULL; } =20 -static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +static AddressSpace *pci_smmu_find_add_as(PCIBus *bus, void *opaque, int d= evfn) { SMMUState *s =3D opaque; SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); @@ -870,6 +871,7 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void= *opaque, int devfn) sdev->smmu =3D s; sdev->bus =3D bus; sdev->devfn =3D devfn; + sdev->pcie_device =3D true; =20 memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), s->mrtypename, @@ -883,8 +885,48 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, voi= d *opaque, int devfn) return &sdev->as; } =20 -static const PCIIOMMUOps smmu_ops =3D { - .get_address_space =3D smmu_find_add_as, +static AddressSpace *bus_smmu_find_add_as(BusState *bus, void *opaque, int= devid) +{ + SMMUState *s =3D opaque; + SMMUBus *sbus =3D g_hash_table_lookup(s->smmu_bus_by_busptr, bus); + SMMUDevice *sdev; + static unsigned int index; + + if (!sbus) { + sbus =3D g_malloc0(sizeof(SMMUBus) + + sizeof(SMMUDevice *) * SMMU_DEVID_MAX); + sbus->bus =3D bus; + g_hash_table_insert(s->smmu_bus_by_busptr, bus, sbus); + } + + sdev =3D sbus->pbdev[devid]; + if (!sdev) { + char *name =3D g_strdup_printf("%s-%d-%d", s->mrtypename, devid, i= ndex++); + + sdev =3D sbus->pbdev[devid] =3D g_new0(SMMUDevice, 1); + + sdev->smmu =3D s; + sdev->bus =3D bus; + sdev->devfn =3D devid; + + memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), + s->mrtypename, + OBJECT(s), name, UINT64_MAX); + address_space_init(&sdev->as, + MEMORY_REGION(&sdev->iommu), name); + trace_smmu_add_mr(name); + g_free(name); + } + + return &sdev->as; +} + +static const PCIIOMMUOps pci_smmu_ops =3D { + .get_address_space =3D pci_smmu_find_add_as, +}; + +static const BusIOMMUOps bus_smmu_ops =3D { + .get_address_space =3D bus_smmu_find_add_as, }; =20 SMMUDevice *smmu_find_sdev(SMMUState *s, uint32_t sid) @@ -926,7 +968,7 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) { SMMUState *s =3D ARM_SMMU(dev); SMMUBaseClass *sbc =3D ARM_SMMU_GET_CLASS(dev); - PCIBus *pci_bus =3D s->primary_bus; + PCIBus *pci_bus =3D s->pci_primary_bus; Error *local_err =3D NULL; =20 sbc->parent_realize(dev, &local_err); @@ -939,6 +981,11 @@ static void smmu_base_realize(DeviceState *dev, Error = **errp) g_free, g_free); s->smmu_pcibus_by_busptr =3D g_hash_table_new(NULL, NULL); =20 + if (s->generic_primary_bus ) { + bus_setup_iommu(s->generic_primary_bus, &bus_smmu_ops, s); + return; + } + if (!pci_bus) { error_setg(errp, "SMMU is not attached to any PCI bus!"); return; @@ -962,10 +1009,10 @@ static void smmu_base_realize(DeviceState *dev, Erro= r **errp) } } =20 - if (s->smmu_per_bus) { - pci_setup_iommu_per_bus(pci_bus, &smmu_ops, s); + if (s->pci_smmu_per_bus) { + pci_setup_iommu_per_bus(pci_bus, &pci_smmu_ops, s); } else { - pci_setup_iommu(pci_bus, &smmu_ops, s); + pci_setup_iommu(pci_bus, &pci_smmu_ops, s); } return; } @@ -991,9 +1038,11 @@ static void smmu_base_reset_exit(Object *obj, ResetTy= pe type) =20 static const Property smmu_dev_properties[] =3D { DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0), - DEFINE_PROP_BOOL("smmu_per_bus", SMMUState, smmu_per_bus, false), - DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, + DEFINE_PROP_BOOL("pci_smmu_per_bus", SMMUState, pci_smmu_per_bus, fals= e), + DEFINE_PROP_LINK("pci-primary-bus", SMMUState, pci_primary_bus, TYPE_PCI_BUS, PCIBus *), + DEFINE_PROP_LINK("generic-primary-bus", SMMUState, generic_primary_bus, + TYPE_BUS, BusState *), }; =20 static void smmu_base_class_init(ObjectClass *klass, const void *data) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 25fb2bab56..d9d7b982b3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3050,7 +3050,7 @@ static void virt_machine_device_pre_plug_cb(HotplugHa= ndler *hotplug_dev, "iommu=3Dsmmuv3" : "virtio-iommu"); } else if (vms->iommu =3D=3D VIRT_IOMMU_NONE) { /* The new SMMUv3 device is specific to the PCI bus */ - object_property_set_bool(OBJECT(dev), "smmu_per_bus", true, NU= LL); + object_property_set_bool(OBJECT(dev), "pci_smmu_per_bus", true= , NULL); } } } diff --git a/hw/core/bus.c b/hw/core/bus.c index bddfc22d38..6d1483fdbd 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -80,6 +80,19 @@ bool bus_is_in_reset(BusState *bus) return resettable_is_in_reset(OBJECT(bus)); } =20 +void bus_setup_iommu(BusState *bus, const BusIOMMUOps *ops, void *opaque) +{ + /* + * If called, bus_setup_iommu() should provide a minimum set of + * useful callbacks for the bus. + */ + assert(ops); + assert(ops->get_address_space); + + bus->iommu_ops =3D ops; + bus->iommu_opaque =3D opaque; +} + static ResettableState *bus_get_reset_state(Object *obj) { BusState *bus =3D BUS(obj); diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 80d0fecfde..670ae46930 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -27,6 +27,8 @@ #define SMMU_PCI_DEVFN_MAX 256 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) =20 +#define SMMU_DEVID_MAX 256 + /* VMSAv8-64 Translation constants and functions */ #define VMSA_LEVELS 4 #define VMSA_MAX_S2_CONCAT 16 @@ -120,12 +122,13 @@ typedef struct SMMUTransCfg { =20 typedef struct SMMUDevice { void *smmu; - PCIBus *bus; + void *bus; int devfn; IOMMUMemoryRegion iommu; AddressSpace as; uint32_t cfg_cache_hits; uint32_t cfg_cache_misses; + bool pcie_device; QLIST_ENTRY(SMMUDevice) next; } SMMUDevice; =20 @@ -134,6 +137,11 @@ typedef struct SMMUPciBus { SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc= */ } SMMUPciBus; =20 +typedef struct SMMUBus { + BusState *bus; + SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc= */ +} SMMUBus; + typedef struct SMMUIOTLBKey { uint64_t iova; int asid; @@ -154,14 +162,16 @@ struct SMMUState { MemoryRegion iomem; =20 GHashTable *smmu_pcibus_by_busptr; + GHashTable *smmu_bus_by_busptr; GHashTable *configs; /* cache for configuration data */ GHashTable *iotlb; SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX]; PCIBus *pci_bus; QLIST_HEAD(, SMMUDevice) devices_with_notifiers; uint8_t bus_num; - PCIBus *primary_bus; - bool smmu_per_bus; /* SMMU is specific to the primary_bus */ + PCIBus *pci_primary_bus; + bool pci_smmu_per_bus; /* SMMU is specific to the pci_primary_bus */ + BusState *generic_primary_bus; }; =20 struct SMMUBaseClass { @@ -183,7 +193,11 @@ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_= t bus_num); /* Return the stream ID of an SMMU device */ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) { - return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); + if (sdev->pcie_device) { + return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); + } else { + return sdev->devfn; + } } =20 /** diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index e3862279da..2092450b90 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -954,6 +954,18 @@ bool device_is_in_reset(DeviceState *dev); */ bool bus_is_in_reset(BusState *bus); =20 +/** + * bus_setup_iommu() - Set up IOMMU operations for a bus + * @bus: the bus to configure + * @ops: IOMMU operations structure containing callback functions + * @opaque: opaque data passed to IOMMU operation callbacks + * + * Configure IOMMU operations for the specified bus. The ops structure + * must contain at least the get_address_space callback. The opaque + * parameter is passed through to the operation callbacks. + */ +void bus_setup_iommu(BusState *bus, const BusIOMMUOps *ops, void *opaque); + /* This should go away once we get rid of the NULL bus hack */ BusState *sysbus_get_default(void); =20 --=20 2.43.0 From nobody Mon Feb 9 15:00:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1766183141; cv=none; d=zohomail.com; s=zohoarc; b=Q03mnitZj176dt4Tya6EF2d+sURvyQSKD+8jKXSPkaTR9tFmxvLrWumHLV0bmjlRtC+isRVpwgxfSg5DmCDID02JMRmbVyVVgH1QSSyun4Fiba+9C+LqKxRgRl7yoETQRRRIXTWmnzPjjmPNcA+l3qQmID+k2o9i1OY2epITqHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766183141; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CdRLm5zMkoDQZ5YxMVTuMYcF0Rw/N9qJIqQIdpP+JoM=; b=ZXM3Xlpmmfg5N3SsSLPD/ltJ6vZPdLod+0KydeytKTHGbIG2QL9+IROXKaoJ4UWIzfezWPRaRWtcW+VzcOsfxsb9X97Xv0bcDRQk3x/JhhBVxvk3GErzKxA7DS/qi5D6lUxuCIPRk5rR6HHsM8XZCtCeIEZzLYBl74rb/TFISqk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766183141798702.0553922385567; Fri, 19 Dec 2025 14:25:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vWiub-0001kg-2L; Fri, 19 Dec 2025 17:25:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vWiuR-0001h1-JG for qemu-devel@nongnu.org; Fri, 19 Dec 2025 17:25:16 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vWiuP-0004zt-HZ for qemu-devel@nongnu.org; Fri, 19 Dec 2025 17:25:15 -0500 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-64b7a38f07eso2786835a12.0 for ; Fri, 19 Dec 2025 14:25:13 -0800 (PST) Received: from thinkpad-t470s.. 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Add memory region for SMMU to memory map. Signed-off-by: Mirsad Ostrakovic Signed-off-by: Ruslan Ruslichenko --- hw/arm/virt-acpi-build.c | 4 +- hw/arm/virt.c | 84 +++++++++++++++++++++++++++++++++------- include/hw/arm/virt.h | 4 +- 3 files changed, 75 insertions(+), 17 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 200e2a1da7..2d7e2e2725 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -334,8 +334,8 @@ static int populate_smmuv3_legacy_dev(GArray *sdev_blob) */ g_array_sort(sdev.rc_smmu_idmaps, iort_idmap_compare); =20 - sdev.base =3D vms->memmap[VIRT_SMMU].base; - sdev.irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + sdev.base =3D vms->memmap[VIRT_SMMU_PCIE].base; + sdev.irq =3D vms->irqmap[VIRT_SMMU_PCIE] + ARM_SPI_BASE; g_array_append_val(sdev_blob, sdev); return sdev.rc_smmu_idmaps->len; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d9d7b982b3..ad609bc651 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -187,13 +187,14 @@ static const MemMapEntry base_memmap[] =3D { [VIRT_FW_CFG] =3D { 0x09020000, 0x00000018 }, [VIRT_GPIO] =3D { 0x09030000, 0x00001000 }, [VIRT_UART1] =3D { 0x09040000, 0x00001000 }, - [VIRT_SMMU] =3D { 0x09050000, SMMU_IO_LEN }, - [VIRT_PCDIMM_ACPI] =3D { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, - [VIRT_ACPI_GED] =3D { 0x09080000, ACPI_GED_EVT_SEL_LEN }, - [VIRT_NVDIMM_ACPI] =3D { 0x09090000, NVDIMM_ACPI_IO_LEN}, - [VIRT_PVTIME] =3D { 0x090a0000, 0x00010000 }, - [VIRT_SECURE_GPIO] =3D { 0x090b0000, 0x00001000 }, - [VIRT_ACPI_PCIHP] =3D { 0x090c0000, ACPI_PCIHP_SIZE }, + [VIRT_SMMU_PCIE] =3D { 0x09050000, SMMU_IO_LEN }, + [VIRT_SMMU_SYSBUS] =3D { 0x09070000, SMMU_IO_LEN }, + [VIRT_PCDIMM_ACPI] =3D { 0x09090000, MEMORY_HOTPLUG_IO_LEN }, + [VIRT_ACPI_GED] =3D { 0x090a0000, ACPI_GED_EVT_SEL_LEN }, + [VIRT_NVDIMM_ACPI] =3D { 0x090b0000, NVDIMM_ACPI_IO_LEN}, + [VIRT_PVTIME] =3D { 0x090c0000, 0x00010000 }, + [VIRT_SECURE_GPIO] =3D { 0x090d0000, 0x00001000 }, + [VIRT_ACPI_PCIHP] =3D { 0x090e0000, ACPI_PCIHP_SIZE }, [VIRT_MMIO] =3D { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that siz= e */ [VIRT_PLATFORM_BUS] =3D { 0x0c000000, 0x02000000 }, @@ -247,7 +248,8 @@ static const int a15irqmap[] =3D { [VIRT_ACPI_GED] =3D 9, [VIRT_MMIO] =3D 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] =3D 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ - [VIRT_SMMU] =3D 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ + [VIRT_SMMU_PCIE] =3D 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ + [VIRT_SMMU_SYSBUS] =3D 78, /* ...to 78 + NUM_SMMU_IRQS - 1 */ [VIRT_PLATFORM_BUS] =3D 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ }; =20 @@ -1514,14 +1516,14 @@ static void create_smmuv3_dev_dtb(VirtMachineState = *vms, 0x0, vms->iommu_phandle, 0x0, 0x10000); } =20 -static void create_smmu(const VirtMachineState *vms, +static void create_smmu_pcie(const VirtMachineState *vms, PCIBus *bus) { VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); - int irq =3D vms->irqmap[VIRT_SMMU]; + int irq =3D vms->irqmap[VIRT_SMMU_PCIE]; int i; - hwaddr base =3D vms->memmap[VIRT_SMMU].base; - hwaddr size =3D vms->memmap[VIRT_SMMU].size; + hwaddr base =3D vms->memmap[VIRT_SMMU_PCIE].base; + hwaddr size =3D vms->memmap[VIRT_SMMU_PCIE].size; DeviceState *dev; =20 if (vms->iommu !=3D VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { @@ -1533,7 +1535,7 @@ static void create_smmu(const VirtMachineState *vms, if (!vmc->no_nested_smmu) { object_property_set_str(OBJECT(dev), "stage", "nested", &error_fat= al); } - object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), + object_property_set_link(OBJECT(dev), "pci-primary-bus", OBJECT(bus), &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); @@ -1544,6 +1546,58 @@ static void create_smmu(const VirtMachineState *vms, create_smmuv3_dt_bindings(vms, base, size, irq); } =20 +static void create_smmu_sysbus(VirtMachineState *vms) +{ + VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); + char *node; + const char compat[] =3D "arm,smmu-v3"; + int irq =3D vms->irqmap[VIRT_SMMU_SYSBUS]; + int i; + hwaddr base =3D vms->memmap[VIRT_SMMU_SYSBUS].base; + hwaddr size =3D vms->memmap[VIRT_SMMU_SYSBUS].size; + const char irq_names[] =3D "eventq\0priq\0cmdq-sync\0gerror"; + DeviceState *dev; + MachineState *ms =3D MACHINE(vms); + + vms->sysbus_iommu_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + + dev =3D qdev_new(TYPE_ARM_SMMUV3); + + if (!vmc->no_nested_smmu) { + object_property_set_str(OBJECT(dev), "stage", "nested", &error_fat= al); + } + object_property_set_link(OBJECT(dev), "generic-primary-bus",=20 + OBJECT(sysbus_get_default()), &error_abort); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + for (i =3D 0; i < NUM_SMMU_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in(vms->gic, irq + i)); + } + + node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, node); + qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); + + qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + + qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, + sizeof(irq_names)); + + qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); + + qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); + + qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->sysbus_iommu_phan= dle); + + g_free(node); +} + static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) { const char compat[] =3D "virtio,pci-iommu\0pci1af4,1057"; @@ -1692,7 +1746,7 @@ static void create_pcie(VirtMachineState *vms) =20 switch (vms->iommu) { case VIRT_IOMMU_SMMUV3: - create_smmu(vms, vms->bus); + create_smmu_pcie(vms, vms->bus); if (!vms->default_bus_bypass_iommu) { qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 0x0, vms->iommu_phandle, 0x0, 0x100= 00); @@ -2509,6 +2563,8 @@ static void machvirt_init(MachineState *machine) create_pcie(vms); create_cxl_host_reg_region(vms); =20 + create_smmu_sysbus(vms); + if (aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { vms->acpi_dev =3D create_acpi_ged(vms); vms->generic_error_notifier.notify =3D virt_generic_error_req; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index c77a33f6df..00b276ecf0 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -63,7 +63,8 @@ enum { VIRT_GIC_VCPU, VIRT_GIC_ITS, VIRT_GIC_REDIST, - VIRT_SMMU, + VIRT_SMMU_PCIE, + VIRT_SMMU_SYSBUS, VIRT_UART0, VIRT_MMIO, VIRT_RTC, @@ -168,6 +169,7 @@ struct VirtMachineState { uint32_t gic_phandle; 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Key changes: - Implemented virtio_mmio_get_dma_as() callback, invoked from get_dma_as() when a device is behind an SMMUv3. - Added stream ID support for virtio-mmio devices registered with the SMMU. With these changes, virtio-mmio devices can perform DMA through SMMUv3, enabling proper address translation and isolation in ARM virt platforms. Signed-off-by: Dmytro Terletskyi --- hw/virtio/virtio-mmio.c | 29 +++++++++++++++++++++++++++++ include/hw/virtio/virtio-mmio.h | 3 +++ 2 files changed, 32 insertions(+) diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index c05c00bcd4..8f19492e3f 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -31,6 +31,7 @@ #include "system/kvm.h" #include "system/replay.h" #include "hw/virtio/virtio-mmio.h" +#include "system/address-spaces.h" #include "qemu/error-report.h" #include "qemu/log.h" #include "trace.h" @@ -775,6 +776,7 @@ static void virtio_mmio_realizefn(DeviceState *d, Error= **errp) { VirtIOMMIOProxy *proxy =3D VIRTIO_MMIO(d); SysBusDevice *sbd =3D SYS_BUS_DEVICE(d); + static uint32_t stream_id =3D VIRTIO_MMIO_STREAM_ID_OFFSET; =20 qbus_init(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, d, NU= LL); sysbus_init_irq(sbd, &proxy->irq); @@ -784,6 +786,8 @@ static void virtio_mmio_realizefn(DeviceState *d, Error= **errp) proxy->flags &=3D ~VIRTIO_IOMMIO_FLAG_USE_IOEVENTFD; } =20 + proxy->stream_id =3D stream_id++; + if (proxy->legacy) { memory_region_init_io(&proxy->iomem, OBJECT(d), &virtio_legacy_mem_ops, proxy, @@ -867,6 +871,27 @@ static void virtio_mmio_vmstate_change(DeviceState *d,= bool running) } } =20 +static AddressSpace *virtio_mmio_get_dma_as(DeviceState *parent) +{ + // BusState *iommu_bus =3D qdev_get_parent_bus(parent); + BusState *iommu_bus =3D sysbus_get_default(); + VirtIOMMIOProxy *proxy =3D VIRTIO_MMIO(parent); + AddressSpace *as =3D NULL; + + if (iommu_bus && iommu_bus->iommu_ops) { + as =3D iommu_bus->iommu_ops->get_address_space( + iommu_bus, iommu_bus->iommu_opaque, proxy->stream_id); + } + + return as ? as : &address_space_memory; +} + +static bool virtio_mmio_iommu_enabled(DeviceState *parent) +{ + AddressSpace *as =3D virtio_mmio_get_dma_as(parent); + return as =3D=3D &address_space_memory; +} + static void virtio_mmio_bus_class_init(ObjectClass *klass, const void *dat= a) { BusClass *bus_class =3D BUS_CLASS(klass); @@ -884,6 +909,10 @@ static void virtio_mmio_bus_class_init(ObjectClass *kl= ass, const void *data) k->pre_plugged =3D virtio_mmio_pre_plugged; k->vmstate_change =3D virtio_mmio_vmstate_change; k->has_variable_vring_alignment =3D true; + + k->get_dma_as =3D virtio_mmio_get_dma_as; + k->iommu_enabled =3D virtio_mmio_iommu_enabled; + bus_class->max_dev =3D 1; bus_class->get_dev_path =3D virtio_mmio_bus_get_dev_path; } diff --git a/include/hw/virtio/virtio-mmio.h b/include/hw/virtio/virtio-mmi= o.h index aa49262022..f0a1a5e3ab 100644 --- a/include/hw/virtio/virtio-mmio.h +++ b/include/hw/virtio/virtio-mmio.h @@ -53,6 +53,8 @@ typedef struct VirtIOMMIOQueue { #define VIRTIO_IOMMIO_FLAG_USE_IOEVENTFD \ (1 << VIRTIO_IOMMIO_FLAG_USE_IOEVENTFD_BIT) =20 +#define VIRTIO_MMIO_STREAM_ID_OFFSET 0x50 + struct VirtIOMMIOProxy { /* Generic */ SysBusDevice parent_obj; @@ -67,6 +69,7 @@ struct VirtIOMMIOProxy { /* virtio-bus */ VirtioBusState bus; bool format_transport_address; + uint32_t stream_id; /* Fields only used for non-legacy (v2) devices */ uint32_t guest_features[2]; VirtIOMMIOQueue vqs[VIRTIO_QUEUE_MAX]; --=20 2.43.0 From nobody Mon Feb 9 15:00:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1766183176; cv=none; d=zohomail.com; s=zohoarc; b=nqil89gjZixOckWwjGp2zW+ygcnkGzxPe/UQqBHtc89hwBLekELpnXspY8uYDpIJtRENdwOH6LZH4iaX3x39qaKiFXHF7rrnOqiPDBhbNYYUbQ1RJ6SyWGCmE0iF8w+efSECJiMtDq6oQXXUBV8Zqujvs/z6WHMap8SB0Hr9azQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766183176; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=l8BqEgdpUXBLEHZZxgBu/z9VKa0uS4p2LU6CFeU+CZA=; b=dJnUk0Xau20iyu1yZmsm18Qyj7G1Z4wMXzI4NlVoz9XNFXOdQuDgTDL/IlbVHg/ItiY35pqbtSZq7jYyl4rn0suctOvJ8JKxOKwFcIDH+Sbs4yLu3GRn+h3/bd2756TWsb28Y67C8fJZTaC2Bam1uw6rqeazWb+Y/CeGGsoWvyY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766183176422144.54755335690186; Fri, 19 Dec 2025 14:26:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vWiub-0001lM-IK; Fri, 19 Dec 2025 17:25:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vWiuX-0001ic-7B for qemu-devel@nongnu.org; Fri, 19 Dec 2025 17:25:21 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vWiuV-00052n-NM for qemu-devel@nongnu.org; Fri, 19 Dec 2025 17:25:20 -0500 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-64d02c01865so465647a12.1 for ; Fri, 19 Dec 2025 14:25:19 -0800 (PST) Received: from thinkpad-t470s.. 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The property specifies the SMMU phandle and stream ID. Signed-off-by: Dmytro Terletskyi Signed-off-by: Ruslan Ruslichenko --- hw/arm/virt.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ad609bc651..ff3eb95036 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -89,6 +89,7 @@ #include "hw/uefi/var-service-api.h" #include "hw/virtio/virtio-md-pci.h" #include "hw/virtio/virtio-iommu.h" +#include "hw/virtio/virtio-mmio.h" #include "hw/char/pl011.h" #include "hw/cxl/cxl.h" #include "hw/cxl/cxl_host.h" @@ -1178,9 +1179,11 @@ static void create_gpio_devices(const VirtMachineSta= te *vms, int gpio, static void create_virtio_devices(const VirtMachineState *vms) { int i; + uint32_t stream_ids[NUM_VIRTIO_TRANSPORTS]; hwaddr size =3D vms->memmap[VIRT_MMIO].size; MachineState *ms =3D MACHINE(vms); =20 + /* We create the transports in forwards order. Since qbus_realize() * prepends (not appends) new child buses, the incrementing loop below= will * create a list of virtio-mmio buses with decreasing base addresses. @@ -1212,8 +1215,11 @@ static void create_virtio_devices(const VirtMachineS= tate *vms) int irq =3D vms->irqmap[VIRT_MMIO] + i; hwaddr base =3D vms->memmap[VIRT_MMIO].base + i * size; =20 - sysbus_create_simple("virtio-mmio", base, + DeviceState* dev =3D sysbus_create_simple("virtio-mmio", base, qdev_get_gpio_in(vms->gic, irq)); + =20 + VirtIOMMIOProxy *proxy =3D VIRTIO_MMIO(dev); + stream_ids[i] =3D proxy->stream_id; } =20 /* We add dtb nodes in reverse order so that they appear in the finish= ed @@ -1238,6 +1244,9 @@ static void create_virtio_devices(const VirtMachineSt= ate *vms) GIC_FDT_IRQ_TYPE_SPI, irq, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "iommus", + 1, vms->sysbus_iommu_phandle, + 1, stream_ids[i]); g_free(nodename); } } --=20 2.43.0 From nobody Mon Feb 9 15:00:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1766183162; cv=none; d=zohomail.com; s=zohoarc; b=F9FkvBXKedufnOZRfWia9NYTL3IWuFcd3yFOTMUjKxH0jlsGm2yYsYglf3Xl83G353hOGETE4Ro2ZhIveivDDOaB1gLqCTofV/c7h/QDw4RaE9g16HM/Bo2wfGIs44DaLA4Bubgwtb1+J2AI3yduWEqhU1++3QLZC4KxB2RIlKY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766183162; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KjDRdqd+e+TYCi+OeSwauNQsmxDgIH4owMF2laRxHAg=; b=OQBWv3pGwugw8SK1wAjPorekuFSyKJBWZ3zIa5zXO+FenTgrLmwt5gO4BMvryZlZlfv5R+tX7bRjIIqnRzr44ADxy3gC8uQ+sY+t1XD1A2LMX53WidaZvYRTrFk0crJ6DfZKrNncR8qWI85sAgsZJk+5t1F6Y6nbwSot0WQmDrE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766183162409128.87997887932784; Fri, 19 Dec 2025 14:26:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vWiud-0001mK-43; Fri, 19 Dec 2025 17:25:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vWiuc-0001m4-Jd for qemu-devel@nongnu.org; Fri, 19 Dec 2025 17:25:26 -0500 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vWiua-00053s-K5 for qemu-devel@nongnu.org; Fri, 19 Dec 2025 17:25:26 -0500 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-64b8b5410a1so1918324a12.2 for ; Fri, 19 Dec 2025 14:25:24 -0800 (PST) Received: from thinkpad-t470s.. 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Introduce generic-bus-iommu-id for each IOMMU and check if it used on init. For now, each smmu can be created via static configuration in arm/virt.c. Signed-off-by: Mirsad Ostrakovic Signed-off-by: Ruslan Ruslichenko --- hw/arm/smmu-common.c | 7 ++++--- hw/arm/virt.c | 3 ++- hw/core/bus.c | 19 ++++++++++++++++--- hw/virtio/virtio-mmio.c | 10 +++++++--- include/hw/arm/smmu-common.h | 3 ++- include/hw/qdev-core.h | 23 ++++++++++++++++++----- include/qemu/typedefs.h | 1 + 7 files changed, 50 insertions(+), 16 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 52ef49d7f6..10a551b5bc 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -981,8 +981,8 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) g_free, g_free); s->smmu_pcibus_by_busptr =3D g_hash_table_new(NULL, NULL); =20 - if (s->generic_primary_bus ) { - bus_setup_iommu(s->generic_primary_bus, &bus_smmu_ops, s); + if (s->generic_bus) { + bus_setup_iommu(s->generic_bus, s->generic_bus_iommu_id, &bus_smmu= _ops, s); return; } =20 @@ -1041,8 +1041,9 @@ static const Property smmu_dev_properties[] =3D { DEFINE_PROP_BOOL("pci_smmu_per_bus", SMMUState, pci_smmu_per_bus, fals= e), DEFINE_PROP_LINK("pci-primary-bus", SMMUState, pci_primary_bus, TYPE_PCI_BUS, PCIBus *), - DEFINE_PROP_LINK("generic-primary-bus", SMMUState, generic_primary_bus, + DEFINE_PROP_LINK("generic-bus", SMMUState, generic_bus, TYPE_BUS, BusState *), + DEFINE_PROP_UINT8("generic-bus-iommu-id", SMMUState, generic_bus_iommu= _id, 255u), }; =20 static void smmu_base_class_init(ObjectClass *klass, const void *data) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ff3eb95036..5ee21234aa 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1575,8 +1575,9 @@ static void create_smmu_sysbus(VirtMachineState *vms) if (!vmc->no_nested_smmu) { object_property_set_str(OBJECT(dev), "stage", "nested", &error_fat= al); } - object_property_set_link(OBJECT(dev), "generic-primary-bus",=20 + object_property_set_link(OBJECT(dev), "generic-bus",=20 OBJECT(sysbus_get_default()), &error_abort); + object_property_set_int(OBJECT(dev), "generic-bus-iommu-id", 0u, &erro= r_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i =3D 0; i < NUM_SMMU_IRQS; i++) { diff --git a/hw/core/bus.c b/hw/core/bus.c index 6d1483fdbd..c26a300546 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -80,7 +80,7 @@ bool bus_is_in_reset(BusState *bus) return resettable_is_in_reset(OBJECT(bus)); } =20 -void bus_setup_iommu(BusState *bus, const BusIOMMUOps *ops, void *opaque) +void bus_setup_iommu(BusState *bus, uint8_t iommu_id, const BusIOMMUOps *o= ps, void *opaque) { /* * If called, bus_setup_iommu() should provide a minimum set of @@ -89,8 +89,17 @@ void bus_setup_iommu(BusState *bus, const BusIOMMUOps *o= ps, void *opaque) assert(ops); assert(ops->get_address_space); =20 - bus->iommu_ops =3D ops; - bus->iommu_opaque =3D opaque; + /* + * Provided IOMMU index shall be in range of valid values. + */ + assert(iommu_id < (sizeof(bus->iommu) / sizeof(bus->iommu[0]))); + /* + * Allocated entry cannot be used! + */ + assert(!bus->iommu[iommu_id].used); + + bus->iommu[iommu_id].iommu_ops =3D ops; + bus->iommu[iommu_id].iommu_opaque =3D opaque; } =20 static ResettableState *bus_get_reset_state(Object *obj) @@ -230,6 +239,10 @@ static void qbus_initfn(Object *obj) { BusState *bus =3D BUS(obj); =20 + for (int i =3D 0u; i < (sizeof(bus->iommu) / sizeof(bus->iommu[0])); i= ++) { + bus->iommu[i].used =3D false; + } + QTAILQ_INIT(&bus->children); object_property_add_link(obj, QDEV_HOTPLUG_HANDLER_PROPERTY, TYPE_HOTPLUG_HANDLER, diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index 8f19492e3f..214c090ec8 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -1,3 +1,4 @@ + /* * Virtio MMIO bindings * @@ -37,6 +38,8 @@ #include "trace.h" #include "qapi/error.h" =20 +#define VIRTIO_SYSBUS_IOMMU_ID (0u) + static bool virtio_mmio_ioeventfd_enabled(DeviceState *d) { VirtIOMMIOProxy *proxy =3D VIRTIO_MMIO(d); @@ -874,13 +877,14 @@ static void virtio_mmio_vmstate_change(DeviceState *d= , bool running) static AddressSpace *virtio_mmio_get_dma_as(DeviceState *parent) { // BusState *iommu_bus =3D qdev_get_parent_bus(parent); + const uint32_t iommu_id =3D VIRTIO_SYSBUS_IOMMU_ID; BusState *iommu_bus =3D sysbus_get_default(); VirtIOMMIOProxy *proxy =3D VIRTIO_MMIO(parent); AddressSpace *as =3D NULL; =20 - if (iommu_bus && iommu_bus->iommu_ops) { - as =3D iommu_bus->iommu_ops->get_address_space( - iommu_bus, iommu_bus->iommu_opaque, proxy->stream_id); + if (iommu_bus && iommu_bus->iommu[iommu_id].iommu_ops) { + as =3D iommu_bus->iommu[iommu_id].iommu_ops->get_address_space( + iommu_bus, iommu_bus->iommu[iommu_id].iommu_opaque, proxy-= >stream_id); } =20 return as ? as : &address_space_memory; diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 670ae46930..a44c73cf0c 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -171,7 +171,8 @@ struct SMMUState { uint8_t bus_num; PCIBus *pci_primary_bus; bool pci_smmu_per_bus; /* SMMU is specific to the pci_primary_bus */ - BusState *generic_primary_bus; + BusState *generic_bus; + uint8_t generic_bus_iommu_id; }; =20 struct SMMUBaseClass { diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 2092450b90..f766213705 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -386,6 +386,20 @@ typedef struct BusIOMMUOps { AddressSpace * (*get_address_space)(BusState *bus, void *opaque, int d= evid); } BusIOMMUOps; =20 +/** + * struct BusIOMMU: + * @iommu_ops: TODO + * @iommu_opaque: TODO + * @used: TODO + */ +struct BusIOMMU { + const BusIOMMUOps *iommu_ops; + void *iommu_opaque; + bool used; +}; + +#define BUS_IOMMU_MAX 10 + /** * struct BusState: * @obj: parent object @@ -396,8 +410,7 @@ typedef struct BusIOMMUOps { * @realized: is the bus itself realized? * @full: is the bus full? * @num_children: current number of child buses - * @iommu_ops: TODO - * @iommu_opaque: TODO + * @iommu: TODO */ struct BusState { /* private: */ @@ -410,8 +423,7 @@ struct BusState { bool realized; bool full; int num_children; - const BusIOMMUOps *iommu_ops; - void *iommu_opaque; + BusIOMMU iommu[BUS_IOMMU_MAX]; =20 /** * @children: an RCU protected QTAILQ, thus readers must use RCU @@ -958,13 +970,14 @@ bool bus_is_in_reset(BusState *bus); * bus_setup_iommu() - Set up IOMMU operations for a bus * @bus: the bus to configure * @ops: IOMMU operations structure containing callback functions + * @iommu_id: TODO * @opaque: opaque data passed to IOMMU operation callbacks * * Configure IOMMU operations for the specified bus. The ops structure * must contain at least the get_address_space callback. The opaque * parameter is passed through to the operation callbacks. */ -void bus_setup_iommu(BusState *bus, const BusIOMMUOps *ops, void *opaque); +void bus_setup_iommu(BusState *bus, uint8_t iommu_id, const BusIOMMUOps *o= ps, void *opaque); =20 /* This should go away once we get rid of the NULL bus hack */ BusState *sysbus_get_default(void); diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 4a94af9665..b5d5f534f3 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -34,6 +34,7 @@ typedef struct BlockBackend BlockBackend; typedef struct BlockBackendRootState BlockBackendRootState; typedef struct BlockDriverState BlockDriverState; typedef struct BusClass BusClass; +typedef struct BusIOMMU BusIOMMU; typedef struct BusState BusState; typedef struct Chardev Chardev; typedef struct Clock Clock; --=20 2.43.0