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Fri, 19 Dec 2025 11:08:58 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Yanan Wang , Paolo Bonzini , Alwalid Salama , qemu-arm@nongnu.org, Zhao Liu , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Riku Voipio , Marcel Apfelbaum , Peter Maydell , Mahmoud Mandour , Eduardo Habkost , Mark Burton , Laurent Vivier , Pierrick Bouvier , Alexandre Iooss , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH 12/12] target/arm: allow gdb to read ARM_CP_NORAW regs (!upstream) Date: Fri, 19 Dec 2025 19:08:49 +0000 Message-ID: <20251219190849.238323-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251219190849.238323-1-alex.bennee@linaro.org> References: <20251219190849.238323-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1766171394059158500 Before this we suppress all ARM_CP_NORAW registers being listed under GDB. This includes useful registers like CurrentEL which gets tagged as ARM_CP_NO_RAW because it is one of the ARM_CP_SPECIAL_MASK registers. These are registers TCG can directly compute because we have the information at compile time but until now with no readfn. Add a .readfn to return the CurrentEL and then loosen the restrictions in arm_register_sysreg_for_feature to allow ARM_CP_NORAW registers to be read if there is a readfn available. Signed-off-by: Alex Benn=C3=A9e Message-ID: <20250507165840.401623-1-alex.bennee@linaro.org> --- vRFC - this is a useful debugging aid but a bit haphazard for up-streaming. See thread comments for details. --- target/arm/gdbstub.c | 6 +++++- target/arm/helper.c | 15 ++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 8865f27089d..205bab811da 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -292,7 +292,11 @@ static void arm_register_sysreg_for_feature(gpointer k= ey, gpointer value, CPUARMState *env =3D &cpu->env; DynamicGDBFeatureInfo *dyn_feature =3D &cpu->dyn_sysreg_feature; =20 - if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { + if (!(ri->type & ARM_CP_NO_GDB)) { + /* skip ARM_CP_NO_RAW if there are no helper functions */ + if ((ri->type & ARM_CP_NO_RAW) && !ri->readfn) { + return; + } if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state =3D=3D ARM_CP_STATE_AA64) { arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, diff --git a/target/arm/helper.c b/target/arm/helper.c index 27ebc6f29b8..1fbc45263d5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3529,6 +3529,17 @@ static void ic_ivau_write(CPUARMState *env, const AR= MCPRegInfo *ri, } #endif =20 +/* + * Normally the current_el is known at translation time and we can + * emit the result directly in TCG code. However this helper exists + * only so we can also expose CURRENTEL to gdb. + */ +static uint64_t aa64_currentel_read(CPUARMState *env, const ARMCPRegInfo *= ri) +{ + int el =3D arm_current_el(env); + return el; +} + static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* * Minimal set of EL0-visible registers. This will need to be expanded @@ -3567,7 +3578,9 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { }, { .name =3D "CURRENTEL", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 4, .crm =3D 2, - .access =3D PL1_R, .type =3D ARM_CP_CURRENTEL }, + .access =3D PL1_R, .type =3D ARM_CP_CURRENTEL, + .readfn =3D aa64_currentel_read + }, /* * Instruction cache ops. All of these except `IC IVAU` NOP because we * don't emulate caches. --=20 2.47.3