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Thu, 18 Dec 2025 20:09:49 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Max Chou , Daniel Henrique Barboza Subject: [PATCH v2] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer Date: Fri, 19 Dec 2025 12:09:43 +0800 Message-ID: <20251219040943.1570449-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1766117441763158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang Use designated initializers to initialize riscv_excp_names[] and riscv_intr_names[] so that we don't have to explicitly add "reserved" items. Also, add the missing trap names: sw_check, hw_error, virt_illegal_instruction, semihost, s_guest_external, and counter_overflow. Signed-off-by: Frank Chang Reviewed-by: Max Chou Reviewed-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 89 +++++++++++++++++++++++----------------------- 1 file changed, 45 insertions(+), 44 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index aa58ba8b99a..ee859093f78 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -305,60 +305,61 @@ const char * const riscv_rvv_regnames[] =3D { }; =20 static const char * const riscv_excp_names[] =3D { - "misaligned_fetch", - "fault_fetch", - "illegal_instruction", - "breakpoint", - "misaligned_load", - "fault_load", - "misaligned_store", - "fault_store", - "user_ecall", - "supervisor_ecall", - "hypervisor_ecall", - "machine_ecall", - "exec_page_fault", - "load_page_fault", - "reserved", - "store_page_fault", - "double_trap", - "reserved", - "reserved", - "reserved", - "guest_exec_page_fault", - "guest_load_page_fault", - "reserved", - "guest_store_page_fault", + [RISCV_EXCP_INST_ADDR_MIS] =3D "misaligned_fetch", + [RISCV_EXCP_INST_ACCESS_FAULT] =3D "fault_fetch", + [RISCV_EXCP_ILLEGAL_INST] =3D "illegal_instruction", + [RISCV_EXCP_BREAKPOINT] =3D "breakpoint", + [RISCV_EXCP_LOAD_ADDR_MIS] =3D "misaligned_load", + [RISCV_EXCP_LOAD_ACCESS_FAULT] =3D "fault_load", + [RISCV_EXCP_STORE_AMO_ADDR_MIS] =3D "misaligned_store", + [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] =3D "fault_store", + [RISCV_EXCP_U_ECALL] =3D "user_ecall", + [RISCV_EXCP_S_ECALL] =3D "supervisor_ecall", + [RISCV_EXCP_VS_ECALL] =3D "hypervisor_ecall", + [RISCV_EXCP_M_ECALL] =3D "machine_ecall", + [RISCV_EXCP_INST_PAGE_FAULT] =3D "exec_page_fault", + [RISCV_EXCP_LOAD_PAGE_FAULT] =3D "load_page_fault", + [RISCV_EXCP_STORE_PAGE_FAULT] =3D "store_page_fault", + [RISCV_EXCP_DOUBLE_TRAP] =3D "double_trap", + [RISCV_EXCP_SW_CHECK] =3D "sw_check", + [RISCV_EXCP_HW_ERR] =3D "hw_error", + [RISCV_EXCP_INST_GUEST_PAGE_FAULT] =3D "guest_exec_page_fault", + [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] =3D "guest_load_page_fault", + [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] =3D "virt_illegal_instruction", + [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] =3D "guest_store_page_fault", + [RISCV_EXCP_SEMIHOST] =3D "semihost", }; =20 static const char * const riscv_intr_names[] =3D { - "u_software", - "s_software", - "vs_software", - "m_software", - "u_timer", - "s_timer", - "vs_timer", - "m_timer", - "u_external", - "s_external", - "vs_external", - "m_external", - "reserved", - "reserved", - "reserved", - "reserved" + [IRQ_U_SOFT] =3D "u_software", + [IRQ_S_SOFT] =3D "s_software", + [IRQ_VS_SOFT] =3D "vs_software", + [IRQ_M_SOFT] =3D "m_software", + [IRQ_U_TIMER] =3D "u_timer", + [IRQ_S_TIMER] =3D "s_timer", + [IRQ_VS_TIMER] =3D "vs_timer", + [IRQ_M_TIMER] =3D "m_timer", + [IRQ_U_EXT] =3D "u_external", + [IRQ_S_EXT] =3D "s_external", + [IRQ_VS_EXT] =3D "vs_external", + [IRQ_M_EXT] =3D "m_external", + [IRQ_S_GEXT] =3D "s_guest_external", + [IRQ_PMU_OVF] =3D "counter_overflow", }; =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { if (async) { - return (cause < ARRAY_SIZE(riscv_intr_names)) ? - riscv_intr_names[cause] : "(unknown)"; + if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cau= se]) { + return riscv_intr_names[cause]; + } } else { - return (cause < ARRAY_SIZE(riscv_excp_names)) ? - riscv_excp_names[cause] : "(unknown)"; + if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cau= se]) { + return riscv_excp_names[cause]; + } } + + return "(unknown)"; } =20 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) --=20 2.43.0