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Thu, 18 Dec 2025 23:04:39 -0800 (PST) Date: Fri, 19 Dec 2025 07:04:14 +0000 In-Reply-To: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> Mime-Version: 1.0 References: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> X-Mailer: b4 0.14.2 Message-ID: <20251219-aspeed-sgpio-v5-1-fd5593178144@google.com> Subject: [PATCH v5 1/6] hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou Content-Type: text/plain; charset="utf-8" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3B_lEaQYKCl4UQ7EJVCKKCHA.8KIMAIQ-9ARAHJKJCJQ.KNC@flex--yubinz.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1766127926949158500 Content-Transfer-Encoding: quoted-printable This initial implementation includes the basic device structure, memory-mapped register definitions, and read/write handlers for the SGPIO control registers. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen --- include/hw/gpio/aspeed_sgpio.h | 66 +++++++++++++++++++ hw/gpio/aspeed_sgpio.c | 145 +++++++++++++++++++++++++++++++++++++= ++++ hw/gpio/meson.build | 1 + 3 files changed, 212 insertions(+) diff --git a/include/hw/gpio/aspeed_sgpio.h b/include/hw/gpio/aspeed_sgpio.h new file mode 100644 index 0000000000000000000000000000000000000000..60279a597c722f94fba406d60cb= 30a52ef9544bc --- /dev/null +++ b/include/hw/gpio/aspeed_sgpio.h @@ -0,0 +1,66 @@ +/* + * ASPEED Serial GPIO Controller + * + * Copyright 2025 Google LLC. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_SGPIO_H +#define ASPEED_SGPIO_H + +#include "hw/sysbus.h" +#include "qom/object.h" +#include "hw/registerfields.h" + +#define TYPE_ASPEED_SGPIO "aspeed.sgpio" +OBJECT_DECLARE_TYPE(AspeedSGPIOState, AspeedSGPIOClass, ASPEED_SGPIO) + +#define ASPEED_SGPIO_MAX_PIN_PAIR 256 +#define ASPEED_SGPIO_MAX_INT 8 + +/* AST2700 SGPIO Register Address Offsets */ +REG32(SGPIO_INT_STATUS_0, 0x40) +REG32(SGPIO_INT_STATUS_1, 0x44) +REG32(SGPIO_INT_STATUS_2, 0x48) +REG32(SGPIO_INT_STATUS_3, 0x4C) +REG32(SGPIO_INT_STATUS_4, 0x50) +REG32(SGPIO_INT_STATUS_5, 0x54) +REG32(SGPIO_INT_STATUS_6, 0x58) +REG32(SGPIO_INT_STATUS_7, 0x5C) +/* AST2700 SGPIO_0 - SGPIO_255 Control Register */ +REG32(SGPIO_0_CONTROL, 0x80) + SHARED_FIELD(SGPIO_SERIAL_OUT_VAL, 0, 1) + SHARED_FIELD(SGPIO_PARALLEL_OUT_VAL, 1, 1) + SHARED_FIELD(SGPIO_INT_EN, 2, 1) + SHARED_FIELD(SGPIO_INT_TYPE, 3, 3) + SHARED_FIELD(SGPIO_RESET_POLARITY, 6, 1) + SHARED_FIELD(SGPIO_RESERVED_1, 7, 2) + SHARED_FIELD(SGPIO_INPUT_MASK, 9, 1) + SHARED_FIELD(SGPIO_PARALLEL_EN, 10, 1) + SHARED_FIELD(SGPIO_PARALLEL_IN_MODE, 11, 1) + SHARED_FIELD(SGPIO_INT_STATUS, 12, 1) + SHARED_FIELD(SGPIO_SERIAL_IN_VAL, 13, 1) + SHARED_FIELD(SGPIO_PARALLEL_IN_VAL, 14, 1) + SHARED_FIELD(SGPIO_RESERVED_2, 15, 12) + SHARED_FIELD(SGPIO_WRITE_PROTECT, 31, 1) +REG32(SGPIO_255_CONTROL, 0x47C) + +struct AspeedSGPIOClass { + SysBusDeviceClass parent_class; + uint32_t nr_sgpio_pin_pairs; + uint64_t mem_size; + const MemoryRegionOps *reg_ops; +}; + +struct AspeedSGPIOState { + /* */ + SysBusDevice parent; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq irq; + uint32_t ctrl_regs[ASPEED_SGPIO_MAX_PIN_PAIR]; + uint32_t int_regs[ASPEED_SGPIO_MAX_INT]; +}; + +#endif /* ASPEED_SGPIO_H */ diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c new file mode 100644 index 0000000000000000000000000000000000000000..167a72c41e96c67bd1867a19e2b= 1706f5bd074e4 --- /dev/null +++ b/hw/gpio/aspeed_sgpio.c @@ -0,0 +1,145 @@ +/* + * ASPEED Serial GPIO Controller + * + * Copyright 2025 Google LLC. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "hw/qdev-properties.h" +#include "hw/gpio/aspeed_sgpio.h" + +static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s, + uint32_t reg) +{ + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_GET_CLASS(s); + uint32_t idx =3D reg - R_SGPIO_0_CONTROL; + if (idx >=3D agc->nr_sgpio_pin_pairs) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n= ", + __func__, idx); + return 0; + } + return s->ctrl_regs[idx]; +} + +static void aspeed_sgpio_2700_write_control_reg(AspeedSGPIOState *s, + uint32_t reg, uint64_t data) +{ + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_GET_CLASS(s); + uint32_t idx =3D reg - R_SGPIO_0_CONTROL; + if (idx >=3D agc->nr_sgpio_pin_pairs) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n= ", + __func__, idx); + return; + } + s->ctrl_regs[idx] =3D data; +} + +static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset, + uint32_t size) +{ + AspeedSGPIOState *s =3D ASPEED_SGPIO(opaque); + uint64_t value =3D 0; + uint64_t reg; + + reg =3D offset >> 2; + + switch (reg) { + case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: + value =3D aspeed_sgpio_2700_read_control_reg(s, reg); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return 0; + } + + return value; +} + +static void aspeed_sgpio_2700_write(void *opaque, hwaddr offset, uint64_t = data, + uint32_t size) +{ + AspeedSGPIOState *s =3D ASPEED_SGPIO(opaque); + uint64_t reg; + + reg =3D offset >> 2; + + switch (reg) { + case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: + aspeed_sgpio_2700_write_control_reg(s, reg, data); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return; + } +} + +static const MemoryRegionOps aspeed_sgpio_2700_ops =3D { + .read =3D aspeed_sgpio_2700_read, + .write =3D aspeed_sgpio_2700_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static void aspeed_sgpio_realize(DeviceState *dev, Error **errp) +{ + AspeedSGPIOState *s =3D ASPEED_SGPIO(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_GET_CLASS(s); + + /* Interrupt parent line */ + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s, + TYPE_ASPEED_SGPIO, agc->mem_size); + + sysbus_init_mmio(sbd, &s->iomem); +} + +static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_sgpio_realize; + dc->desc =3D "Aspeed SGPIO Controller"; +} + +static void aspeed_sgpio_2700_class_init(ObjectClass *klass, const void *d= ata) +{ + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_CLASS(klass); + agc->nr_sgpio_pin_pairs =3D ASPEED_SGPIO_MAX_PIN_PAIR; + agc->mem_size =3D 0x1000; + agc->reg_ops =3D &aspeed_sgpio_2700_ops; +} + +static const TypeInfo aspeed_sgpio_info =3D { + .name =3D TYPE_ASPEED_SGPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedSGPIOState), + .class_size =3D sizeof(AspeedSGPIOClass), + .class_init =3D aspeed_sgpio_class_init, + .abstract =3D true, +}; + +static const TypeInfo aspeed_sgpio_ast2700_info =3D { + .name =3D TYPE_ASPEED_SGPIO "-ast2700", + .parent =3D TYPE_ASPEED_SGPIO, + .class_init =3D aspeed_sgpio_2700_class_init, +}; + +static void aspeed_sgpio_register_types(void) +{ + type_register_static(&aspeed_sgpio_info); + type_register_static(&aspeed_sgpio_ast2700_info); +} + +type_init(aspeed_sgpio_register_types); diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 74840619c01bf4d9a02c058c434c3ec9d2a55bee..6a67ee958faace69ffd3fe08e8a= de31ced0faf7e 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -16,5 +16,6 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( )) system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio= .c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sgpio.c')) system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c')) --=20 2.52.0.351.gbe84eed79e-goog