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Thu, 18 Dec 2025 23:04:39 -0800 (PST) Date: Fri, 19 Dec 2025 07:04:14 +0000 In-Reply-To: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> Mime-Version: 1.0 References: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> X-Mailer: b4 0.14.2 Message-ID: <20251219-aspeed-sgpio-v5-1-fd5593178144@google.com> Subject: [PATCH v5 1/6] hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou Content-Type: text/plain; charset="utf-8" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3B_lEaQYKCl4UQ7EJVCKKCHA.8KIMAIQ-9ARAHJKJCJQ.KNC@flex--yubinz.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1766127926949158500 Content-Transfer-Encoding: quoted-printable This initial implementation includes the basic device structure, memory-mapped register definitions, and read/write handlers for the SGPIO control registers. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen --- include/hw/gpio/aspeed_sgpio.h | 66 +++++++++++++++++++ hw/gpio/aspeed_sgpio.c | 145 +++++++++++++++++++++++++++++++++++++= ++++ hw/gpio/meson.build | 1 + 3 files changed, 212 insertions(+) diff --git a/include/hw/gpio/aspeed_sgpio.h b/include/hw/gpio/aspeed_sgpio.h new file mode 100644 index 0000000000000000000000000000000000000000..60279a597c722f94fba406d60cb= 30a52ef9544bc --- /dev/null +++ b/include/hw/gpio/aspeed_sgpio.h @@ -0,0 +1,66 @@ +/* + * ASPEED Serial GPIO Controller + * + * Copyright 2025 Google LLC. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_SGPIO_H +#define ASPEED_SGPIO_H + +#include "hw/sysbus.h" +#include "qom/object.h" +#include "hw/registerfields.h" + +#define TYPE_ASPEED_SGPIO "aspeed.sgpio" +OBJECT_DECLARE_TYPE(AspeedSGPIOState, AspeedSGPIOClass, ASPEED_SGPIO) + +#define ASPEED_SGPIO_MAX_PIN_PAIR 256 +#define ASPEED_SGPIO_MAX_INT 8 + +/* AST2700 SGPIO Register Address Offsets */ +REG32(SGPIO_INT_STATUS_0, 0x40) +REG32(SGPIO_INT_STATUS_1, 0x44) +REG32(SGPIO_INT_STATUS_2, 0x48) +REG32(SGPIO_INT_STATUS_3, 0x4C) +REG32(SGPIO_INT_STATUS_4, 0x50) +REG32(SGPIO_INT_STATUS_5, 0x54) +REG32(SGPIO_INT_STATUS_6, 0x58) +REG32(SGPIO_INT_STATUS_7, 0x5C) +/* AST2700 SGPIO_0 - SGPIO_255 Control Register */ +REG32(SGPIO_0_CONTROL, 0x80) + SHARED_FIELD(SGPIO_SERIAL_OUT_VAL, 0, 1) + SHARED_FIELD(SGPIO_PARALLEL_OUT_VAL, 1, 1) + SHARED_FIELD(SGPIO_INT_EN, 2, 1) + SHARED_FIELD(SGPIO_INT_TYPE, 3, 3) + SHARED_FIELD(SGPIO_RESET_POLARITY, 6, 1) + SHARED_FIELD(SGPIO_RESERVED_1, 7, 2) + SHARED_FIELD(SGPIO_INPUT_MASK, 9, 1) + SHARED_FIELD(SGPIO_PARALLEL_EN, 10, 1) + SHARED_FIELD(SGPIO_PARALLEL_IN_MODE, 11, 1) + SHARED_FIELD(SGPIO_INT_STATUS, 12, 1) + SHARED_FIELD(SGPIO_SERIAL_IN_VAL, 13, 1) + SHARED_FIELD(SGPIO_PARALLEL_IN_VAL, 14, 1) + SHARED_FIELD(SGPIO_RESERVED_2, 15, 12) + SHARED_FIELD(SGPIO_WRITE_PROTECT, 31, 1) +REG32(SGPIO_255_CONTROL, 0x47C) + +struct AspeedSGPIOClass { + SysBusDeviceClass parent_class; + uint32_t nr_sgpio_pin_pairs; + uint64_t mem_size; + const MemoryRegionOps *reg_ops; +}; + +struct AspeedSGPIOState { + /* */ + SysBusDevice parent; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq irq; + uint32_t ctrl_regs[ASPEED_SGPIO_MAX_PIN_PAIR]; + uint32_t int_regs[ASPEED_SGPIO_MAX_INT]; +}; + +#endif /* ASPEED_SGPIO_H */ diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c new file mode 100644 index 0000000000000000000000000000000000000000..167a72c41e96c67bd1867a19e2b= 1706f5bd074e4 --- /dev/null +++ b/hw/gpio/aspeed_sgpio.c @@ -0,0 +1,145 @@ +/* + * ASPEED Serial GPIO Controller + * + * Copyright 2025 Google LLC. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "hw/qdev-properties.h" +#include "hw/gpio/aspeed_sgpio.h" + +static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s, + uint32_t reg) +{ + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_GET_CLASS(s); + uint32_t idx =3D reg - R_SGPIO_0_CONTROL; + if (idx >=3D agc->nr_sgpio_pin_pairs) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n= ", + __func__, idx); + return 0; + } + return s->ctrl_regs[idx]; +} + +static void aspeed_sgpio_2700_write_control_reg(AspeedSGPIOState *s, + uint32_t reg, uint64_t data) +{ + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_GET_CLASS(s); + uint32_t idx =3D reg - R_SGPIO_0_CONTROL; + if (idx >=3D agc->nr_sgpio_pin_pairs) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n= ", + __func__, idx); + return; + } + s->ctrl_regs[idx] =3D data; +} + +static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset, + uint32_t size) +{ + AspeedSGPIOState *s =3D ASPEED_SGPIO(opaque); + uint64_t value =3D 0; + uint64_t reg; + + reg =3D offset >> 2; + + switch (reg) { + case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: + value =3D aspeed_sgpio_2700_read_control_reg(s, reg); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return 0; + } + + return value; +} + +static void aspeed_sgpio_2700_write(void *opaque, hwaddr offset, uint64_t = data, + uint32_t size) +{ + AspeedSGPIOState *s =3D ASPEED_SGPIO(opaque); + uint64_t reg; + + reg =3D offset >> 2; + + switch (reg) { + case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: + aspeed_sgpio_2700_write_control_reg(s, reg, data); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return; + } +} + +static const MemoryRegionOps aspeed_sgpio_2700_ops =3D { + .read =3D aspeed_sgpio_2700_read, + .write =3D aspeed_sgpio_2700_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static void aspeed_sgpio_realize(DeviceState *dev, Error **errp) +{ + AspeedSGPIOState *s =3D ASPEED_SGPIO(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_GET_CLASS(s); + + /* Interrupt parent line */ + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s, + TYPE_ASPEED_SGPIO, agc->mem_size); + + sysbus_init_mmio(sbd, &s->iomem); +} + +static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_sgpio_realize; + dc->desc =3D "Aspeed SGPIO Controller"; +} + +static void aspeed_sgpio_2700_class_init(ObjectClass *klass, const void *d= ata) +{ + AspeedSGPIOClass *agc =3D ASPEED_SGPIO_CLASS(klass); + agc->nr_sgpio_pin_pairs =3D ASPEED_SGPIO_MAX_PIN_PAIR; + agc->mem_size =3D 0x1000; + agc->reg_ops =3D &aspeed_sgpio_2700_ops; +} + +static const TypeInfo aspeed_sgpio_info =3D { + .name =3D TYPE_ASPEED_SGPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedSGPIOState), + .class_size =3D sizeof(AspeedSGPIOClass), + .class_init =3D aspeed_sgpio_class_init, + .abstract =3D true, +}; + +static const TypeInfo aspeed_sgpio_ast2700_info =3D { + .name =3D TYPE_ASPEED_SGPIO "-ast2700", + .parent =3D TYPE_ASPEED_SGPIO, + .class_init =3D aspeed_sgpio_2700_class_init, +}; + +static void aspeed_sgpio_register_types(void) +{ + type_register_static(&aspeed_sgpio_info); + type_register_static(&aspeed_sgpio_ast2700_info); +} + +type_init(aspeed_sgpio_register_types); diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 74840619c01bf4d9a02c058c434c3ec9d2a55bee..6a67ee958faace69ffd3fe08e8a= de31ced0faf7e 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -16,5 +16,6 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( )) system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio= .c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sgpio.c')) system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c')) --=20 2.52.0.351.gbe84eed79e-goog From nobody Sat Feb 7 06:55:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; 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Thu, 18 Dec 2025 23:04:41 -0800 (PST) Date: Fri, 19 Dec 2025 07:04:15 +0000 In-Reply-To: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> Mime-Version: 1.0 References: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> X-Mailer: b4 0.14.2 Message-ID: <20251219-aspeed-sgpio-v5-2-fd5593178144@google.com> Subject: [PATCH v5 2/6] hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou Content-Type: text/plain; charset="utf-8" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::104a; envelope-from=3CflEaQYKCmAWS9GLXEMMEJC.AMKOCKS-BCTCJLMLELS.MPE@flex--yubinz.bounces.google.com; helo=mail-pj1-x104a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1766127974499158500 Content-Transfer-Encoding: quoted-printable The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are implemented to get and set the level of individual SGPIO pins. These are then exposed as boolean properties on the SGPIO device object. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen --- hw/gpio/aspeed_sgpio.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c index 167a72c41e96c67bd1867a19e2b1706f5bd074e4..927c711cb3aef889c47c9a9156f= e4241981c5efa 100644 --- a/hw/gpio/aspeed_sgpio.c +++ b/hw/gpio/aspeed_sgpio.c @@ -51,6 +51,8 @@ static uint64_t aspeed_sgpio_2700_read(void *opaque, hwad= dr offset, reg =3D offset >> 2; =20 switch (reg) { + case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7: + break; case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: value =3D aspeed_sgpio_2700_read_control_reg(s, reg); break; @@ -82,6 +84,73 @@ static void aspeed_sgpio_2700_write(void *opaque, hwaddr= offset, uint64_t data, } } =20 +static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin) +{ + uint32_t value =3D s->ctrl_regs[pin >> 1]; + bool is_input =3D !(pin % 2); + uint32_t bit_mask =3D 0; + + if (is_input) { + bit_mask =3D SGPIO_SERIAL_IN_VAL_MASK; + } else { + bit_mask =3D SGPIO_SERIAL_OUT_VAL_MASK; + } + + return value & bit_mask; +} + +static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, bool = level) +{ + uint32_t value =3D s->ctrl_regs[pin >> 1]; + bool is_input =3D !(pin % 2); + uint32_t bit_mask =3D 0; + + if (is_input) { + bit_mask =3D SGPIO_SERIAL_IN_VAL_MASK; + } else { + bit_mask =3D SGPIO_SERIAL_OUT_VAL_MASK; + } + + if (level) { + value |=3D bit_mask; + } else { + value &=3D ~bit_mask; + } + s->ctrl_regs[pin >> 1] =3D value; +} + +static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool level =3D true; + int pin =3D 0xfff; + AspeedSGPIOState *s =3D ASPEED_SGPIO(obj); + + if (sscanf(name, "sgpio%03d", &pin) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + level =3D aspeed_sgpio_get_pin_level(s, pin); + visit_type_bool(v, name, &level, errp); +} + +static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool level; + int pin =3D 0xfff; + AspeedSGPIOState *s =3D ASPEED_SGPIO(obj); + + if (!visit_type_bool(v, name, &level, errp)) { + return; + } + if (sscanf(name, "sgpio%03d", &pin) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + aspeed_sgpio_set_pin_level(s, pin, level); +} + static const MemoryRegionOps aspeed_sgpio_2700_ops =3D { .read =3D aspeed_sgpio_2700_read, .write =3D aspeed_sgpio_2700_write, @@ -105,6 +174,15 @@ static void aspeed_sgpio_realize(DeviceState *dev, Err= or **errp) sysbus_init_mmio(sbd, &s->iomem); } =20 +static void aspeed_sgpio_init(Object *obj) +{ + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) { + g_autofree char *name =3D g_strdup_printf("sgpio%03d", i); + object_property_add(obj, name, "bool", aspeed_sgpio_get_pin, + aspeed_sgpio_set_pin, NULL, NULL); + } +} + static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -134,6 +212,7 @@ static const TypeInfo aspeed_sgpio_ast2700_info =3D { .name =3D TYPE_ASPEED_SGPIO "-ast2700", .parent =3D TYPE_ASPEED_SGPIO, .class_init =3D aspeed_sgpio_2700_class_init, + .instance_init =3D aspeed_sgpio_init, }; =20 static void aspeed_sgpio_register_types(void) --=20 2.52.0.351.gbe84eed79e-goog From nobody Sat Feb 7 06:55:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; 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Thu, 18 Dec 2025 23:04:43 -0800 (PST) Date: Fri, 19 Dec 2025 07:04:16 +0000 In-Reply-To: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> Mime-Version: 1.0 References: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> X-Mailer: b4 0.14.2 Message-ID: <20251219-aspeed-sgpio-v5-3-fd5593178144@google.com> Subject: [PATCH v5 3/6] hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou Content-Type: text/plain; charset="utf-8" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3C_lEaQYKCmIYUBINZGOOGLE.COMQEMU-DEVELNONGNU.ORG@flex--yubinz.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1766127972696158500 Content-Transfer-Encoding: quoted-printable The SGPIO controller can generate interrupts based on various pin state changes, such as rising/falling edges or high/low levels. This change adds the necessary logic to detect these events, update the interrupt status registers, and signal the interrupt to the SoC. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen --- include/hw/gpio/aspeed_sgpio.h | 2 + hw/gpio/aspeed_sgpio.c | 126 +++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 126 insertions(+), 2 deletions(-) diff --git a/include/hw/gpio/aspeed_sgpio.h b/include/hw/gpio/aspeed_sgpio.h index 60279a597c722f94fba406d60cb30a52ef9544bc..8a11a9998c013cb2e4be99690ec= d7bcd9dcb5815 100644 --- a/include/hw/gpio/aspeed_sgpio.h +++ b/include/hw/gpio/aspeed_sgpio.h @@ -58,7 +58,9 @@ struct AspeedSGPIOState { =20 /*< public >*/ MemoryRegion iomem; + int pending; qemu_irq irq; + qemu_irq sgpios[ASPEED_SGPIO_MAX_PIN_PAIR]; uint32_t ctrl_regs[ASPEED_SGPIO_MAX_PIN_PAIR]; uint32_t int_regs[ASPEED_SGPIO_MAX_INT]; }; diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c index 927c711cb3aef889c47c9a9156fe4241981c5efa..a058a3edcabd346a048e2b61740= a3972a5e5a871 100644 --- a/hw/gpio/aspeed_sgpio.c +++ b/hw/gpio/aspeed_sgpio.c @@ -12,9 +12,130 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/gpio/aspeed_sgpio.h" =20 +/* + * For each set of gpios there are three sensitivity registers that contr= ol + * the interrupt trigger mode. + * + * | 2 | 1 | 0 | trigger mode + * ----------------------------- + * | 0 | 0 | 0 | falling-edge + * | 0 | 0 | 1 | rising-edge + * | 0 | 1 | 0 | level-low + * | 0 | 1 | 1 | level-high + * | 1 | X | X | dual-edge + */ + +/* GPIO Interrupt Triggers */ +#define ASPEED_FALLING_EDGE 0 +#define ASPEED_RISING_EDGE 1 +#define ASPEED_LEVEL_LOW 2 +#define ASPEED_LEVEL_HIGH 3 +#define ASPEED_DUAL_EDGE 4 + +static void aspeed_clear_irq(AspeedSGPIOState *s, int idx) +{ + uint32_t reg_index =3D idx / 32; + uint32_t bit_index =3D idx % 32; + uint32_t pending =3D extract32(s->int_regs[reg_index], bit_index, 1); + + assert(s->pending >=3D pending); + + /* No change to s->pending if pending is 0 */ + s->pending -=3D pending; + + /* + * The write acknowledged the interrupt regardless of whether it + * was pending or not. The post-condition is that it mustn't be + * pending. Unconditionally clear the status bit. + */ + s->int_regs[reg_index] =3D deposit32(s->int_regs[reg_index], bit_index= , 1, 0); +} + +static void aspeed_evaluate_irq(AspeedSGPIOState *s, int sgpio_prev_high, + int sgpio_curr_high, int idx) +{ + uint32_t ctrl =3D s->ctrl_regs[idx]; + uint32_t falling_edge =3D 0, rising_edge =3D 0; + uint32_t int_trigger =3D SHARED_FIELD_EX32(ctrl, SGPIO_INT_TYPE); + uint32_t int_enabled =3D SHARED_FIELD_EX32(ctrl, SGPIO_INT_EN); + uint32_t reg_index =3D idx / 32; + uint32_t bit_index =3D idx % 32; + + if (!int_enabled) { + return; + } + + /* Detect edges */ + if (sgpio_curr_high && !sgpio_prev_high) { + rising_edge =3D 1; + } else if (!sgpio_curr_high && sgpio_prev_high) { + falling_edge =3D 1; + } + + if (((int_trigger =3D=3D ASPEED_FALLING_EDGE) && falling_edge) || + ((int_trigger =3D=3D ASPEED_RISING_EDGE) && rising_edge) || + ((int_trigger =3D=3D ASPEED_LEVEL_LOW) && !sgpio_curr_high) || + ((int_trigger =3D=3D ASPEED_LEVEL_HIGH) && sgpio_curr_high) || + ((int_trigger >=3D ASPEED_DUAL_EDGE) && (rising_edge || falling_e= dge))) + { + s->int_regs[reg_index] =3D deposit32(s->int_regs[reg_index], + bit_index, 1, 1); + /* Trigger the VIC IRQ */ + s->pending++; + } +} + +static void aspeed_sgpio_update(AspeedSGPIOState *s, uint32_t idx, + uint32_t value) +{ + uint32_t old =3D s->ctrl_regs[idx]; + uint32_t new =3D value; + uint32_t diff =3D (old ^ new); + if (diff) { + /* If the interrupt clear bit is set */ + if (SHARED_FIELD_EX32(new, SGPIO_INT_STATUS)) { + aspeed_clear_irq(s, idx); + /* Clear the interrupt clear bit */ + new &=3D ~SGPIO_INT_STATUS_MASK; + } + + /* Update the control register. */ + s->ctrl_regs[idx] =3D new; + + /* If the output value is changed */ + if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_OUT_VAL)) { + /* ...trigger the line-state IRQ */ + qemu_set_irq(s->sgpios[idx], 1); + } + + /* If the input value is changed */ + if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_IN_VAL)) { + aspeed_evaluate_irq(s, + SHARED_FIELD_EX32(old, SGPIO_SERIAL_IN_VAL), + SHARED_FIELD_EX32(new, SGPIO_SERIAL_IN_VAL), + idx); + } + } + qemu_set_irq(s->irq, !!(s->pending)); +} + +static uint64_t aspeed_sgpio_2700_read_int_status_reg(AspeedSGPIOState *s, + uint32_t reg) +{ + uint32_t idx =3D reg - R_SGPIO_INT_STATUS_0; + if (idx >=3D ASPEED_SGPIO_MAX_INT) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: interrupt status index: %d, out of bounds\n", + __func__, idx); + return 0; + } + return s->int_regs[idx]; +} + static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s, uint32_t reg) { @@ -38,7 +159,7 @@ static void aspeed_sgpio_2700_write_control_reg(AspeedSG= PIOState *s, __func__, idx); return; } - s->ctrl_regs[idx] =3D data; + aspeed_sgpio_update(s, idx, data); } =20 static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset, @@ -52,6 +173,7 @@ static uint64_t aspeed_sgpio_2700_read(void *opaque, hwa= ddr offset, =20 switch (reg) { case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7: + value =3D aspeed_sgpio_2700_read_int_status_reg(s, reg); break; case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: value =3D aspeed_sgpio_2700_read_control_reg(s, reg); @@ -116,7 +238,7 @@ static void aspeed_sgpio_set_pin_level(AspeedSGPIOState= *s, int pin, bool level) } else { value &=3D ~bit_mask; } - s->ctrl_regs[pin >> 1] =3D value; + aspeed_sgpio_update(s, pin >> 1, value); } =20 static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name, --=20 2.52.0.351.gbe84eed79e-goog From nobody Sat Feb 7 06:55:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1766127924; cv=none; d=zohomail.com; s=zohoarc; b=GX1TZJZDTvXezEnPfQW0Dv3W0mhbcUbzmNVLRqSVDG5vD59IqhQZJoouxIDH8uRbgsAuYMlwepaJQvNRcZAjYg5Xc8uPPAG43no6nf7uthqdh1RnkhoTEWi6LphKx+TO4u0nMMfs4zgwHtyFEnR+rsdsW7ZxxSfgD8+OEsXw2K8= ARC-Message-Signature: i=1; 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Thu, 18 Dec 2025 23:04:44 -0800 (PST) Date: Fri, 19 Dec 2025 07:04:17 +0000 In-Reply-To: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> Mime-Version: 1.0 References: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> X-Mailer: b4 0.14.2 Message-ID: <20251219-aspeed-sgpio-v5-4-fd5593178144@google.com> Subject: [PATCH v5 4/6] hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou , "=?utf-8?q?C=C3=A9dric_Le_Goater?=" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::124a; envelope-from=3DPlEaQYKCmMZVCJOaHPPHMF.DPNRFNV-EFWFMOPOHOV.PSH@flex--yubinz.bounces.google.com; helo=mail-dl1-x124a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1766127926936158500 This commit updates the Aspeed SoC model to support two SGPIO controllers, reflecting the hardware capabilities of the AST2700 The memory map and interrupt map are updated to include entries for two SGPIO controllers (SGPIOM0 and SGPIOM1). This change is a prerequisite for the full implementation of the SGPIO device model. Signed-off-by: Yubin Zou Reviewed-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 8 ++++++-- hw/arm/aspeed_ast10x0.c | 6 +++--- hw/arm/aspeed_ast27x0.c | 10 ++++++++++ 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 4b8e599f1a53bfb2e4d3196d5495cd316f799354..18ff961a38508c5df83b46e187f= 732d736443f20 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -32,6 +32,7 @@ #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" #include "hw/gpio/aspeed_gpio.h" +#include "hw/gpio/aspeed_sgpio.h" #include "hw/sd/aspeed_sdhci.h" #include "hw/usb/hcd-ehci.h" #include "qom/object.h" @@ -46,6 +47,7 @@ #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 #define ASPEED_SPIS_NUM 3 +#define ASPEED_SGPIO_NUM 2 #define ASPEED_EHCIS_NUM 4 #define ASPEED_WDTS_NUM 8 #define ASPEED_CPUS_NUM 4 @@ -89,6 +91,7 @@ struct AspeedSoCState { AspeedMiiState mii[ASPEED_MACS_NUM]; AspeedGPIOState gpio; AspeedGPIOState gpio_1_8v; + AspeedSGPIOState sgpiom[ASPEED_SGPIO_NUM]; AspeedSDHCIState sdhci; AspeedSDHCIState emmc; AspeedLPCState lpc; @@ -106,7 +109,6 @@ struct AspeedSoCState { UnimplementedDeviceState pwm; UnimplementedDeviceState espi; UnimplementedDeviceState udc; - UnimplementedDeviceState sgpiom; UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; @@ -166,6 +168,7 @@ struct AspeedSoCClass { uint64_t secsram_size; int pcie_num; int spis_num; + int sgpio_num; int ehcis_num; int wdts_num; int macs_num; @@ -221,6 +224,8 @@ enum { ASPEED_DEV_SDHCI, ASPEED_DEV_GPIO, ASPEED_DEV_GPIO_1_8V, + ASPEED_DEV_SGPIOM0, + ASPEED_DEV_SGPIOM1, ASPEED_DEV_RTC, ASPEED_DEV_TIMER1, ASPEED_DEV_TIMER2, @@ -263,7 +268,6 @@ enum { ASPEED_DEV_I3C, ASPEED_DEV_ESPI, ASPEED_DEV_UDC, - ASPEED_DEV_SGPIOM, ASPEED_DEV_JTAG0, ASPEED_DEV_JTAG1, ASPEED_DEV_FSI1, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 7f49c13391be0b923e317409a0fccfa741f5e658..c141cc080422579ca6b6965369d= 84dfbe416247b 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -36,7 +36,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] =3D { [ASPEED_DEV_ESPI] =3D 0x7E6EE000, [ASPEED_DEV_SBC] =3D 0x7E6F2000, [ASPEED_DEV_GPIO] =3D 0x7E780000, - [ASPEED_DEV_SGPIOM] =3D 0x7E780500, + [ASPEED_DEV_SGPIOM0] =3D 0x7E780500, [ASPEED_DEV_TIMER1] =3D 0x7E782000, [ASPEED_DEV_UART1] =3D 0x7E783000, [ASPEED_DEV_UART2] =3D 0x7E78D000, @@ -94,7 +94,7 @@ static const int aspeed_soc_ast1030_irqmap[] =3D { [ASPEED_DEV_I2C] =3D 110, /* 110 ~ 123 */ [ASPEED_DEV_KCS] =3D 138, /* 138 -> 142 */ [ASPEED_DEV_UDC] =3D 9, - [ASPEED_DEV_SGPIOM] =3D 51, + [ASPEED_DEV_SGPIOM0] =3D 51, [ASPEED_DEV_JTAG0] =3D 27, [ASPEED_DEV_JTAG1] =3D 53, }; @@ -427,7 +427,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) sc->memmap[ASPEED_DEV_UDC], 0x1000); aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom", - sc->memmap[ASPEED_DEV_SGPIOM], 0x100); + sc->memmap[ASPEED_DEV_SGPIOM0], 0x100); =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag", diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index c484bcd4e22fb49faf9c16992ae2cdfd6cd82da4..e5f04bd16e80696e41005d9062a= 6df6d060b8088 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -69,6 +69,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_ADC] =3D 0x14C00000, [ASPEED_DEV_SCUIO] =3D 0x14C02000, [ASPEED_DEV_GPIO] =3D 0x14C0B000, + [ASPEED_DEV_SGPIOM0] =3D 0x14C0C000, + [ASPEED_DEV_SGPIOM1] =3D 0x14C0D000, [ASPEED_DEV_I2C] =3D 0x14C0F000, [ASPEED_DEV_INTCIO] =3D 0x14C18000, [ASPEED_DEV_PCIE_PHY2] =3D 0x14C1C000, @@ -122,6 +124,8 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D { [ASPEED_DEV_KCS] =3D 128, [ASPEED_DEV_ADC] =3D 130, [ASPEED_DEV_GPIO] =3D 130, + [ASPEED_DEV_SGPIOM0] =3D 130, + [ASPEED_DEV_SGPIOM1] =3D 130, [ASPEED_DEV_I2C] =3D 130, [ASPEED_DEV_FMC] =3D 131, [ASPEED_DEV_WDT] =3D 131, @@ -173,6 +177,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_I2C] =3D 194, [ASPEED_DEV_ADC] =3D 194, [ASPEED_DEV_GPIO] =3D 194, + [ASPEED_DEV_SGPIOM0] =3D 194, + [ASPEED_DEV_SGPIOM1] =3D 194, [ASPEED_DEV_FMC] =3D 195, [ASPEED_DEV_WDT] =3D 195, [ASPEED_DEV_PWM] =3D 195, @@ -214,6 +220,8 @@ static const int ast2700_gic130_gic194_intcmap[] =3D { [ASPEED_DEV_I2C] =3D 0, [ASPEED_DEV_ADC] =3D 16, [ASPEED_DEV_GPIO] =3D 18, + [ASPEED_DEV_SGPIOM0] =3D 21, + [ASPEED_DEV_SGPIOM1] =3D 24, }; =20 /* GICINT 131 */ @@ -1061,6 +1069,7 @@ static void aspeed_soc_ast2700a0_class_init(ObjectCla= ss *oc, const void *data) sc->sram_size =3D 0x20000; sc->pcie_num =3D 0; sc->spis_num =3D 3; + sc->sgpio_num =3D 2; sc->ehcis_num =3D 2; sc->wdts_num =3D 8; sc->macs_num =3D 1; @@ -1089,6 +1098,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->sram_size =3D 0x20000; sc->pcie_num =3D 3; sc->spis_num =3D 3; + sc->sgpio_num =3D 2; sc->ehcis_num =3D 4; sc->wdts_num =3D 8; sc->macs_num =3D 3; --=20 2.52.0.351.gbe84eed79e-goog From nobody Sat Feb 7 06:55:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1766127969; cv=none; d=zohomail.com; s=zohoarc; b=M3OwtAx1XnQNSu8C9YFlZ/G/Hiy4Pez0IIAvsQM+4L9Pg9h/jKQRX57w6Ykd1OFKPyzSQ7pKzHrB5TZQOjXZEatbS3RRWV+K0+zAojXvW+8kKUzHTaSDHGJ0x+akkdTU8sdGYi5iphI/rwPa3bysALrTzJVEGiLGx9WotTPs5Vg= ARC-Message-Signature: i=1; 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Thu, 18 Dec 2025 23:04:46 -0800 (PST) Date: Fri, 19 Dec 2025 07:04:18 +0000 In-Reply-To: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> Mime-Version: 1.0 References: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> X-Mailer: b4 0.14.2 Message-ID: <20251219-aspeed-sgpio-v5-5-fd5593178144@google.com> Subject: [PATCH v5 5/6] hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou , "=?utf-8?q?C=C3=A9dric_Le_Goater?=" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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object_initialize_child(obj, "gpio", &s->gpio, typename); =20 + snprintf(typename, sizeof(typename), "aspeed.sgpio-%s", socname); + for (i =3D 0; i < sc->sgpio_num; i++) { + object_initialize_child(obj, "sgpio[*]", &s->sgpiom[i], typename); + } + object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); =20 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); @@ -973,6 +978,17 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); =20 + /* SGPIO */ + for (i =3D 0; i < sc->sgpio_num; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sgpiom[i]), 0, + sc->memmap[ASPEED_DEV_SGPIOM0 + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sgpiom[i]), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SGPIOM0 += i)); + } + /* RTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { return; 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Thu, 18 Dec 2025 23:04:47 -0800 (PST) Date: Fri, 19 Dec 2025 07:04:19 +0000 In-Reply-To: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> Mime-Version: 1.0 References: <20251219-aspeed-sgpio-v5-0-fd5593178144@google.com> X-Mailer: b4 0.14.2 Message-ID: <20251219-aspeed-sgpio-v5-6-fd5593178144@google.com> Subject: [PATCH v5 6/6] test/qtest: Add Unit test for Aspeed SGPIO From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou Content-Type: text/plain; charset="utf-8" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=3D_lEaQYKCmYcYFMRdKSSKPI.GSQUIQY-HIZIPRSRKRY.SVK@flex--yubinz.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1766127930930158500 Content-Transfer-Encoding: quoted-printable This commit introduces a new qtest for the Aspeed SGPIO controller The test covers the following: - Setting and clearing SGPIO output pins and verifying the pin state. - Setting and clearing SGPIO input pins and verifying the pin state. - Verifying that level-high interrupts are correctly triggered and cleare= d. Signed-off-by: Yubin Zou Reviewed-by: Kane Chen --- tests/qtest/ast2700-sgpio-test.c | 165 +++++++++++++++++++++++++++++++++++= ++++ tests/qtest/meson.build | 1 + 2 files changed, 166 insertions(+) diff --git a/tests/qtest/ast2700-sgpio-test.c b/tests/qtest/ast2700-sgpio-t= est.c new file mode 100644 index 0000000000000000000000000000000000000000..14fa4084dad3daedcf78815b05b= 1282c284f0783 --- /dev/null +++ b/tests/qtest/ast2700-sgpio-test.c @@ -0,0 +1,165 @@ +/* + * QTest testcase for the ASPEED AST2700 SGPIO Controller. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2025 Google LLC. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qobject/qdict.h" +#include "libqtest-single.h" +#include "hw/registerfields.h" +#include "hw/gpio/aspeed_sgpio.h" + +#define AST2700_SGPIO0_BASE 0x14C0C000 +#define AST2700_SGPIO1_BASE 0x14C0D000 + +static void test_output_pins(const char *machine, const uint32_t base, int= idx) +{ + QTestState *s =3D qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t offset =3D 0; + uint32_t value =3D 0; + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Odd index is output port */ + sprintf(name, "sgpio%03d", i * 2 + 1); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + offset =3D base + (R_SGPIO_0_CONTROL + i) * 4; + /* set serial output */ + qtest_writel(s, offset, 0x00000001); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), = =3D=3D, 1); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, tru= e); + + /* clear serial output */ + qtest_writel(s, offset, 0x00000000); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), = =3D=3D, 0); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, fal= se); + } + qtest_quit(s); +} + +static void test_input_pins(const char *machine, const uint32_t base, int = idx) +{ + QTestState *s =3D qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t offset =3D 0; + uint32_t value =3D 0; + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Even index is input port */ + sprintf(name, "sgpio%03d", i * 2); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + offset =3D base + (R_SGPIO_0_CONTROL + i) * 4; + /* set serial input */ + qtest_qom_set_bool(s, qom_path, name, true); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 1); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, tru= e); + + /* clear serial input */ + qtest_qom_set_bool(s, qom_path, name, false); + value =3D qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 0); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), =3D=3D, fal= se); + } + qtest_quit(s); +} + +static void test_irq_level_high(const char *machine, + const uint32_t base, int idx) +{ + QTestState *s =3D qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t ctrl_offset =3D 0; + uint32_t int_offset =3D 0; + uint32_t int_reg_idx =3D 0; + uint32_t int_bit_idx =3D 0; + uint32_t value =3D 0; + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Even index is input port */ + sprintf(name, "sgpio%03d", i * 2); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + int_reg_idx =3D i / 32; + int_bit_idx =3D i % 32; + int_offset =3D base + (R_SGPIO_INT_STATUS_0 + int_reg_idx) * 4; + ctrl_offset =3D base + (R_SGPIO_0_CONTROL + i) * 4; + + /* Enable the interrupt */ + value =3D SHARED_FIELD_DP32(value, SGPIO_INT_EN, 1); + qtest_writel(s, ctrl_offset, value); + + /* Set the interrupt type to level-high trigger */ + value =3D SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), + SGPIO_INT_TYPE, 3); + qtest_writel(s, ctrl_offset, value); + + /* Set serial input high */ + qtest_qom_set_bool(s, qom_path, name, true); + value =3D qtest_readl(s, ctrl_offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 1); + + /* Interrupt status is set */ + value =3D qtest_readl(s, int_offset); + g_assert_cmphex(extract32(value, int_bit_idx, 1), =3D=3D, 1); + + /* Clear Interrupt */ + value =3D SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), + SGPIO_INT_STATUS, 1); + qtest_writel(s, ctrl_offset, value); + value =3D qtest_readl(s, int_offset); + g_assert_cmphex(extract32(value, int_bit_idx, 1), =3D=3D, 0); + + /* Clear serial input */ + qtest_qom_set_bool(s, qom_path, name, false); + value =3D qtest_readl(s, ctrl_offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), =3D= =3D, 0); + } + qtest_quit(s); +} + +static void test_ast_2700_sgpio_input(void) +{ + test_input_pins("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_input_pins("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +static void test_ast_2700_sgpio_output(void) +{ + test_output_pins("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_output_pins("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +static void test_ast_2700_sgpio_irq(void) +{ + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_input", + test_ast_2700_sgpio_input); + qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_output", + test_ast_2700_sgpio_output); + qtest_add_func("/ast2700/sgpio/ast_2700_sgpio_irq", + test_ast_2700_sgpio_irq); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 669d07c06bdedc6be0c69acadeba989dc15ddf3f..5c80b2ed6de1f453d2483db482c= 1b0e7801ba980 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -221,6 +221,7 @@ qtests_aspeed =3D \ qtests_aspeed64 =3D \ ['ast2700-gpio-test', 'ast2700-hace-test', + 'ast2700-sgpio-test', 'ast2700-smc-test'] =20 qtests_stm32l4x5 =3D \ --=20 2.52.0.351.gbe84eed79e-goog