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Duplicate the MemoryRegionOps, using one entry for BIG and another for LITTLE endianness. Select the proper MemoryRegionOps in memory_region_init_ram_device_ptr(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- system/memory.c | 68 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 48 insertions(+), 20 deletions(-) diff --git a/system/memory.c b/system/memory.c index 8b84661ae36..5bcdeaf0bee 100644 --- a/system/memory.c +++ b/system/memory.c @@ -1361,41 +1361,69 @@ const MemoryRegionOps unassigned_mem_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static uint64_t memory_region_ram_device_read(void *opaque, - hwaddr addr, unsigned size) +static uint64_t memory_region_ram_device_read_le(void *opaque, + hwaddr addr, unsigned siz= e) { MemoryRegion *mr =3D opaque; - uint64_t data =3D ldn_he_p(mr->ram_block->host + addr, size); + uint64_t data =3D ldn_le_p(mr->ram_block->host + addr, size); =20 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, s= ize); =20 return data; } =20 -static void memory_region_ram_device_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) +static uint64_t memory_region_ram_device_read_be(void *opaque, + hwaddr addr, unsigned siz= e) +{ + MemoryRegion *mr =3D opaque; + uint64_t data =3D ldn_be_p(mr->ram_block->host + addr, size); + + trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, s= ize); + + return data; +} + +static void memory_region_ram_device_write_le(void *opaque, hwaddr addr, + uint64_t data, unsigned size) { MemoryRegion *mr =3D opaque; =20 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, = size); =20 - stn_he_p(mr->ram_block->host + addr, size, data); + stn_le_p(mr->ram_block->host + addr, size, data); } =20 -static const MemoryRegionOps ram_device_mem_ops =3D { - .read =3D memory_region_ram_device_read, - .write =3D memory_region_ram_device_write, - .endianness =3D HOST_BIG_ENDIAN ? DEVICE_BIG_ENDIAN : DEVICE_LITTLE_EN= DIAN, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - .unaligned =3D true, - }, - .impl =3D { - .min_access_size =3D 1, - .max_access_size =3D 8, - .unaligned =3D true, +static void memory_region_ram_device_write_be(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + MemoryRegion *mr =3D opaque; + + trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, = size); + + stn_be_p(mr->ram_block->host + addr, size, data); +} + +static const MemoryRegionOps ram_device_mem_ops[2] =3D { + [0 ... 1] =3D { + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D true, + }, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + .unaligned =3D true, + }, }, + + [0].endianness =3D DEVICE_LITTLE_ENDIAN, + [0].read =3D memory_region_ram_device_read_le, + [0].write =3D memory_region_ram_device_write_le, + + [1].endianness =3D DEVICE_BIG_ENDIAN, + [1].read =3D memory_region_ram_device_read_be, + [1].write =3D memory_region_ram_device_write_be, }; =20 bool memory_region_access_valid(MemoryRegion *mr, @@ -1712,7 +1740,7 @@ void memory_region_init_ram_device_ptr(MemoryRegion *= mr, mr->ram =3D true; mr->terminates =3D true; mr->ram_device =3D true; - mr->ops =3D &ram_device_mem_ops; + mr->ops =3D &ram_device_mem_ops[HOST_BIG_ENDIAN]; mr->opaque =3D mr; mr->destructor =3D memory_region_destructor_ram; =20 --=20 2.52.0 From nobody Mon Feb 9 09:01:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1766093398; cv=none; d=zohomail.com; s=zohoarc; b=LRTe8wKBKjSv+WiRIl7Y+78rgxiA6UwnZcQf+cyHtGWfL6/QeHu/nyE1EnI6HiH2UwLriEpSA+NfYdE65RoMKYGdEt1RKABxTAneDpLMrwitWjrZVOAvq23fw2pkx8mFUCBrVL+tCSlOhPMF8SVXr6XDBwIUNTzWGzuzr16Tr7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1766093398; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+gtJF0mQnqytiehBxnmWHOQY5+iP99pLlE/lksFMG9Q=; b=QTyxQ5qHxEYmbbNpcxP9UPaIPY0gR7CXrrra8SVu6UXXbBsPNWQk5kPkyNrRf6uuIplA89G05u/WxpArikbITZWS30D1n3wn5n0c5Gtk20furYNesCObIK7jR7UVzEYg5b1lMix7+M7sY1xlLWiTkr/smBRb+rDMGUH954g5XYU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1766093398578276.4236389801879; Thu, 18 Dec 2025 13:29:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vWLYD-0001Gt-JE; Thu, 18 Dec 2025 16:28:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vWLY7-0001Eo-DM for qemu-devel@nongnu.org; Thu, 18 Dec 2025 16:28:39 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vWLY5-0007G1-4X for qemu-devel@nongnu.org; Thu, 18 Dec 2025 16:28:38 -0500 Received: by mail-wm1-x344.google.com with SMTP id 5b1f17b1804b1-477770019e4so9220835e9.3 for ; Thu, 18 Dec 2025 13:28:36 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Use the -m suffix to differentiate with others. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- docs/devel/loads-stores.rst | 10 ++++--- include/exec/memory_ldst_cached.h.inc | 30 ++++++++++++++++++++ include/system/memory_ldst_endian.h.inc | 4 +++ include/system/memory_ldst_phys_endian.h.inc | 10 +++++++ 4 files changed, 50 insertions(+), 4 deletions(-) diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst index c906c6509ee..9b8ee4a5d34 100644 --- a/docs/devel/loads-stores.rst +++ b/docs/devel/loads-stores.rst @@ -375,6 +375,7 @@ succeeded using a MemTxResult return code. - ``w`` : 16 bits - ``l`` : 32 bits - ``q`` : 64 bits + - ``m`` : MO_SIZE =20 ``endian`` - ``le`` : little endian @@ -384,8 +385,8 @@ The ``_{endian}`` suffix is omitted for byte accesses. =20 Regexes for git grep: - ``\`` - - ``\`` - - ``\`` + - ``\`` + - ``\`` =20 ``address_space_write_rom`` ~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -431,6 +432,7 @@ device doing the access has no way to report such an er= ror. - ``w`` : 16 bits - ``l`` : 32 bits - ``q`` : 64 bits + - ``m`` : MO_SIZE =20 ``endian`` - ``le`` : little endian @@ -439,8 +441,8 @@ device doing the access has no way to report such an er= ror. The ``_{endian}_`` infix is omitted for byte accesses. =20 Regexes for git grep: - - ``\`` - - ``\`` + - ``\`` + - ``\`` =20 ``cpu_physical_memory_*`` ~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/include/exec/memory_ldst_cached.h.inc b/include/exec/memory_ld= st_cached.h.inc index d7834f852c4..21f89fe09fa 100644 --- a/include/exec/memory_ldst_cached.h.inc +++ b/include/exec/memory_ldst_cached.h.inc @@ -24,6 +24,21 @@ #define LD_P(size) \ glue(glue(ld, size), glue(ENDIANNESS, _p)) =20 +static inline uint64_t ADDRESS_SPACE_LD_CACHED(m)(MemoryRegionCache *cache, + MemOp mop, hwaddr addr, + MemTxAttrs attrs, + MemTxResult *result) +{ + const unsigned size =3D memop_size(mop); + assert(addr < cache->len && size <=3D cache->len - addr); + fuzz_dma_read_cb(cache->xlat + addr, size, cache->mrs.mr); + if (likely(cache->ptr)) { + return LD_P(n)(cache->ptr + addr, size); + } else { + return ADDRESS_SPACE_LD_CACHED_SLOW(m)(cache, mop, addr, attrs, re= sult); + } +} + static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cach= e, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { @@ -71,6 +86,21 @@ static inline uint64_t ADDRESS_SPACE_LD_CACHED(q)(Memory= RegionCache *cache, #define ST_P(size) \ glue(glue(st, size), glue(ENDIANNESS, _p)) =20 +static inline void ADDRESS_SPACE_ST_CACHED(m)(MemoryRegionCache *cache, + MemOp mop, + hwaddr addr, uint64_t val, + MemTxAttrs attrs, + MemTxResult *result) +{ + const unsigned size =3D memop_size(mop); + assert(addr < cache->len && size <=3D cache->len - addr); + if (likely(cache->ptr)) { + ST_P(n)(cache->ptr + addr, val, size); + } else { + ADDRESS_SPACE_ST_CACHED_SLOW(m)(cache, mop, addr, val, attrs, resu= lt); + } +} + static inline void ADDRESS_SPACE_ST_CACHED(w)(MemoryRegionCache *cache, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result) { diff --git a/include/system/memory_ldst_endian.h.inc b/include/system/memor= y_ldst_endian.h.inc index ec86e42afbc..9455b973663 100644 --- a/include/system/memory_ldst_endian.h.inc +++ b/include/system/memory_ldst_endian.h.inc @@ -20,12 +20,16 @@ uint32_t ADDRESS_SPACE_LD(l)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); uint64_t ADDRESS_SPACE_LD(q)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); +uint64_t ADDRESS_SPACE_LD(m)(ARG1_DECL, MemOp mop, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); void ADDRESS_SPACE_ST(w)(ARG1_DECL, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); void ADDRESS_SPACE_ST(l)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); void ADDRESS_SPACE_ST(q)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); +void ADDRESS_SPACE_ST(m)(ARG1_DECL, MemOp mop, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result); =20 #undef ADDRESS_SPACE_LD #undef ADDRESS_SPACE_ST diff --git a/include/system/memory_ldst_phys_endian.h.inc b/include/system/= memory_ldst_phys_endian.h.inc index 9603d886867..659f38f7112 100644 --- a/include/system/memory_ldst_phys_endian.h.inc +++ b/include/system/memory_ldst_phys_endian.h.inc @@ -34,6 +34,11 @@ static inline uint64_t LD_PHYS(q)(ARG1_DECL, hwaddr addr) return ADDRESS_SPACE_LD(q)(ARG1, addr, MEMTXATTRS_UNSPECIFIED, NULL); } =20 +static inline uint32_t LD_PHYS(m)(ARG1_DECL, MemOp op, hwaddr addr) +{ + return ADDRESS_SPACE_LD(m)(ARG1, op, addr, MEMTXATTRS_UNSPECIFIED, NUL= L); +} + static inline void ST_PHYS(w)(ARG1_DECL, hwaddr addr, uint16_t val) { ADDRESS_SPACE_ST(w)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); @@ -49,6 +54,11 @@ static inline void ST_PHYS(q)(ARG1_DECL, hwaddr addr, ui= nt64_t val) ADDRESS_SPACE_ST(q)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } =20 +static inline void ST_PHYS(m)(ARG1_DECL, MemOp op, hwaddr addr, uint64_t v= al) +{ + ADDRESS_SPACE_ST(m)(ARG1, op, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); +} + #undef LD_PHYS #undef ST_PHYS #undef ADDRESS_SPACE_LD --=20 2.52.0 From nobody Mon Feb 9 09:01:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1766093372; cv=none; d=zohomail.com; s=zohoarc; b=GEkkWhkCJ0GEQDVMMS2u0u7mbkbJNtzeeps+BDyl+2ZIQ83HIgW0Dc/qzJA/Fk3fYfF6Juj35SfWVtsnfiATSEiG2c4HyFctI8VE2Dm4T1mABtDsg9JzmIVenl6NgpLk95s+4VSBo7mJlJwfdkwkVg8zv65WZJOd6YK/by1V4s8= ARC-Message-Signature: i=1; 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Set it to all our system emulation targets, taking care to not poison it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- configs/targets/aarch64-softmmu.mak | 1 + configs/targets/alpha-softmmu.mak | 1 + configs/targets/arm-softmmu.mak | 1 + configs/targets/avr-softmmu.mak | 1 + configs/targets/hppa-softmmu.mak | 1 + configs/targets/i386-softmmu.mak | 1 + configs/targets/loongarch64-softmmu.mak | 1 + configs/targets/m68k-softmmu.mak | 1 + configs/targets/microblaze-softmmu.mak | 1 + configs/targets/microblazeel-softmmu.mak | 1 + configs/targets/mips-softmmu.mak | 1 + configs/targets/mips64-softmmu.mak | 1 + configs/targets/mips64el-softmmu.mak | 1 + configs/targets/mipsel-softmmu.mak | 1 + configs/targets/or1k-softmmu.mak | 1 + configs/targets/ppc-softmmu.mak | 1 + configs/targets/ppc64-softmmu.mak | 1 + configs/targets/riscv32-softmmu.mak | 1 + configs/targets/riscv64-softmmu.mak | 1 + configs/targets/rx-softmmu.mak | 1 + configs/targets/s390x-softmmu.mak | 1 + configs/targets/sh4-softmmu.mak | 1 + configs/targets/sh4eb-softmmu.mak | 1 + configs/targets/sparc-softmmu.mak | 1 + configs/targets/sparc64-softmmu.mak | 1 + configs/targets/tricore-softmmu.mak | 1 + configs/targets/x86_64-softmmu.mak | 1 + configs/targets/xtensa-softmmu.mak | 1 + configs/targets/xtensaeb-softmmu.mak | 1 + scripts/make-config-poison.sh | 1 + 30 files changed, 30 insertions(+) diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-= softmmu.mak index d14bcfc4900..5a9e8a32374 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -4,4 +4,5 @@ TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sy= sregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-prof= ile-mve.xml gdb-xml/aarch64-pauth.xml gdb-xml/aarch64-sme2.xml # needed by boot.c TARGET_NEED_FDT=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-soft= mmu.mak index e31f059a52d..05c696ead2d 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Dalpha +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D64 TARGET_XML_FILES=3D gdb-xml/alpha-core.xml diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.= mak index 6a5a8eda949..b8466614fa9 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -2,4 +2,5 @@ TARGET_ARCH=3Darm TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml gdb-xml/arm-m-profile-mve.xml # needed by boot.c TARGET_NEED_FDT=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/avr-softmmu.mak b/configs/targets/avr-softmmu.= mak index b6157fc465d..1aba1ccf13b 100644 --- a/configs/targets/avr-softmmu.mak +++ b/configs/targets/avr-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Davr TARGET_XML_FILES=3D gdb-xml/avr-cpu.xml +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmm= u.mak index ea331107a08..290eadd2939 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Dhppa TARGET_BIG_ENDIAN=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmm= u.mak index e9d89e8ab41..3dc1e9e8eab 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -2,4 +2,5 @@ TARGET_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy TARGET_XML_FILES=3D gdb-xml/i386-32bit.xml +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loon= garch64-softmmu.mak index fc44c54233d..bb6051835b2 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -4,4 +4,5 @@ TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.= xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-l= asx.xml # all boards require libfdt TARGET_NEED_FDT=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/m68k-softmmu.mak b/configs/targets/m68k-softmm= u.mak index bacc52e96a9..33649a00132 100644 --- a/configs/targets/m68k-softmmu.mak +++ b/configs/targets/m68k-softmmu.mak @@ -1,4 +1,5 @@ TARGET_ARCH=3Dm68k TARGET_BIG_ENDIAN=3Dy TARGET_XML_FILES=3D gdb-xml/cf-core.xml gdb-xml/cf-fp.xml gdb-xml/m68k-cor= e.xml gdb-xml/m68k-fp.xml +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/micro= blaze-softmmu.mak index bab7b498c24..20756f3c6cd 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -3,4 +3,5 @@ TARGET_BIG_ENDIAN=3Dy # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3Dgdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-pr= otect.xml +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/mic= roblazeel-softmmu.mak index 8aee7ebc5cf..70cdbcb8aec 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -2,4 +2,5 @@ TARGET_ARCH=3Dmicroblaze # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3Dgdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-pr= otect.xml +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmm= u.mak index c9588066b8d..4ef1f6892cd 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Dmips TARGET_BIG_ENDIAN=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/mips64-softmmu.mak b/configs/targets/mips64-so= ftmmu.mak index 7202655fcac..acd60bd9713 100644 --- a/configs/targets/mips64-softmmu.mak +++ b/configs/targets/mips64-softmmu.mak @@ -1,4 +1,5 @@ TARGET_ARCH=3Dmips64 TARGET_BASE_ARCH=3Dmips TARGET_BIG_ENDIAN=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/mips64el-softmmu.mak b/configs/targets/mips64e= l-softmmu.mak index 3ebeadb29ea..759c47ddf7e 100644 --- a/configs/targets/mips64el-softmmu.mak +++ b/configs/targets/mips64el-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Dmips64 TARGET_BASE_ARCH=3Dmips +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-so= ftmmu.mak index 90e09bdc3e5..6b5aad7fe84 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=3Dmips +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmm= u.mak index 0e47d9878b0..f4621b8fe08 100644 --- a/configs/targets/or1k-softmmu.mak +++ b/configs/targets/or1k-softmmu.mak @@ -2,4 +2,5 @@ TARGET_ARCH=3Dopenrisc TARGET_BIG_ENDIAN=3Dy # needed by boot.c and all boards TARGET_NEED_FDT=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/ppc-softmmu.mak b/configs/targets/ppc-softmmu.= mak index 9bfa7df6c36..e7c1543727a 100644 --- a/configs/targets/ppc-softmmu.mak +++ b/configs/targets/ppc-softmmu.mak @@ -1,5 +1,6 @@ TARGET_ARCH=3Dppc TARGET_BIG_ENDIAN=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/power-core.xml gdb-xml/power-fpu.xml gdb-xml/p= ower-altivec.xml gdb-xml/power-spe.xml TARGET_LONG_BITS=3D32 diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-soft= mmu.mak index 74572864b36..bb6b769836e 100644 --- a/configs/targets/ppc64-softmmu.mak +++ b/configs/targets/ppc64-softmmu.mak @@ -1,6 +1,7 @@ TARGET_ARCH=3Dppc64 TARGET_BASE_ARCH=3Dppc TARGET_BIG_ENDIAN=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml= /power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml # all boards require libfdt diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-= softmmu.mak index db55275b868..1a6e6f2a53a 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -3,4 +3,5 @@ TARGET_BASE_ARCH=3Driscv TARGET_XML_FILES=3D gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-= softmmu.mak index 2bdd4a62cd2..f7c09be186b 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -4,4 +4,5 @@ TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv= -32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/rx-softmmu.mak b/configs/targets/rx-softmmu.mak index 1c250a6450d..0c3932e73c4 100644 --- a/configs/targets/rx-softmmu.mak +++ b/configs/targets/rx-softmmu.mak @@ -2,4 +2,5 @@ TARGET_ARCH=3Drx TARGET_XML_FILES=3D gdb-xml/rx-core.xml # all boards require libfdt TARGET_NEED_FDT=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-soft= mmu.mak index 76dd5de6584..d7d165c5781 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -2,4 +2,5 @@ TARGET_ARCH=3Ds390x TARGET_BIG_ENDIAN=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/= s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml = gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/sh4-softmmu.mak b/configs/targets/sh4-softmmu.= mak index 787d349b501..fd8ec407139 100644 --- a/configs/targets/sh4-softmmu.mak +++ b/configs/targets/sh4-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=3Dsh4 +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/sh4eb-softmmu.mak b/configs/targets/sh4eb-soft= mmu.mak index cdea2c61c58..7a1dfdbe211 100644 --- a/configs/targets/sh4eb-softmmu.mak +++ b/configs/targets/sh4eb-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Dsh4 TARGET_BIG_ENDIAN=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-soft= mmu.mak index 57801faf1fc..7254e5dd1b6 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-= softmmu.mak index d9d51d21e59..7b5d475c85d 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,5 +1,6 @@ TARGET_ARCH=3Dsparc64 TARGET_BASE_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_XML_FILES=3Dgdb-xml/sparc64-core.xml TARGET_LONG_BITS=3D64 diff --git a/configs/targets/tricore-softmmu.mak b/configs/targets/tricore-= softmmu.mak index 781ce49a62f..63e040ccc2b 100644 --- a/configs/targets/tricore-softmmu.mak +++ b/configs/targets/tricore-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=3Dtricore +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index 5619b2bc686..263ec88b7d7 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -3,4 +3,5 @@ TARGET_BASE_ARCH=3Di386 TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy TARGET_XML_FILES=3D gdb-xml/i386-64bit.xml +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-so= ftmmu.mak index 2a9797338a6..1ce74cd8e5e 100644 --- a/configs/targets/xtensa-softmmu.mak +++ b/configs/targets/xtensa-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=3Dxtensa +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/xtensaeb-softmmu.mak b/configs/targets/xtensae= b-softmmu.mak index 5204729af8b..9be73447c88 100644 --- a/configs/targets/xtensaeb-softmmu.mak +++ b/configs/targets/xtensaeb-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Dxtensa TARGET_BIG_ENDIAN=3Dy +TARGET_USE_LEGACY_NATIVE_ENDIAN_API=3Dy TARGET_LONG_BITS=3D32 diff --git a/scripts/make-config-poison.sh b/scripts/make-config-poison.sh index 2b36907e239..543119c074e 100755 --- a/scripts/make-config-poison.sh +++ b/scripts/make-config-poison.sh @@ -10,6 +10,7 @@ exec sed -n \ -e' /CONFIG_TCG/d' \ -e '/CONFIG_USER_ONLY/d' \ -e '/CONFIG_SOFTMMU/d' \ + -e '/TARGET_USE_LEGACY_NATIVE_ENDIAN_API/d' \ -e '/^#define / {' \ -e 's///' \ -e 's/ .*//' \ --=20 2.52.0 From nobody Mon Feb 9 09:01:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as 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Once a target gets cleaned we'll unset the definition in the target config, then the target won't be able to use the legacy API anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/accel/tcg/cpu-ldst.h | 2 ++ include/exec/translator.h | 2 +- include/qemu/bswap.h | 5 +++++ include/system/memory_cached.h | 2 ++ system/memory-internal.h | 2 ++ include/exec/memory_ldst.h.inc | 2 ++ include/exec/memory_ldst_phys.h.inc | 2 ++ system/memory_ldst.c.inc | 2 ++ 8 files changed, 18 insertions(+), 1 deletion(-) diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h index 0de7f5eaa6b..91b618c2f41 100644 --- a/include/accel/tcg/cpu-ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -428,6 +428,7 @@ cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64= _t val) cpu_stq_le_data_ra(env, addr, val, 0); } =20 +#ifdef TARGET_USE_LEGACY_NATIVE_ENDIAN_API #if TARGET_BIG_ENDIAN # define cpu_lduw_data cpu_lduw_be_data # define cpu_ldsw_data cpu_ldsw_be_data @@ -501,5 +502,6 @@ static inline uint64_t cpu_ldq_code(CPUArchState *env, = abi_ptr addr) MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true)); return cpu_ldq_code_mmu(env, addr, oi, 0); } +#endif /* TARGET_USE_LEGACY_NATIVE_ENDIAN_API */ =20 #endif /* ACCEL_TCG_CPU_LDST_H */ diff --git a/include/exec/translator.h b/include/exec/translator.h index 3c326555696..30e6596c5d7 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -188,7 +188,7 @@ uint32_t translator_ldl_end(CPUArchState *env, DisasCon= textBase *db, uint64_t translator_ldq_end(CPUArchState *env, DisasContextBase *db, vaddr pc, MemOp endian); =20 -#ifdef COMPILING_PER_TARGET +#if defined(TARGET_USE_LEGACY_NATIVE_ENDIAN_API) && defined(COMPILING_PER_= TARGET) static inline uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc) { diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index 65a1b3634f4..8b0070d26a6 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -412,7 +412,9 @@ static inline void stq_be_p(void *ptr, uint64_t v) } \ } =20 +#ifdef TARGET_USE_LEGACY_NATIVE_ENDIAN_API DO_STN_LDN_P(he) +#endif DO_STN_LDN_P(le) DO_STN_LDN_P(be) =20 @@ -423,6 +425,7 @@ DO_STN_LDN_P(be) #undef le_bswaps #undef be_bswaps =20 +#ifdef TARGET_USE_LEGACY_NATIVE_ENDIAN_API =20 /* Return ld{word}_{le,be}_p following target endianness. */ #define LOAD_IMPL(word, args...) \ @@ -494,4 +497,6 @@ static inline void stn_p(void *ptr, int sz, uint64_t v) =20 #undef STORE_IMPL =20 +#endif /* TARGET_USE_LEGACY_NATIVE_ENDIAN_API */ + #endif /* BSWAP_H */ diff --git a/include/system/memory_cached.h b/include/system/memory_cached.h index 1a07774b6ad..356023f5729 100644 --- a/include/system/memory_cached.h +++ b/include/system/memory_cached.h @@ -77,8 +77,10 @@ static inline void address_space_stb_cached(MemoryRegion= Cache *cache, } } =20 +#ifdef TARGET_USE_LEGACY_NATIVE_ENDIAN_API #define ENDIANNESS #include "exec/memory_ldst_cached.h.inc" +#endif =20 #define ENDIANNESS _le #include "exec/memory_ldst_cached.h.inc" diff --git a/system/memory-internal.h b/system/memory-internal.h index 46f758fa7e4..d781d437642 100644 --- a/system/memory-internal.h +++ b/system/memory-internal.h @@ -41,9 +41,11 @@ void mtree_print_dispatch(struct AddressSpaceDispatch *d, /* returns true if end is big endian. */ static inline bool devend_big_endian(enum device_endian end) { +#ifdef TARGET_USE_LEGACY_NATIVE_ENDIAN_API if (end =3D=3D DEVICE_NATIVE_ENDIAN) { return target_big_endian(); } +#endif return end =3D=3D DEVICE_BIG_ENDIAN; } =20 diff --git a/include/exec/memory_ldst.h.inc b/include/exec/memory_ldst.h.inc index dd1fb482eac..8ff6e563310 100644 --- a/include/exec/memory_ldst.h.inc +++ b/include/exec/memory_ldst.h.inc @@ -25,8 +25,10 @@ uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, void glue(address_space_stb, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result); =20 +#ifdef TARGET_USE_LEGACY_NATIVE_ENDIAN_API #define ENDIANNESS #include "system/memory_ldst_endian.h.inc" +#endif /* TARGET_USE_LEGACY_NATIVE_ENDIAN_API */ =20 #define ENDIANNESS _le #include "system/memory_ldst_endian.h.inc" diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst= _phys.h.inc index f4c91dc7a91..e0da6d19a5b 100644 --- a/include/exec/memory_ldst_phys.h.inc +++ b/include/exec/memory_ldst_phys.h.inc @@ -31,8 +31,10 @@ static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwa= ddr addr, uint8_t val) MEMTXATTRS_UNSPECIFIED, NULL); } =20 +#ifdef TARGET_USE_LEGACY_NATIVE_ENDIAN_API #define ENDIANNESS #include "system/memory_ldst_phys_endian.h.inc" +#endif /* TARGET_USE_LEGACY_NATIVE_ENDIAN_API */ =20 #define ENDIANNESS _le #include "system/memory_ldst_phys_endian.h.inc" diff --git a/system/memory_ldst.c.inc b/system/memory_ldst.c.inc index 5a979ea6ac3..2f707e5f5b4 100644 --- a/system/memory_ldst.c.inc +++ b/system/memory_ldst.c.inc @@ -181,9 +181,11 @@ void glue(address_space_stq_internal, SUFFIX)(ARG1_DEC= L, MemOp mop, attrs, result); } =20 +#ifdef TARGET_USE_LEGACY_NATIVE_ENDIAN_API #define ENDIANNESS #define MO_ENDIAN (target_big_endian() ? MO_BE : MO_LE) #include "memory_ldst_endian.c.inc" +#endif /* TARGET_USE_LEGACY_NATIVE_ENDIAN_API */ =20 #define ENDIANNESS _le #define MO_ENDIAN MO_LE --=20 2.52.0