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Date: Thu, 18 Dec 2025 21:31:18 +0300 Message-ID: <20251218183122.408690-4-sergeev0xef@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251218183122.408690-1-sergeev0xef@gmail.com> References: <20251218183122.408690-1-sergeev0xef@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=sergeev0xef@gmail.com; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 18 Dec 2025 13:32:44 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1766082877785158500 Content-Type: text/plain; charset="utf-8" SBI events are not a part of RISC-V specification and should not be hardcoded right in QEMU. It's up to vendor to implement them. Also, we can get rid of event->ctr mapping, as it is used only for SBI event handling. Signed-off-by: Aleksandr Sergeev Reviewed-by: Alexei Filippov --- target/riscv/cpu.h | 15 --- target/riscv/cpu_helper.c | 23 ---- target/riscv/csr.c | 18 +-- target/riscv/pmu.c | 240 ++------------------------------------ target/riscv/pmu.h | 7 -- 5 files changed, 16 insertions(+), 287 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 36e7f10037..8ab5fa0afb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -550,8 +550,6 @@ struct ArchCPU { QEMUTimer *pmu_timer; /* A bitmask of Available programmable counters */ uint32_t pmu_avail_ctrs; - /* Mapping of events to counters */ - GHashTable *pmu_event_ctr_map; const GPtrArray *decoders; }; =20 @@ -925,19 +923,6 @@ enum { CSR_TABLE_SIZE =3D 0x1000 }; =20 -/* - * The event id are encoded based on the encoding specified in the - * SBI specification v0.3 - */ - -enum riscv_pmu_event_idx { - RISCV_PMU_EVENT_HW_CPU_CYCLES =3D 0x01, - RISCV_PMU_EVENT_HW_INSTRUCTIONS =3D 0x02, - RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS =3D 0x10019, - RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS =3D 0x1001B, - RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, -}; - /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c4fb68b5de..b3780cf8a8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1736,28 +1736,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vad= dr addr, cpu_loop_exit_restore(cs, retaddr); } =20 - -static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) -{ - enum riscv_pmu_event_idx pmu_event_type; - - switch (access_type) { - case MMU_INST_FETCH: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; - break; - case MMU_DATA_LOAD: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; - break; - case MMU_DATA_STORE: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; - break; - default: - return; - } - - riscv_pmu_incr_ctr(cpu, pmu_event_type); -} - bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -1781,7 +1759,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - pmu_tlb_fill_incr_ctr(cpu, access_type); if (two_stage_lookup) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 81475ec9a3..fb052725fe 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1188,8 +1188,6 @@ static RISCVException write_mhpmevent(CPURISCVState *= env, int csrno, env->mhpmevent_val[ctr_idx] =3D mhpmevt_val; } =20 - riscv_pmu_update_event_map(env, mhpmevt_val, ctr_idx); - return RISCV_EXCP_NONE; } =20 @@ -1223,8 +1221,6 @@ static RISCVException write_mhpmeventh(CPURISCVState = *env, int csrno, mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); env->mhpmeventh_val[ctr_idx] =3D mhpmevth_val; =20 - riscv_pmu_update_event_map(env, mhpmevt_val, ctr_idx); - return RISCV_EXCP_NONE; } =20 @@ -1232,7 +1228,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_= val(CPURISCVState *env, int counter_idx, bool upper_half) { - int inst =3D riscv_pmu_ctr_monitor_instructions(env, counter_idx); + int inst =3D (counter_idx =3D=3D HPM_MINSTRET_IDX); uint64_t *counter_arr_virt =3D env->pmu_fixed_ctrs[inst].counter_virt; uint64_t *counter_arr =3D env->pmu_fixed_ctrs[inst].counter; target_ulong result =3D 0; @@ -1303,8 +1299,7 @@ static RISCVException riscv_pmu_write_ctr(CPURISCVSta= te *env, target_ulong val, =20 counter->mhpmcounter_val =3D val; if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && - (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { + (ctr_idx =3D=3D HPM_MCYCLE_IDX || ctr_idx =3D=3D HPM_MINSTRET_IDX)= ) { counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters_val= (env, ctr_idx, f= alse); if (ctr_idx > 2) { @@ -1332,8 +1327,7 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCVSt= ate *env, target_ulong val, counter->mhpmcounterh_val =3D val; mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && - (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { + (ctr_idx =3D=3D HPM_MCYCLE_IDX || ctr_idx =3D=3D HPM_MINSTRET_IDX)= ) { counter->mhpmcounterh_prev =3D riscv_pmu_ctr_get_fixed_counters_va= l(env, ctr_idx, = true); if (ctr_idx > 2) { @@ -1384,8 +1378,7 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env,= target_ulong *val, * The kernel computes the perf delta by subtracting the current value= from * the value it initialized previously (ctr_val). */ - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + if (ctr_idx =3D=3D HPM_MCYCLE_IDX || ctr_idx =3D=3D HPM_MINSTRET_IDX) { *val =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, upper_= half) - ctr_prev + ctr_val; } else { @@ -2955,8 +2948,7 @@ static RISCVException write_mcountinhibit(CPURISCVSta= te *env, int csrno, /* Check if any other counter is also monitoring cycles/instructions */ for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { if (!(updated_ctrs & BIT(cidx)) || - (!riscv_pmu_ctr_monitor_cycles(env, cidx) && - !riscv_pmu_ctr_monitor_instructions(env, cidx))) { + (cidx !=3D HPM_MCYCLE_IDX && cidx !=3D HPM_MINSTRET_IDX)) { continue; } =20 diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index b983eadd83..c503fffde1 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -101,82 +101,6 @@ static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, u= int32_t ctr_idx) } } =20 -static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) -{ - CPURISCVState *env =3D &cpu->env; - target_ulong max_val =3D UINT32_MAX; - PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - bool virt_on =3D env->virt_enabled; - - /* Privilege mode filtering */ - if ((env->priv =3D=3D PRV_M && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || - (env->priv =3D=3D PRV_S && virt_on && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || - (env->priv =3D=3D PRV_U && virt_on && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) || - (env->priv =3D=3D PRV_S && !virt_on && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) || - (env->priv =3D=3D PRV_U && !virt_on && - (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) { - return 0; - } - - /* Handle the overflow scenario */ - if (counter->mhpmcounter_val =3D=3D max_val) { - if (counter->mhpmcounterh_val =3D=3D max_val) { - counter->mhpmcounter_val =3D 0; - counter->mhpmcounterh_val =3D 0; - /* Generate interrupt only if OF bit is clear */ - if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { - env->mhpmeventh_val[ctr_idx] |=3D MHPMEVENTH_BIT_OF; - riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); - } - } else { - counter->mhpmcounterh_val++; - } - } else { - counter->mhpmcounter_val++; - } - - return 0; -} - -static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) -{ - CPURISCVState *env =3D &cpu->env; - PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - uint64_t max_val =3D UINT64_MAX; - bool virt_on =3D env->virt_enabled; - - /* Privilege mode filtering */ - if ((env->priv =3D=3D PRV_M && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || - (env->priv =3D=3D PRV_S && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || - (env->priv =3D=3D PRV_U && virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || - (env->priv =3D=3D PRV_S && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || - (env->priv =3D=3D PRV_U && !virt_on && - (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { - return 0; - } - - /* Handle the overflow scenario */ - if (counter->mhpmcounter_val =3D=3D max_val) { - counter->mhpmcounter_val =3D 0; - /* Generate interrupt only if OF bit is clear */ - if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { - env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; - riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); - } - } else { - counter->mhpmcounter_val++; - } - return 0; -} - /* * Information needed to update counters: * new_priv, new_virt: To correctly save starting snapshot for the newly @@ -272,97 +196,6 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, t= arget_ulong newpriv, riscv_pmu_icount_update_priv(env, newpriv, new_virt); } =20 -int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) -{ - uint32_t ctr_idx; - int ret; - CPURISCVState *env =3D &cpu->env; - gpointer value; - - if (!cpu->cfg.pmu_mask) { - return 0; - } - value =3D g_hash_table_lookup(cpu->pmu_event_ctr_map, - GUINT_TO_POINTER(event_idx)); - if (!value) { - return -1; - } - - ctr_idx =3D GPOINTER_TO_UINT(value); - if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { - return -1; - } - - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - ret =3D riscv_pmu_incr_ctr_rv32(cpu, ctr_idx); - } else { - ret =3D riscv_pmu_incr_ctr_rv64(cpu, ctr_idx); - } - - return ret; -} - -bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, - uint32_t target_ctr) -{ - RISCVCPU *cpu; - uint32_t event_idx; - uint32_t ctr_idx; - - /* Fixed instret counter */ - if (target_ctr =3D=3D 2) { - return true; - } - - cpu =3D env_archcpu(env); - if (!cpu->pmu_event_ctr_map) { - return false; - } - - event_idx =3D RISCV_PMU_EVENT_HW_INSTRUCTIONS; - ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, - GUINT_TO_POINTER(event_idx))); - if (!ctr_idx) { - return false; - } - - return target_ctr =3D=3D ctr_idx ? true : false; -} - -bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) -{ - RISCVCPU *cpu; - uint32_t event_idx; - uint32_t ctr_idx; - - /* Fixed mcycle counter */ - if (target_ctr =3D=3D 0) { - return true; - } - - cpu =3D env_archcpu(env); - if (!cpu->pmu_event_ctr_map) { - return false; - } - - event_idx =3D RISCV_PMU_EVENT_HW_CPU_CYCLES; - ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, - GUINT_TO_POINTER(event_idx))); - - /* Counter zero is not used for event_ctr_map */ - if (!ctr_idx) { - return false; - } - - return (target_ctr =3D=3D ctr_idx) ? true : false; -} - -static gboolean pmu_remove_event_map(gpointer key, gpointer value, - gpointer udata) -{ - return (GPOINTER_TO_UINT(value) =3D=3D GPOINTER_TO_UINT(udata)) ? true= : false; -} - static int64_t pmu_icount_ticks_to_ns(int64_t value) { int64_t ret =3D 0; @@ -376,50 +209,6 @@ static int64_t pmu_icount_ticks_to_ns(int64_t value) return ret; } =20 -int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, - uint32_t ctr_idx) -{ - uint32_t event_idx; - RISCVCPU *cpu =3D env_archcpu(env); - - if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map)= { - return -1; - } - - /* - * Expected mhpmevent value is zero for reset case. Remove the current - * mapping. - */ - if (!(value & MHPMEVENT_IDX_MASK)) { - g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, - pmu_remove_event_map, - GUINT_TO_POINTER(ctr_idx)); - return 0; - } - - event_idx =3D value & MHPMEVENT_IDX_MASK; - if (g_hash_table_lookup(cpu->pmu_event_ctr_map, - GUINT_TO_POINTER(event_idx))) { - return 0; - } - - switch (event_idx) { - case RISCV_PMU_EVENT_HW_CPU_CYCLES: - case RISCV_PMU_EVENT_HW_INSTRUCTIONS: - case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS: - case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: - case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: - break; - default: - /* We don't support any raw events right now */ - return -1; - } - g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx= ), - GUINT_TO_POINTER(ctr_idx)); - - return 0; -} - static bool pmu_hpmevent_is_of_set(CPURISCVState *env, uint32_t ctr_idx) { target_ulong mhpmevent_val; @@ -457,23 +246,19 @@ static bool pmu_hpmevent_set_of_if_clear(CPURISCVStat= e *env, uint32_t ctr_idx) return false; } =20 -static void pmu_timer_trigger_irq(RISCVCPU *cpu, - enum riscv_pmu_event_idx evt_idx) +static void pmu_timer_trigger_irq(RISCVCPU *cpu, uint32_t ctr_idx) { - uint32_t ctr_idx; CPURISCVState *env =3D &cpu->env; PMUCTRState *counter; int64_t irq_trigger_at; uint64_t curr_ctr_val, curr_ctrh_val; uint64_t ctr_val; =20 - if (evt_idx !=3D RISCV_PMU_EVENT_HW_CPU_CYCLES && - evt_idx !=3D RISCV_PMU_EVENT_HW_INSTRUCTIONS) { + if (ctr_idx !=3D HPM_MINSTRET_IDX && + ctr_idx !=3D HPM_MCYCLE_IDX) { return; } =20 - ctr_idx =3D GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_ma= p, - GUINT_TO_POINTER(evt_idx))); if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { return; } @@ -523,10 +308,13 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, void riscv_pmu_timer_cb(void *priv) { RISCVCPU *cpu =3D priv; + uint32_t ctr_idx; =20 - /* Timer event was triggered only for these events */ - pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); - pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); + for (ctr_idx =3D 0; ctr_idx < RV_MAX_MHPMCOUNTERS; ctr_idx++) { + if (riscv_pmu_counter_valid(cpu, ctr_idx)) { + pmu_timer_trigger_irq(cpu, ctr_idx); + } + } } =20 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr= _idx) @@ -557,8 +345,8 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t = value, uint32_t ctr_idx) overflow_left =3D overflow_delta - INT64_MAX; } =20 - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { + if (ctr_idx =3D=3D HPM_MCYCLE_IDX || + ctr_idx =3D=3D HPM_MINSTRET_IDX) { overflow_ns =3D pmu_icount_ticks_to_ns((int64_t)overflow_delta); overflow_left =3D pmu_icount_ticks_to_ns(overflow_left) ; } else { @@ -592,12 +380,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) return; } =20 - cpu->pmu_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direct_eq= ual); - if (!cpu->pmu_event_ctr_map) { - error_setg(errp, "Unable to allocate PMU event hash table"); - return; - } - cpu->pmu_avail_ctrs =3D cpu->cfg.pmu_mask; } =20 diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 8f019bea9f..97b167d8f2 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -22,15 +22,8 @@ #include "cpu.h" #include "qapi/error.h" =20 -bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, - uint32_t target_ctr); -bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, - uint32_t target_ctr); void riscv_pmu_timer_cb(void *priv); void riscv_pmu_init(RISCVCPU *cpu, Error **errp); -int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, - uint32_t ctr_idx); -int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); --=20 2.51.0