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Date: Thu, 18 Dec 2025 21:31:16 +0300 Message-ID: <20251218183122.408690-2-sergeev0xef@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251218183122.408690-1-sergeev0xef@gmail.com> References: <20251218183122.408690-1-sergeev0xef@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=sergeev0xef@gmail.com; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 18 Dec 2025 13:32:34 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1766082817500158500 Content-Type: text/plain; charset="utf-8" When working with hpm registers, we need to calculate counter index by csr number. By now it was done manually. Let's add a function -- riscv_pmu_csrno_to_ctr_idx(), which incapsulates this action. Signed-off-by: Aleksandr Sergeev Reviewed-by: Alexei Filippov --- target/riscv/cpu_bits.h | 4 +++ target/riscv/csr.c | 73 ++++++++++++++--------------------------- target/riscv/pmu.c | 44 +++++++++++++++++++++++++ target/riscv/pmu.h | 1 + 4 files changed, 73 insertions(+), 49 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b62dd82fe7..5c3c1af64e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -1145,6 +1145,10 @@ typedef enum CTRType { /* RISC-V-specific interrupt pending bits. */ #define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 =20 +#define HPM_MCYCLE_IDX 0 +#define HPM_MTIME_IDX 1 +#define HPM_MINSTRET_IDX 2 + /* JVT CSR bits */ #define JVT_MODE 0x3F #define JVT_BASE (~0x3F) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c91658c3d..8bdbc71160 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -110,17 +110,8 @@ static RISCVException ctr(CPURISCVState *env, int csrn= o) { #if !defined(CONFIG_USER_ONLY) RISCVCPU *cpu =3D env_archcpu(env); - int ctr_index; - target_ulong ctr_mask; - int base_csrno =3D CSR_CYCLE; - bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; - - if (rv32 && csrno >=3D CSR_CYCLEH) { - /* Offset for RV32 hpmcounternh counters */ - base_csrno +=3D 0x80; - } - ctr_index =3D csrno - base_csrno; - ctr_mask =3D BIT(ctr_index); + uint32_t ctr_index =3D riscv_pmu_csrno_to_ctr_idx(csrno); + target_ulong ctr_mask =3D BIT(ctr_index); =20 if ((csrno >=3D CSR_CYCLE && csrno <=3D CSR_INSTRET) || (csrno >=3D CSR_CYCLEH && csrno <=3D CSR_INSTRETH)) { @@ -1166,9 +1157,9 @@ static RISCVException write_minstretcfgh(CPURISCVStat= e *env, int csrno, static RISCVException read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) { - int evt_index =3D csrno - CSR_MCOUNTINHIBIT; + uint32_t ctr_idx =3D riscv_pmu_csrno_to_ctr_idx(csrno); =20 - *val =3D env->mhpmevent_val[evt_index]; + *val =3D env->mhpmevent_val[ctr_idx]; =20 return RISCV_EXCP_NONE; } @@ -1176,14 +1167,15 @@ static RISCVException read_mhpmevent(CPURISCVState = *env, int csrno, static RISCVException write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { - int evt_index =3D csrno - CSR_MCOUNTINHIBIT; + uint32_t ctr_idx =3D riscv_pmu_csrno_to_ctr_idx(csrno); + uint64_t mhpmevt_val =3D val; uint64_t inh_avail_mask; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - env->mhpmevent_val[evt_index] =3D val; + env->mhpmevent_val[ctr_idx] =3D val; mhpmevt_val =3D mhpmevt_val | - ((uint64_t)env->mhpmeventh_val[evt_index] << 32); + ((uint64_t)env->mhpmeventh_val[ctr_idx] << 32); } else { inh_avail_mask =3D ~MHPMEVENT_FILTER_MASK | MHPMEVENT_BIT_MINH; inh_avail_mask |=3D riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH := 0; @@ -1193,10 +1185,10 @@ static RISCVException write_mhpmevent(CPURISCVState= *env, int csrno, inh_avail_mask |=3D (riscv_has_ext(env, RVH) && riscv_has_ext(env, RVS)) ? MHPMEVENT_BIT_VSINH = : 0; mhpmevt_val =3D val & inh_avail_mask; - env->mhpmevent_val[evt_index] =3D mhpmevt_val; + env->mhpmevent_val[ctr_idx] =3D mhpmevt_val; } =20 - riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + riscv_pmu_update_event_map(env, mhpmevt_val, ctr_idx); =20 return RISCV_EXCP_NONE; } @@ -1204,9 +1196,9 @@ static RISCVException write_mhpmevent(CPURISCVState *= env, int csrno, static RISCVException read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *val) { - int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + uint32_t ctr_idx =3D riscv_pmu_csrno_to_ctr_idx(csrno); =20 - *val =3D env->mhpmeventh_val[evt_index]; + *val =3D env->mhpmeventh_val[ctr_idx]; =20 return RISCV_EXCP_NONE; } @@ -1214,9 +1206,9 @@ static RISCVException read_mhpmeventh(CPURISCVState *= env, int csrno, static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { - int evt_index =3D csrno - CSR_MHPMEVENT3H + 3; + uint32_t ctr_idx =3D riscv_pmu_csrno_to_ctr_idx(csrno); uint64_t mhpmevth_val; - uint64_t mhpmevt_val =3D env->mhpmevent_val[evt_index]; + uint64_t mhpmevt_val =3D env->mhpmevent_val[ctr_idx]; target_ulong inh_avail_mask =3D (target_ulong)(~MHPMEVENTH_FILTER_MASK= | MHPMEVENTH_BIT_MINH); =20 @@ -1229,9 +1221,9 @@ static RISCVException write_mhpmeventh(CPURISCVState = *env, int csrno, =20 mhpmevth_val =3D val & inh_avail_mask; mhpmevt_val =3D mhpmevt_val | (mhpmevth_val << 32); - env->mhpmeventh_val[evt_index] =3D mhpmevth_val; + env->mhpmeventh_val[ctr_idx] =3D mhpmevth_val; =20 - riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); + riscv_pmu_update_event_map(env, mhpmevt_val, ctr_idx); =20 return RISCV_EXCP_NONE; } @@ -1357,7 +1349,7 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCVSt= ate *env, target_ulong val, static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { - int ctr_idx =3D csrno - CSR_MCYCLE; + uint32_t ctr_idx =3D riscv_pmu_csrno_to_ctr_idx(csrno); =20 return riscv_pmu_write_ctr(env, val, ctr_idx); } @@ -1365,7 +1357,7 @@ static RISCVException write_mhpmcounter(CPURISCVState= *env, int csrno, static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { - int ctr_idx =3D csrno - CSR_MCYCLEH; + uint32_t ctr_idx =3D riscv_pmu_csrno_to_ctr_idx(csrno); =20 return riscv_pmu_write_ctrh(env, val, ctr_idx); } @@ -1406,33 +1398,16 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *en= v, target_ulong *val, static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) { - uint16_t ctr_index; - - if (csrno >=3D CSR_MCYCLE && csrno <=3D CSR_MHPMCOUNTER31) { - ctr_index =3D csrno - CSR_MCYCLE; - } else if (csrno >=3D CSR_CYCLE && csrno <=3D CSR_HPMCOUNTER31) { - ctr_index =3D csrno - CSR_CYCLE; - } else { - return RISCV_EXCP_ILLEGAL_INST; - } - - return riscv_pmu_read_ctr(env, val, false, ctr_index); + uint32_t ctr_idx =3D riscv_pmu_csrno_to_ctr_idx(csrno); + return riscv_pmu_read_ctr(env, val, false, ctr_idx); } =20 static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) { - uint16_t ctr_index; =20 - if (csrno >=3D CSR_MCYCLEH && csrno <=3D CSR_MHPMCOUNTER31H) { - ctr_index =3D csrno - CSR_MCYCLEH; - } else if (csrno >=3D CSR_CYCLEH && csrno <=3D CSR_HPMCOUNTER31H) { - ctr_index =3D csrno - CSR_CYCLEH; - } else { - return RISCV_EXCP_ILLEGAL_INST; - } - - return riscv_pmu_read_ctr(env, val, true, ctr_index); + uint32_t ctr_idx =3D riscv_pmu_csrno_to_ctr_idx(csrno); + return riscv_pmu_read_ctr(env, val, true, ctr_idx); } =20 static int rmw_cd_mhpmcounter(CPURISCVState *env, int ctr_idx, @@ -1599,8 +1574,8 @@ static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cf= g_index, target_ulong *val, static RISCVException read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) { - int mhpmevt_start =3D CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; - int i; + uint32_t mhpmevt_start =3D riscv_pmu_csrno_to_ctr_idx(CSR_MHPMEVENT3); + uint32_t i; *val =3D 0; target_ulong *mhpm_evt_val; uint64_t of_bit_mask; diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a68809eef3..b983eadd83 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -600,3 +600,47 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) =20 cpu->pmu_avail_ctrs =3D cpu->cfg.pmu_mask; } + +uint32_t riscv_pmu_csrno_to_ctr_idx(int csrno) +{ + #define CASE_RANGE(low, high, offset) { \ + case (low)...(high): \ + return csrno - (low) + (offset); \ + } + #define HPMCOUNTER_START (HPM_MINSTRET_IDX + 1) + + switch (csrno) { + CASE_RANGE(CSR_MHPMEVENT3, CSR_MHPMEVENT31, HPMCOUNTER_START) + CASE_RANGE(CSR_MHPMEVENT3H, CSR_MHPMEVENT31H, HPMCOUNTER_START) + CASE_RANGE(CSR_HPMCOUNTER3, CSR_HPMCOUNTER31, HPMCOUNTER_START) + CASE_RANGE(CSR_HPMCOUNTER3H, CSR_HPMCOUNTER31H, HPMCOUNTER_START) + CASE_RANGE(CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER31, HPMCOUNTER_START) + CASE_RANGE(CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER31H, HPMCOUNTER_START) + + case CSR_MCYCLE: + case CSR_MCYCLEH: + case CSR_CYCLE: + case CSR_CYCLEH: + case CSR_MCYCLECFG: + case CSR_MCYCLECFGH: + return HPM_MCYCLE_IDX; + + case CSR_MINSTRET: + case CSR_MINSTRETH: + case CSR_INSTRET: + case CSR_INSTRETH: + case CSR_MINSTRETCFG: + case CSR_MINSTRETCFGH: + return HPM_MINSTRET_IDX; + + case CSR_TIME: + case CSR_TIMEH: + return HPM_MTIME_IDX; + + default: + g_assert_not_reached(); + } + + #undef HPMCOUNTER_START + #undef CASE_RANGE +} diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3853d0e262..8f019bea9f 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -38,5 +38,6 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, targ= et_ulong newpriv, bool new_virt); RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, bool upper_half, uint32_t ctr_idx); +uint32_t riscv_pmu_csrno_to_ctr_idx(int csrno); =20 #endif /* RISCV_PMU_H */ --=20 2.51.0