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Tsirkin" , Artyom Tarasenko , Peter Maydell , David Hildenbrand , Peter Xu Subject: [PATCH 12/14] system/memory: Factor address_space_ldst[M]_internal() helper out Date: Wed, 17 Dec 2025 15:31:48 +0100 Message-ID: <20251217143150.94463-13-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251217143150.94463-1-philmd@linaro.org> References: <20251217143150.94463-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1765982092138158500 All the LD/ST[W,L,Q] variants use the same template, only modifying the access size used. Unify as a single pair of LD/ST methods taking a MemOp argument. Thus use the 'm' suffix for MemOp. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- system/memory_ldst.c.inc | 289 ++++++++------------------------------- 1 file changed, 58 insertions(+), 231 deletions(-) diff --git a/system/memory_ldst.c.inc b/system/memory_ldst.c.inc index 823fc3a7561..e0c0c3f5dca 100644 --- a/system/memory_ldst.c.inc +++ b/system/memory_ldst.c.inc @@ -20,39 +20,43 @@ */ =20 /* warning: addr must be aligned */ -static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result, - enum device_endian endian) +static inline +uint64_t glue(address_space_ldm_internal, SUFFIX)(ARG1_DECL, MemOp mop, + hwaddr addr, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endia= n) { + const unsigned size =3D memop_size(mop); uint8_t *ptr; uint64_t val; MemoryRegion *mr; - hwaddr l =3D 4; + hwaddr l =3D size; hwaddr addr1; MemTxResult r; bool release_lock =3D false; =20 RCU_READ_LOCK(); mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); - if (l < 4 || !memory_access_is_direct(mr, false, attrs)) { + if (l < size || !memory_access_is_direct(mr, false, attrs)) { release_lock |=3D prepare_mmio_access(mr); =20 /* I/O case */ r =3D memory_region_dispatch_read(mr, addr1, &val, - MO_32 | devend_memop(endian), attr= s); + mop | devend_memop(endian), attrs); } else { /* RAM case */ - fuzz_dma_read_cb(addr, 4, mr); + fuzz_dma_read_cb(addr, size, mr); ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { case DEVICE_LITTLE_ENDIAN: - val =3D ldl_le_p(ptr); + val =3D ldn_le_p(ptr, size); break; case DEVICE_BIG_ENDIAN: - val =3D ldl_be_p(ptr); + val =3D ldn_be_p(ptr, size); break; default: - val =3D ldl_p(ptr); + val =3D ldn_p(ptr, size); break; } r =3D MEMTX_OK; @@ -67,87 +71,30 @@ static inline uint32_t glue(address_space_ldl_internal,= SUFFIX)(ARG1_DECL, return val; } =20 +/* warning: addr must be aligned */ +static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result, + enum device_endian endian) +{ + return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_32, addr, + attrs, result, endian); +} + /* warning: addr must be aligned */ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { - uint8_t *ptr; - uint64_t val; - MemoryRegion *mr; - hwaddr l =3D 8; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); - if (l < 8 || !memory_access_is_direct(mr, false, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - - /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, - MO_64 | devend_memop(endian), attr= s); - } else { - /* RAM case */ - fuzz_dma_read_cb(addr, 8, mr); - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - val =3D ldq_le_p(ptr); - break; - case DEVICE_BIG_ENDIAN: - val =3D ldq_be_p(ptr); - break; - default: - val =3D ldq_p(ptr); - break; - } - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); - return val; + return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_64, addr, + attrs, result, endian); } =20 uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { - uint8_t *ptr; - uint64_t val; - MemoryRegion *mr; - hwaddr l =3D 1; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); - if (!memory_access_is_direct(mr, false, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - - /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs); - } else { - /* RAM case */ - fuzz_dma_read_cb(addr, 1, mr); - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - val =3D ldub_p(ptr); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); - return val; + return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_8, addr, + attrs, result, + DEVICE_NATIVE_ENDIAN); } =20 /* warning: addr must be aligned */ @@ -155,37 +102,46 @@ static inline uint16_t glue(address_space_lduw_intern= al, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { + return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_16, addr, + attrs, result, endian); +} + +static inline +void glue(address_space_stm_internal, SUFFIX)(ARG1_DECL, MemOp mop, + hwaddr addr, uint64_t val, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) +{ + const unsigned size =3D memop_size(mop); uint8_t *ptr; - uint64_t val; MemoryRegion *mr; - hwaddr l =3D 2; + hwaddr l =3D size; hwaddr addr1; MemTxResult r; bool release_lock =3D false; =20 RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, false, attrs); - if (l < 2 || !memory_access_is_direct(mr, false, attrs)) { + mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); + if (l < size || !memory_access_is_direct(mr, true, attrs)) { release_lock |=3D prepare_mmio_access(mr); - - /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, - MO_16 | devend_memop(endian), attr= s); + r =3D memory_region_dispatch_write(mr, addr1, val, + mop | devend_memop(endian), attrs= ); } else { /* RAM case */ - fuzz_dma_read_cb(addr, 2, mr); ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { case DEVICE_LITTLE_ENDIAN: - val =3D lduw_le_p(ptr); + stn_le_p(ptr, size, val); break; case DEVICE_BIG_ENDIAN: - val =3D lduw_be_p(ptr); + stn_be_p(ptr, size, val); break; default: - val =3D lduw_p(ptr); + stn_p(ptr, size, val); break; } + invalidate_and_set_dirty(mr, addr1, size); r =3D MEMTX_OK; } if (result) { @@ -195,7 +151,6 @@ static inline uint16_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, bql_unlock(); } RCU_READ_UNLOCK(); - return val; } =20 /* warning: addr must be aligned */ @@ -203,74 +158,16 @@ static inline void glue(address_space_stl_internal, S= UFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l =3D 4; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 4 || !memory_access_is_direct(mr, true, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, - MO_32 | devend_memop(endian), att= rs); - } else { - /* RAM case */ - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - stl_le_p(ptr, val); - break; - case DEVICE_BIG_ENDIAN: - stl_be_p(ptr, val); - break; - default: - stl_p(ptr, val); - break; - } - invalidate_and_set_dirty(mr, addr1, 4); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); + glue(address_space_stm_internal, SUFFIX)(ARG1, MO_32, addr, val, + attrs, result, endian); } =20 void glue(address_space_stb, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result) { - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l =3D 1; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); - if (!memory_access_is_direct(mr, true, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, MO_8, attrs); - } else { - /* RAM case */ - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - stb_p(ptr, val); - invalidate_and_set_dirty(mr, addr1, 1); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); + glue(address_space_stm_internal, SUFFIX)(ARG1, MO_8, addr, val, + attrs, result, + DEVICE_NATIVE_ENDIAN); } =20 /* warning: addr must be aligned */ @@ -278,86 +175,16 @@ static inline void glue(address_space_stw_internal, S= UFFIX)(ARG1_DECL, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l =3D 2; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 2 || !memory_access_is_direct(mr, true, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, - MO_16 | devend_memop(endian), att= rs); - } else { - /* RAM case */ - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - stw_le_p(ptr, val); - break; - case DEVICE_BIG_ENDIAN: - stw_be_p(ptr, val); - break; - default: - stw_p(ptr, val); - break; - } - invalidate_and_set_dirty(mr, addr1, 2); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); + glue(address_space_stm_internal, SUFFIX)(ARG1, MO_16, addr, val, + attrs, result, endian); } =20 static inline void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result, enum device_endian endian) { - uint8_t *ptr; - MemoryRegion *mr; - hwaddr l =3D 8; - hwaddr addr1; - MemTxResult r; - bool release_lock =3D false; - - RCU_READ_LOCK(); - mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); - if (l < 8 || !memory_access_is_direct(mr, true, attrs)) { - release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, - MO_64 | devend_memop(endian), att= rs); - } else { - /* RAM case */ - ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); - switch (endian) { - case DEVICE_LITTLE_ENDIAN: - stq_le_p(ptr, val); - break; - case DEVICE_BIG_ENDIAN: - stq_be_p(ptr, val); - break; - default: - stq_p(ptr, val); - break; - } - invalidate_and_set_dirty(mr, addr1, 8); - r =3D MEMTX_OK; - } - if (result) { - *result =3D r; - } - if (release_lock) { - bql_unlock(); - } - RCU_READ_UNLOCK(); + glue(address_space_stm_internal, SUFFIX)(ARG1, MO_64, addr, val, + attrs, result, endian); } =20 #define ENDIANNESS --=20 2.52.0