From nobody Thu Dec 18 09:41:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929167; cv=none; d=zohomail.com; s=zohoarc; b=eTUalQ0N1iLByOzHKgxMyQcg94QKGJywJ3JQySS0MtacpbehtTfrQF2SvV25NhrcXXCUbDTP3Rab2zj6IFMy/S71lU1nFSIvfddcH++S6RJtPFWpzUhrZT2lM+/lq307EL905PHxzOy0NpLsKHFwK1lvCrKYy6INFBhnfwycOkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929167; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=a3U+ZaBuXfpA0G4zxktPBWyoxo5yyQM9fwBSNf9EjgA=; b=BpBxD6HDjQuj7Oi5J4Yhq0Zsa3HJ7nZcgIY2WRLEgO3MkkoR9fMSKYyK++pXPxwkwcWecDxnkHNSpA6b40qG5X7EeeywpclALu32xyom/3MJsLHnz1lPPxbjx5orV731W0GaDFEDm0wIUjaWN4ppTCf8+FissDov8MKEfAHo5ys= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17659291670671007.6211724292301; Tue, 16 Dec 2025 15:52:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenH-0001Gf-Oc; Tue, 16 Dec 2025 18:49:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen0-0001BP-VW for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:13 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemy-0006lX-KO for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=a3U+ZaBuXfpA0G4zxktPBWyoxo5yyQM9fwBSNf9EjgA=; b=dfifWosGclhWLdq 96/iaOU8zt72AswHw0KWC8XbAc+oWnwSeDNImjvMpBsP86XjTAXYjV41n6emALjWSRDbOnMWPxrah UEpLnOif+HuQ66Lrnfkl8IrdNRzX8oXWpjQWRZ9AGpe3NB0D6zJBvOpHKhH9xDltpONAFy3mVtbFU Xs=; Date: Wed, 17 Dec 2025 00:51:10 +0100 Subject: [PATCH 05/14] configs/target: Implement per-binary TargetInfo structure for riscv MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-5-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929168395154100 Defines TargetInfo for 32- and 64-bit riscv binaries. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++++++++++ configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++++++++++ configs/targets/meson.build | 1 + 3 files changed, 53 insertions(+) diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-so= ftmmu.c new file mode 100644 index 0000000000..897c93594b --- /dev/null +++ b/configs/targets/riscv32-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv32) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" + +static const TargetInfo target_info_riscv32_system =3D { + .target_name =3D "riscv32", + .target_arch =3D SYS_EMU_TARGET_RISCV32, + .long_bits =3D 32, + .cpu_type =3D TYPE_RISCV_CPU, + .machine_typename =3D TYPE_TARGET_RISCV32_MACHINE, + .endianness =3D ENDIAN_MODE_LITTLE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_riscv32_system; +} diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-so= ftmmu.c new file mode 100644 index 0000000000..d2e4520d76 --- /dev/null +++ b/configs/targets/riscv64-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv64) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" + +static const TargetInfo target_info_riscv64_system =3D { + .target_name =3D "riscv64", + .target_arch =3D SYS_EMU_TARGET_RISCV64, + .long_bits =3D 64, + .cpu_type =3D TYPE_RISCV_CPU, + .machine_typename =3D TYPE_TARGET_RISCV64_MACHINE, + .endianness =3D ENDIAN_MODE_LITTLE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_riscv64_system; +} diff --git a/configs/targets/meson.build b/configs/targets/meson.build index cca2514eb5..2ab4d27eaf 100644 --- a/configs/targets/meson.build +++ b/configs/targets/meson.build @@ -1,5 +1,6 @@ foreach target : [ 'arm-softmmu', 'aarch64-softmmu', + 'riscv32-softmmu', 'riscv64-softmmu' ] config_target_info +=3D {target : files(target + '.c')} endforeach --=20 2.51.0