From nobody Thu Dec 18 09:41:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929182; cv=none; d=zohomail.com; s=zohoarc; b=g3C7s3LGGpSHL0gQCv39WF6Hi5u6kH2UdsKzCfdN7K3BRLNzFQm8y2QL2GBWlfEjglno/lmmrFbMIxYzBrsGY0M84elxqiwmlMjM/RxC4IOirXvaFvAfOXC7F/Wj8E9/AejByIz0mj7K8D9StraRIZDqhnTy9Hc8DZ3cOwZ5lvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929182; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Lh6q/PRs+COIODpbn3Lbfbr1eCux7qx9JaD+WFn/UEc=; b=n7nGYeqpOPUK7dx36xFDpUw7/Nv+qmrgbjIbHWYmRKcW0TOwTQAGkoYuA3EwPmNBZYWdNsJMsd4P0hkN0gOCzWzRDboov0QVIFDGlWTRGM1uaVBfaTmXN+N8xNg02JHaS3+bNXThXZP3WoIhQ+lhE19Ryg5ni2phe3rFaHUXDfU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929181862623.1330901901857; Tue, 16 Dec 2025 15:53:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenH-0001Gd-NF; Tue, 16 Dec 2025 18:49:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen0-0001BK-UK for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:13 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemw-0006lM-Q9 for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=Lh6q/PRs+COIODpbn3Lbfbr1eCux7qx9JaD+WFn/UEc=; b=pEIiO57eE1ywOIw pFImcnDlO3pk9M6PDmUx8u1Fl8pb72WTSztTRMA8Q11FKOjDGz4xDrzjuShg7CP+cYxisOuvr3bD2 1XnaKGX04s9X+doBqszDgPWh4O/CdxMuwUMmZ8rtkWGEx9kcglQnvcptIioq7wwd6/wpT4bF0ANwn UQ=; Date: Wed, 17 Dec 2025 00:51:07 +0100 Subject: [PATCH 02/14] hw/riscv: Add macros and globals for simplifying machine definitions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-2-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929184516154100 Adds macros and global interfaces for defining machines available only in qemu-system-riscv32, qemu-system-riscv64, or both. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- include/hw/riscv/machines-qom.h | 26 ++++++++++++++++++++++++++ target/riscv/machine.c | 17 +++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qo= m.h index 6e2c542c87..2254b2dbcc 100644 --- a/include/hw/riscv/machines-qom.h +++ b/include/hw/riscv/machines-qom.h @@ -17,4 +17,30 @@ #define TYPE_TARGET_RISCV64_MACHINE \ "target-info-riscv64-machine" =20 +/* + * Interfaces specifiying wether a given QOM object is available in + * qemu-system-riscv32, qemu-riscv-riscv64, or both. + */ + +extern InterfaceInfo riscv32_machine_interfaces[]; +extern InterfaceInfo riscv64_machine_interfaces[]; +extern InterfaceInfo riscv32_64_machine_interfaces[]; + +/* + * Helper macros for defining machines available in qemu-system-riscv32, + * qemu-system-riscv64, or both. + */ + +#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv32_machine_interfaces) + +#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv64_machine_interfaces) + +#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv32_64_machine_interfaces) + #endif diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 13eb292c4a..3d2e3968fd 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -23,6 +23,7 @@ #include "migration/cpu.h" #include "exec/icount.h" #include "target/riscv/debug.h" +#include "hw/riscv/machines-qom.h" =20 static bool pmp_needed(void *opaque) { @@ -503,3 +504,19 @@ const VMStateDescription vmstate_riscv_cpu =3D { NULL } }; + +InterfaceInfo riscv32_machine_interfaces[] =3D { + { TYPE_TARGET_RISCV32_MACHINE }, + { } +}; + +InterfaceInfo riscv64_machine_interfaces[] =3D { + { TYPE_TARGET_RISCV64_MACHINE }, + { } +}; + +InterfaceInfo riscv32_64_machine_interfaces[] =3D { + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, + { } +}; --=20 2.51.0