From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929181; cv=none; d=zohomail.com; s=zohoarc; b=FuQEp0gS2rRKg9W8M+qk8tlRg/wOA16Tsg1hAfbJbrv3ee5Nfu5CDWyVhBIJ6jOTE73/mnvityT2+Rnfw7Trb1UNVMGbxFYOkYHCEhTfQ6rB9mwEBMwimlzoqqhEbgo1XBRPS6AMhBRsAU7NzV4rCijMa6j7Dq+fZsCjUWDqhzI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929181; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=HVrHmCLtKG/li6bva9ES51CEQVlXbEoSxOKkY91hKRw=; b=bp3GTATHE8igBCypbfwM4WKfl5CiL/RZKoyS8xBN0iVusQB/ffVRC2oW2nYIZQMkttA1OpN6fHyf90qzHhvTxVeKh5VZhjG9wYP6P476Utu7LUmvp1j4DWsZtth5+PAWUFV3f0Ax44KRpNUT4xPvw7wEKg2sbZES6HNryIFOUjA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929181208719.1198987859791; Tue, 16 Dec 2025 15:53:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenH-0001GY-5h; Tue, 16 Dec 2025 18:49:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen0-0001BQ-Vi for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:13 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemw-0006lF-Q6 for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=HVrHmCLtKG/li6bva9ES51CEQVlXbEoSxOKkY91hKRw=; b=jiXqVZeokxRuI4G KSk/+NWnTuJ4gEQt0LWCOz+WdPRCkCCI08AC0nuQxwiOsVMYLePg9EYUQdg2fnn27/f0/oWptOF8m 2Xb5yHGQdJdfCF65fT36EsxuP/pG+OBnRlENDc0c43nxEKhMJUJCa9oUfSkvKbXTWFlczQWDGfOim oM=; Date: Wed, 17 Dec 2025 00:51:06 +0100 Subject: [PATCH 01/14] hw/riscv: Register generic riscv[32|64] QOM interfaces MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-1-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929181705158500 Defines generic 32- and 64-bit riscv machine interfaces for machines to implement. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- include/hw/riscv/machines-qom.h | 20 ++++++++++++++++++++ target-info-qom.c | 9 +++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qo= m.h new file mode 100644 index 0000000000..6e2c542c87 --- /dev/null +++ b/include/hw/riscv/machines-qom.h @@ -0,0 +1,20 @@ +/* + * QOM type definitions for riscv32 / riscv64 machines + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_RISCV_MACHINES_QOM_H +#define HW_RISCV_MACHINES_QOM_H + +#include "hw/boards.h" + +#define TYPE_TARGET_RISCV32_MACHINE \ + "target-info-riscv32-machine" + +#define TYPE_TARGET_RISCV64_MACHINE \ + "target-info-riscv64-machine" + +#endif diff --git a/target-info-qom.c b/target-info-qom.c index 7fd58d2481..aaaebd55c7 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qom/object.h" #include "hw/arm/machines-qom.h" +#include "hw/riscv/machines-qom.h" =20 static const TypeInfo target_info_types[] =3D { { @@ -19,6 +20,14 @@ static const TypeInfo target_info_types[] =3D { .name =3D TYPE_TARGET_AARCH64_MACHINE, .parent =3D TYPE_INTERFACE, }, + { + .name =3D TYPE_TARGET_RISCV32_MACHINE, + .parent =3D TYPE_INTERFACE, + }, + { + .name =3D TYPE_TARGET_RISCV64_MACHINE, + .parent =3D TYPE_INTERFACE, + }, }; =20 DEFINE_TYPES(target_info_types) --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929182; cv=none; d=zohomail.com; s=zohoarc; b=g3C7s3LGGpSHL0gQCv39WF6Hi5u6kH2UdsKzCfdN7K3BRLNzFQm8y2QL2GBWlfEjglno/lmmrFbMIxYzBrsGY0M84elxqiwmlMjM/RxC4IOirXvaFvAfOXC7F/Wj8E9/AejByIz0mj7K8D9StraRIZDqhnTy9Hc8DZ3cOwZ5lvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929182; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Lh6q/PRs+COIODpbn3Lbfbr1eCux7qx9JaD+WFn/UEc=; b=n7nGYeqpOPUK7dx36xFDpUw7/Nv+qmrgbjIbHWYmRKcW0TOwTQAGkoYuA3EwPmNBZYWdNsJMsd4P0hkN0gOCzWzRDboov0QVIFDGlWTRGM1uaVBfaTmXN+N8xNg02JHaS3+bNXThXZP3WoIhQ+lhE19Ryg5ni2phe3rFaHUXDfU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929181862623.1330901901857; Tue, 16 Dec 2025 15:53:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenH-0001Gd-NF; Tue, 16 Dec 2025 18:49:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen0-0001BK-UK for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:13 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemw-0006lM-Q9 for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=Lh6q/PRs+COIODpbn3Lbfbr1eCux7qx9JaD+WFn/UEc=; b=pEIiO57eE1ywOIw pFImcnDlO3pk9M6PDmUx8u1Fl8pb72WTSztTRMA8Q11FKOjDGz4xDrzjuShg7CP+cYxisOuvr3bD2 1XnaKGX04s9X+doBqszDgPWh4O/CdxMuwUMmZ8rtkWGEx9kcglQnvcptIioq7wwd6/wpT4bF0ANwn UQ=; Date: Wed, 17 Dec 2025 00:51:07 +0100 Subject: [PATCH 02/14] hw/riscv: Add macros and globals for simplifying machine definitions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-2-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929184516154100 Adds macros and global interfaces for defining machines available only in qemu-system-riscv32, qemu-system-riscv64, or both. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- include/hw/riscv/machines-qom.h | 26 ++++++++++++++++++++++++++ target/riscv/machine.c | 17 +++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qo= m.h index 6e2c542c87..2254b2dbcc 100644 --- a/include/hw/riscv/machines-qom.h +++ b/include/hw/riscv/machines-qom.h @@ -17,4 +17,30 @@ #define TYPE_TARGET_RISCV64_MACHINE \ "target-info-riscv64-machine" =20 +/* + * Interfaces specifiying wether a given QOM object is available in + * qemu-system-riscv32, qemu-riscv-riscv64, or both. + */ + +extern InterfaceInfo riscv32_machine_interfaces[]; +extern InterfaceInfo riscv64_machine_interfaces[]; +extern InterfaceInfo riscv32_64_machine_interfaces[]; + +/* + * Helper macros for defining machines available in qemu-system-riscv32, + * qemu-system-riscv64, or both. + */ + +#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv32_machine_interfaces) + +#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv64_machine_interfaces) + +#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv32_64_machine_interfaces) + #endif diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 13eb292c4a..3d2e3968fd 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -23,6 +23,7 @@ #include "migration/cpu.h" #include "exec/icount.h" #include "target/riscv/debug.h" +#include "hw/riscv/machines-qom.h" =20 static bool pmp_needed(void *opaque) { @@ -503,3 +504,19 @@ const VMStateDescription vmstate_riscv_cpu =3D { NULL } }; + +InterfaceInfo riscv32_machine_interfaces[] =3D { + { TYPE_TARGET_RISCV32_MACHINE }, + { } +}; + +InterfaceInfo riscv64_machine_interfaces[] =3D { + { TYPE_TARGET_RISCV64_MACHINE }, + { } +}; + +InterfaceInfo riscv32_64_machine_interfaces[] =3D { + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, + { } +}; --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929015818625.4933841111708; Tue, 16 Dec 2025 15:50:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVen9-0001DR-KX; Tue, 16 Dec 2025 18:49:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemy-0001An-Sn for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:10 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemw-0006lO-Q5 for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=+fD/7JQa5FuLmN7yxAhnPUWNpgKG+9LM4Dx9os85w2w=; b=wg/kkk3rntcM+iR RsAQ4zBUaz+xIAdNgUeJVhbCdscVHXcNI1zmjuoFl/fqPriT0spxxipGr2naNXjDMXaAbnb/+qcoj hVGRuB4Xt763pwBOXge8GDjsk00eHMIEte0tDRNsaH0Kz54/3hd461gReFh1DKph599BQu9y/8NRI sQ=; Date: Wed, 17 Dec 2025 00:51:08 +0100 Subject: [PATCH 03/14] hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-3-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929057424154100 Register machines able to run in qemu-system-riscv32, qemu-system-riscv64, or both. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- hw/riscv/microblaze-v-generic.c | 3 ++- hw/riscv/microchip_pfsoc.c | 2 ++ hw/riscv/opentitan.c | 2 ++ hw/riscv/shakti_c.c | 2 ++ hw/riscv/sifive_e.c | 2 ++ hw/riscv/sifive_u.c | 2 ++ hw/riscv/spike.c | 2 ++ hw/riscv/virt.c | 3 +++ hw/riscv/xiangshan_kmh.c | 2 ++ 9 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index e863c50cbc..0df276f9fb 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -25,6 +25,7 @@ #include "system/address-spaces.h" #include "hw/char/xilinx_uartlite.h" #include "hw/misc/unimp.h" +#include "hw/riscv/machines-qom.h" =20 #define LMB_BRAM_SIZE (128 * KiB) #define MEMORY_BASEADDR 0x80000000 @@ -186,4 +187,4 @@ static void mb_v_generic_machine_init(MachineClass *mc) mc->default_cpus =3D 1; } =20 -DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init) +DEFINE_MACHINE_RISCV32_64("amd-microblaze-v-generic", mb_v_generic_machine= _init) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index bc4f409c19..51b53121c5 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -49,6 +49,7 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/machines-qom.h" #include "hw/riscv/microchip_pfsoc.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -748,6 +749,7 @@ static const TypeInfo microchip_icicle_kit_machine_type= info =3D { .class_init =3D microchip_icicle_kit_machine_class_init, .instance_init =3D microchip_icicle_kit_machine_instance_init, .instance_size =3D sizeof(MicrochipIcicleKitState), + .interfaces =3D riscv64_machine_interfaces, }; =20 static void microchip_icicle_kit_machine_init_register_types(void) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index d369a8a7dc..e8c6829365 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -26,6 +26,7 @@ #include "hw/boards.h" #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "qemu/units.h" #include "system/system.h" #include "system/address-spaces.h" @@ -335,6 +336,7 @@ static const TypeInfo open_titan_types[] =3D { .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(OpenTitanState), .class_init =3D opentitan_machine_class_init, + .interfaces =3D riscv32_machine_interfaces, } }; =20 diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 3e7f441172..d4cf72de3e 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "hw/boards.h" #include "hw/riscv/shakti_c.h" +#include "hw/riscv/machines-qom.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/intc/sifive_plic.h" @@ -92,6 +93,7 @@ static const TypeInfo shakti_c_machine_type_info =3D { .class_init =3D shakti_c_machine_class_init, .instance_init =3D shakti_c_machine_instance_init, .instance_size =3D sizeof(ShaktiCMachineState), + .interfaces =3D riscv64_machine_interfaces, }; =20 static void shakti_c_machine_type_info_register(void) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 7baed1958e..7ed419cf69 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -40,6 +40,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -167,6 +168,7 @@ static const TypeInfo sifive_e_machine_typeinfo =3D { .class_init =3D sifive_e_machine_class_init, .instance_init =3D sifive_e_machine_instance_init, .instance_size =3D sizeof(SiFiveEState), + .interfaces =3D riscv32_64_machine_interfaces, }; =20 static void sifive_e_machine_init_register_types(void) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2d27e925e8..2ff2059bb9 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -51,6 +51,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -742,6 +743,7 @@ static const TypeInfo sifive_u_machine_typeinfo =3D { .class_init =3D sifive_u_machine_class_init, .instance_init =3D sifive_u_machine_instance_init, .instance_size =3D sizeof(SiFiveUState), + .interfaces =3D riscv32_64_machine_interfaces, }; =20 static void sifive_u_machine_init_register_types(void) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ce190f6c62..69eb3dfc24 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -33,6 +33,7 @@ #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/riscv_htif.h" #include "hw/intc/riscv_aclint.h" #include "chardev/char.h" @@ -374,6 +375,7 @@ static const TypeInfo spike_machine_typeinfo =3D { .class_init =3D spike_machine_class_init, .instance_init =3D spike_machine_instance_init, .instance_size =3D sizeof(SpikeState), + .interfaces =3D riscv32_64_machine_interfaces, }; =20 static void spike_machine_init_register_types(void) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index aa4dd91325..f42fffb223 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -36,6 +36,7 @@ #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/riscv/numa.h" #include "kvm/kvm_riscv.h" #include "hw/firmware/smbios.h" @@ -1989,6 +1990,8 @@ static const TypeInfo virt_machine_typeinfo =3D { .instance_size =3D sizeof(RISCVVirtState), .interfaces =3D (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, { } }, }; diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index a95fd6174f..4d7e191098 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -41,6 +41,7 @@ #include "hw/riscv/boot.h" #include "hw/riscv/xiangshan_kmh.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/machines-qom.h" #include "system/system.h" =20 static const MemMapEntry xiangshan_kmh_memmap[] =3D { @@ -211,6 +212,7 @@ static const TypeInfo xiangshan_kmh_machine_info =3D { .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(XiangshanKmhState), .class_init =3D xiangshan_kmh_machine_class_init, + .interfaces =3D riscv64_machine_interfaces, }; =20 static void xiangshan_kmh_machine_register_types(void) --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zohomail.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929080561880.3725983822671; Tue, 16 Dec 2025 15:51:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenK-0001JI-76; Tue, 16 Dec 2025 18:49:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen1-0001BN-0i for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:14 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemy-0006lT-KP for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=SbulELr7fvQ/Mas+GWwU/UakpuILoL/WSUAL/5qfqFY=; b=Kn9nBieUSeZErcA BqlXnj6h34Uz9WeOof2dTsLttUoEJRHEFGmMonzcs9uvLLcmVaNhJZNlLDH68Tiijdk68Msw8U2M2 C0hEt2lQiSJmCLw/gvrHwfI4uyJJUCnmB062Y9cuch9j2QYY/fIQ0XeSVHXzc6qDEeo7Hdv+bpao9 cY=; Date: Wed, 17 Dec 2025 00:51:09 +0100 Subject: [PATCH 04/14] hw/core: Add riscv[32|64] to "none" machine MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-4-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: temperror (zohomail.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929118192158500 Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- hw/core/null-machine.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 67b769bd3e..77e4ed60e6 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -17,6 +17,7 @@ #include "system/address-spaces.h" #include "hw/core/cpu.h" #include "hw/arm/machines-qom.h" +#include "hw/riscv/machines-qom.h" =20 static void machine_none_init(MachineState *mch) { @@ -59,4 +60,6 @@ static void machine_none_machine_init(MachineClass *mc) DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init, { TYPE_TARGET_AARCH64_MACHINE }, { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, { }) --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929167; cv=none; d=zohomail.com; s=zohoarc; b=eTUalQ0N1iLByOzHKgxMyQcg94QKGJywJ3JQySS0MtacpbehtTfrQF2SvV25NhrcXXCUbDTP3Rab2zj6IFMy/S71lU1nFSIvfddcH++S6RJtPFWpzUhrZT2lM+/lq307EL905PHxzOy0NpLsKHFwK1lvCrKYy6INFBhnfwycOkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929167; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=a3U+ZaBuXfpA0G4zxktPBWyoxo5yyQM9fwBSNf9EjgA=; b=BpBxD6HDjQuj7Oi5J4Yhq0Zsa3HJ7nZcgIY2WRLEgO3MkkoR9fMSKYyK++pXPxwkwcWecDxnkHNSpA6b40qG5X7EeeywpclALu32xyom/3MJsLHnz1lPPxbjx5orV731W0GaDFEDm0wIUjaWN4ppTCf8+FissDov8MKEfAHo5ys= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17659291670671007.6211724292301; Tue, 16 Dec 2025 15:52:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenH-0001Gf-Oc; Tue, 16 Dec 2025 18:49:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen0-0001BP-VW for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:13 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemy-0006lX-KO for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=a3U+ZaBuXfpA0G4zxktPBWyoxo5yyQM9fwBSNf9EjgA=; b=dfifWosGclhWLdq 96/iaOU8zt72AswHw0KWC8XbAc+oWnwSeDNImjvMpBsP86XjTAXYjV41n6emALjWSRDbOnMWPxrah UEpLnOif+HuQ66Lrnfkl8IrdNRzX8oXWpjQWRZ9AGpe3NB0D6zJBvOpHKhH9xDltpONAFy3mVtbFU Xs=; Date: Wed, 17 Dec 2025 00:51:10 +0100 Subject: [PATCH 05/14] configs/target: Implement per-binary TargetInfo structure for riscv MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-5-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929168395154100 Defines TargetInfo for 32- and 64-bit riscv binaries. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++++++++++ configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++++++++++ configs/targets/meson.build | 1 + 3 files changed, 53 insertions(+) diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-so= ftmmu.c new file mode 100644 index 0000000000..897c93594b --- /dev/null +++ b/configs/targets/riscv32-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv32) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" + +static const TargetInfo target_info_riscv32_system =3D { + .target_name =3D "riscv32", + .target_arch =3D SYS_EMU_TARGET_RISCV32, + .long_bits =3D 32, + .cpu_type =3D TYPE_RISCV_CPU, + .machine_typename =3D TYPE_TARGET_RISCV32_MACHINE, + .endianness =3D ENDIAN_MODE_LITTLE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_riscv32_system; +} diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-so= ftmmu.c new file mode 100644 index 0000000000..d2e4520d76 --- /dev/null +++ b/configs/targets/riscv64-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv64) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" + +static const TargetInfo target_info_riscv64_system =3D { + .target_name =3D "riscv64", + .target_arch =3D SYS_EMU_TARGET_RISCV64, + .long_bits =3D 64, + .cpu_type =3D TYPE_RISCV_CPU, + .machine_typename =3D TYPE_TARGET_RISCV64_MACHINE, + .endianness =3D ENDIAN_MODE_LITTLE, +}; + +const TargetInfo *target_info(void) +{ + return &target_info_riscv64_system; +} diff --git a/configs/targets/meson.build b/configs/targets/meson.build index cca2514eb5..2ab4d27eaf 100644 --- a/configs/targets/meson.build +++ b/configs/targets/meson.build @@ -1,5 +1,6 @@ foreach target : [ 'arm-softmmu', 'aarch64-softmmu', + 'riscv32-softmmu', 'riscv64-softmmu' ] config_target_info +=3D {target : files(target + '.c')} endforeach --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929157; cv=none; d=zohomail.com; s=zohoarc; b=gL1EyKbevX4qFAxpaw4Ob2ffCVfsFGD587e0uDcKw7F6BjcDUV1hfpsGY2zeBg0ttt9K4pydJ8AZzdKjHdKsF17ywWhDt8YbSR5wav2LjyEVUb2ebrjBaONlvMMskVNg/9l2tFWQVZttd2oqqP8vKMN3YoNQHVqoDUlf6tA6c/g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929157; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=54mt/PTzZGX+TPISgLkPIrlQtFwnzbtxDC8UvzVAWmo=; b=PRI8Ps9M1t/YMCWgY5uj/uGfxqhOcGom7nIVvc2vFrjNmu6AAD8GTz9vBji6oOOpthNDtPhqLSLi2+GeTrDr0YbLE7UmlRoEFlEnDrbj5POEQP1T7hCueF/MM52GKqpGenY2lHwZno4rCdW4SqglhikOpsu5yKk8EloD+GUNzjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929157073128.15832602185424; Tue, 16 Dec 2025 15:52:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenH-0001GX-6U; Tue, 16 Dec 2025 18:49:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen0-0001BM-W3 for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:13 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemy-0006le-KR for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=54mt/PTzZGX+TPISgLkPIrlQtFwnzbtxDC8UvzVAWmo=; b=c7oml7BiAlLA5B8 oboswFuuxRzwMVmR2ymPl2sNd+QdxxwZKiBkQCOOo0K8RejXyg5/rHhdPSv8zs0V538K8eoN3Cx20 xChXOg0OvEsss1r3HEzmNqDCNtxMwvPJq86cTJqzs3oMFAULJI5NllEC0nx1ZH7Oi1+bKjIqs+PcY n0=; Date: Wed, 17 Dec 2025 00:51:11 +0100 Subject: [PATCH 06/14] target-info: Add target_riscv64() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-6-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929157632158500 Adds a helper function to tell if the binary is targeting riscv64 or not. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 6235962223..a4853ad4bb 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -71,4 +71,11 @@ bool target_arm(void); */ bool target_aarch64(void); =20 +/** + * target_riscv64: + * + * Returns whether the target architecture is riscv64 + */ +bool target_riscv64(void); + #endif diff --git a/target-info.c b/target-info.c index 24696ff411..6cc78e25c8 100644 --- a/target-info.c +++ b/target-info.c @@ -73,3 +73,8 @@ bool target_aarch64(void) { return target_arch() =3D=3D SYS_EMU_TARGET_AARCH64; } + +bool target_riscv64(void) +{ + return target_arch() =3D=3D SYS_EMU_TARGET_RISCV64; +} --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zohomail.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929118112916.0916697736789; Tue, 16 Dec 2025 15:51:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenA-0001Dd-8R; Tue, 16 Dec 2025 18:49:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen0-0001BL-UK for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:13 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemy-0006lo-KN for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=HQ/9L5rNO3zjZ1NHaoFq2/XxX4vXgnW07fih0NsZedM=; b=TuHzuUXJSPFcLpd 43a7vHcSOTOAIIDGAtmq5Ui74+nyNHPaAQJD5vV0DMT2kjcyF34vVTjP/l4yjTIT3w2hj5guSYnku EYsZOtQKqdTLRlcPLJSyL8lfNbUpO8M718luxmxJY1QubgCH5/as17aafDZ6MqBw58ram9T2zzfTP dI=; Date: Wed, 17 Dec 2025 00:51:12 +0100 Subject: [PATCH 07/14] target/riscv: Replace TYPE_RISCV_CPU_BASE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-7-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: temperror (zohomail.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929150080158500 TYPE_RISCV_CPU_BASE is used only to initialize the correct default machine for 3 machines. Replace it with a runtime check. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- include/hw/riscv/virt.h | 11 +++++++++++ target/riscv/cpu.h | 6 ------ hw/riscv/microblaze-v-generic.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 2 +- 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 7b4c2c8b7d..3a17641078 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,6 +19,7 @@ #ifndef HW_RISCV_VIRT_H #define HW_RISCV_VIRT_H =20 +#include "qemu/target-info.h" #include "hw/boards.h" #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" @@ -137,6 +138,16 @@ bool virt_is_iommu_sys_enabled(RISCVVirtState *s); void virt_acpi_setup(RISCVVirtState *vms); uint32_t imsic_num_bits(uint32_t count); =20 +static inline const char *virt_default_cpu_type(void) +{ + if (target_riscv64()) { + return TYPE_RISCV_CPU_BASE64; + } else { + return TYPE_RISCV_CPU_BASE32; + } +} + + /* * The virt machine physical address space used by some of the devices * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616406f07f..da2bc554d3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -39,12 +39,6 @@ typedef struct CPUArchState CPURISCVState; =20 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU =20 -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - /* * b0: Whether a instruction always raise a store AMO or not. */ diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index 0df276f9fb..0222ff0c06 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -26,6 +26,7 @@ #include "hw/char/xilinx_uartlite.h" #include "hw/misc/unimp.h" #include "hw/riscv/machines-qom.h" +#include "hw/riscv/virt.h" =20 #define LMB_BRAM_SIZE (128 * KiB) #define MEMORY_BASEADDR 0x80000000 @@ -183,7 +184,7 @@ static void mb_v_generic_machine_init(MachineClass *mc) mc->init =3D mb_v_generic_init; mc->min_cpus =3D 1; mc->max_cpus =3D 1; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D virt_default_cpu_type(); mc->default_cpus =3D 1; } =20 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 69eb3dfc24..7d1a642a78 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -34,6 +34,7 @@ #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/riscv/machines-qom.h" +#include "hw/riscv/virt.h" #include "hw/char/riscv_htif.h" #include "hw/intc/riscv_aclint.h" #include "chardev/char.h" @@ -351,7 +352,7 @@ static void spike_machine_class_init(ObjectClass *oc, c= onst void *data) mc->init =3D spike_board_init; mc->max_cpus =3D SPIKE_CPUS_MAX; mc->is_default =3D true; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D virt_default_cpu_type(); mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f42fffb223..6f6164e05d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1922,7 +1922,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->desc =3D "RISC-V VirtIO board"; mc->init =3D virt_machine_init; mc->max_cpus =3D VIRT_CPUS_MAX; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D virt_default_cpu_type(); mc->block_default_type =3D IF_VIRTIO; mc->no_cdrom =3D 1; mc->pci_allow_0_address =3D true; --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zohomail.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929024361511.8417040155157; Tue, 16 Dec 2025 15:50:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenJ-0001Is-VZ; Tue, 16 Dec 2025 18:49:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen2-0001BS-32 for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:14 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemz-0006lu-PV for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=OnTlwtr2WErgQ6f6Hrd7x4go/fqxZMxAQBasqqI88jM=; b=OQzs5zF3ZLaI+i5 guotCSUEL8OdZANKZmJ0Xdviff2kluCbnzks0PkBCCw3u0cRgxmSJu5RazCVhZbdWKF6VRRmW+iwc 7N2KCIfYRnvlU8EEFTA2l978C8thhJcOM+VMlFsmodp4pKCJpLLg8vRFBP+BWvdz0YgY9IKvOV9St 0s=; Date: Wed, 17 Dec 2025 00:51:13 +0100 Subject: [PATCH 08/14] target/riscv: Remove ifdefs in cpu.h MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-8-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: temperror (zohomail.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929070518158500 KVM fields of CPURISCVState are now always exposed as CONFIG_KVM cannot be used in common code. riscv_cpu_mxl() is changed to return CPURISCVState::misa_mxl unconditionally, as use of target_riscv64() would result in an extra load and compare with TargetInfo::target_arch. We might as well just perform a single load. Likewise, for cpu_recompute_xl(), cpu_address_xl(), and riscv_cpu_sxl(), we opt for returning the corresponding CPURISCVState field with ifdefs for system mode adding extra conditions. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 36 ++++++++---------------------------- 1 file changed, 8 insertions(+), 28 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index da2bc554d3..946665d9ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -497,14 +497,12 @@ struct CPUArchState { hwaddr kernel_addr; hwaddr fdt_addr; =20 -#ifdef CONFIG_KVM /* kvm timer */ bool kvm_timer_dirty; uint64_t kvm_timer_time; uint64_t kvm_timer_compare; uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; -#endif /* CONFIG_KVM */ =20 /* RNMI */ uint64_t mnscratch; @@ -703,14 +701,10 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) FIELD(TB_FLAGS, PM_PMM, 29, 2) FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) =20 -#ifdef TARGET_RISCV32 -#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) { return env->misa_mxl; } -#endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) @@ -754,9 +748,6 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, p= rivilege_mode_t mode) } #endif =20 -#if defined(TARGET_RISCV32) -#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) { #if !defined(CONFIG_USER_ONLY) @@ -765,43 +756,32 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState= *env) return env->misa_mxl; #endif } -#endif =20 -#if defined(TARGET_RISCV32) -#define cpu_address_xl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL cpu_address_xl(CPURISCVState *env) { -#ifdef CONFIG_USER_ONLY - return env->xl; -#else - int mode =3D cpu_address_mode(env); - - return cpu_get_xl(env, mode); +#ifndef CONFIG_USER_ONLY + if (target_riscv64()) { + int mode =3D cpu_address_mode(env); + return cpu_get_xl(env, mode); + } #endif + return env->xl; } -#endif =20 static inline int riscv_cpu_xlen(CPURISCVState *env) { return 16 << env->xl; } =20 -#ifdef TARGET_RISCV32 -#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) { -#ifdef CONFIG_USER_ONLY - return env->misa_mxl; -#else +#ifndef CONFIG_USER_ONLY if (env->misa_mxl !=3D MXL_RV32) { return get_field(env->mstatus, MSTATUS64_SXL); } #endif - return MXL_RV32; + return env->misa_mxl; } -#endif =20 static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg, uint32_t priv_ver, --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929154; cv=none; d=zohomail.com; s=zohoarc; b=YpYsSuCEtxVx2Zz3YSSmIwTTs7NNDHxQ4BTjmZpxInrrmGQz6jidTagehaNU7osRRmq4Y/a8qVxv7mNVCZraoTs31iByXmsmFaKhu16/lKh+TNdiZrHLQLXdX0XLZRAiKrxWErw3V58Z3HO3WJ4Xoy0ahZ8WsmG2jk0l2h1Dihc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929154; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=5LS6qTr8SyvzN335pzNMdcKQrS8VFuQg/dsljWu1Cfk=; b=gFxRf4LtR0tdnRRb1C/xNDW6fNyHjdAVKhLOCuVo2NR5E+t/V3lqFg1xIsbaUgR/hZ6QCRMC5JhjYm5OEHYiifrpZckw29fz/jRdWxf8/vFxzVCktBlDaulXNmrO7ZNFZnFsvgWVfcrXcgU5pssT6oyOm4t4Ur8zfTkL+P0q7bk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17659291540573.2906158382716058; Tue, 16 Dec 2025 15:52:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenA-0001Dw-Jb; Tue, 16 Dec 2025 18:49:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen0-0001BO-V6 for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:13 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVemy-0006lt-LO for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=5LS6qTr8SyvzN335pzNMdcKQrS8VFuQg/dsljWu1Cfk=; b=kL8rbsmyAHiMogR TLHnldmulFJ4GCZXVNAWCYK6e2PUhmydnlCJVRXKnHyW+FMnbBWGmVrQdQPNIYWLXMavUg5XLPnwd 8Y5qfbBj73k/uC6NhQYxV3E8MYFBNfDsqAfA0fcAouvEFXeA0BXz8RbKi7XmH2Cjvk3n/CeDxQofG fk=; Date: Wed, 17 Dec 2025 00:51:14 +0100 Subject: [PATCH 09/14] target/riscv: Replace TARGET_LONG_BITS in header exposed to common code MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-9-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929155736158500 Macro is used in hw/intc/riscv_imsic.c. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- target/riscv/cpu_bits.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b62dd82fe7..3d1c48487f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -810,7 +810,7 @@ typedef enum RISCVException { #define IRQ_PMU_OVF 13 #define IRQ_LOCAL_MAX 64 /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ -#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) +#define IRQ_LOCAL_GUEST_MAX (target_long_bits() - 1) =20 /* RNMI causes */ #define RNMI_MAX 16 --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929159; cv=none; d=zohomail.com; s=zohoarc; b=KN45GveJ75nOcHE7A61RX5nn30g+qjPsega/3/hEk3WnmtjnHVvmNw/cyZJbgSArGjIZIoJi/aP7dKwUeELYY/AK1GyuhbsiBTK+x+Gs24eM9pF3U1TYSQjmVH5a0ZKCUyiK8IIVmDNCQY7uIxYyYpkgOmqg66YmNAQ8MUqg5Ps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929159; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=FzpOcrVYjNzEtYgsWqtDXWI5lGWknI6VeBb0xQgmtOw=; b=lWoZp/Va+MA0tYDuDmiIVdDgafDyxP0FXHH2VKQjyfS/nFgqFr+xvBI5UCZ2MDV7TuQL/xBP9F2hy02qvclS3xbOgGGRO6HFeJJpgpEEPBZYTJjOJHTKwklggGMUkHXlnGRQXjEsiy+/nKFfq2Y4Jgmb6vjvJ9+lJIO2BjOKw9A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929157736510.21294836781396; Tue, 16 Dec 2025 15:52:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenH-0001Ge-OS; Tue, 16 Dec 2025 18:49:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen5-0001CU-DT for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:18 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen3-0006m4-J3 for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=FzpOcrVYjNzEtYgsWqtDXWI5lGWknI6VeBb0xQgmtOw=; b=QnxwhycABv+XnoF 8pDtw0Ukid1fVaNi9wKNJ1CeGDuLXrRG1eyiijDiHejGl4cY4X7rrhi0h079q+9P5WD8mdRz+WX6c OJAKzWSEY79NgWBCwpiF0ezOuX9PUShivvIGmkQZdUx+D39Aq0UJ6j7w5sRCLAfVuJx4QENuVXYD8 v8=; Date: Wed, 17 Dec 2025 00:51:15 +0100 Subject: [PATCH 10/14] target/riscv: Move riscv_pmu_read_ctr() to internal csr.h header MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-10-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929162181154100 The function depends on target_ulong and is via the pmu.h header exposed to hw/riscv, this function is only used internally in pmu.c and csr.c, so move it to the internal csr.h header. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- target/riscv/csr.h | 3 +++ target/riscv/pmu.h | 2 -- target/riscv/pmu.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.h b/target/riscv/csr.h index 3752a0ef43..e6a6f2e85f 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -90,4 +90,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_= index, target_ulong val); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); =20 +/* PMU CSRs */ +RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, + bool upper_half, uint32_t ctr_idx); #endif /* RISCV_CSR_H */ diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3853d0e262..ca40cfeed6 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -36,7 +36,5 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t va= lue, uint32_t ctr_idx); void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, bool new_virt); -RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, - bool upper_half, uint32_t ctr_idx); =20 #endif /* RISCV_PMU_H */ diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 708f2ec7aa..9701c8cba6 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -22,6 +22,7 @@ #include "qemu/timer.h" #include "cpu.h" #include "pmu.h" +#include "target/riscv/csr.h" #include "exec/icount.h" #include "system/device_tree.h" =20 --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929045931759.0708288350307; Tue, 16 Dec 2025 15:50:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenC-0001E7-Jj; Tue, 16 Dec 2025 18:49:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen6-0001CZ-I2 for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:18 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen4-0006mH-Fs for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=vaTs1VnbsgKYFk8rZjeEaioTtQMT1eDTmwJ9+Jy4GbM=; b=xD8La5KHboaFf6w feyOhLUO5Ak7i2g4F+3wNeICCx7Beu+BWfDH5nI/iKoS9/j9fvIz3oS9WHumiC38WtpCfK6cAFMjh zzsEircaNsYkCyFt3aYK3k5CGTDxEUn5Fsbi0Qt2fuABXnu7VL8s7AedmuEL79SHPjRdnfCnqjdUg fo=; Date: Wed, 17 Dec 2025 00:51:16 +0100 Subject: [PATCH 11/14] target/riscv: Make pmu.h target-agnostic MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-11-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929071852154100 Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/pmu.h | 2 +- target/riscv/pmu.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index ca40cfeed6..273d8f3f94 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -34,7 +34,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_even= t_idx event_idx); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); -void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, +void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newp= riv, bool new_virt); =20 #endif /* RISCV_PMU_H */ diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 9701c8cba6..d818c2f8f6 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -115,7 +115,8 @@ static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, ui= nt32_t ctr_idx) * new priv and new virt values are passed in as arguments. */ static void riscv_pmu_icount_update_priv(CPURISCVState *env, - target_ulong newpriv, bool new_vi= rt) + privilege_mode_t newpriv, + bool new_virt) { uint64_t *snapshot_prev, *snapshot_new; uint64_t current_icount; @@ -155,7 +156,8 @@ static void riscv_pmu_icount_update_priv(CPURISCVState = *env, } =20 static void riscv_pmu_cycle_update_priv(CPURISCVState *env, - target_ulong newpriv, bool new_vir= t) + privilege_mode_t newpriv, + bool new_virt) { uint64_t *snapshot_prev, *snapshot_new; uint64_t current_ticks; @@ -190,7 +192,7 @@ static void riscv_pmu_cycle_update_priv(CPURISCVState *= env, counter_arr[env->priv] +=3D delta; } =20 -void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, +void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newp= riv, bool new_virt) { riscv_pmu_cycle_update_priv(env, newpriv, new_virt); --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929186; cv=none; d=zohomail.com; s=zohoarc; b=PURiO1mOgQIkDP54WwZqwZK5KwcWgN0LJnyfuLA45OaQwbo3LIz2uLLRyhOOhCat6UNgBzHwx1LwzgZzgf+JJzelk7/5cJL9pH/nFJWUXEpq5qJXnpWFd3drWblFmwIbvk0Kvc0rwrQu/DkrLVneJy+Vadn+8bnv7P7vLDJ4S1M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929186; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=R75J3pf9cXFNs6ESiMpqWKuQgrceG7VdVOtBGjF5oLs=; b=RnWSzShM/HUfPovelFqEm4Mt0maeNK63p45IGL+ghgf2CuP6hF3acEzG8ctlwXyUqIztFDQuHo9AvCVu+k7HqaOXxu6xFfCgXg3RIuz/+2Z7AtgKgfHx0Fykmm8Fj8yEDUBG3ubPMXB0/Fmrgt3XXUBUn6tD+gJpUuM9ERC5kFk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929186014540.2494253725205; Tue, 16 Dec 2025 15:53:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenI-0001HE-8J; Tue, 16 Dec 2025 18:49:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen5-0001CW-Un for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:18 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen4-0006mF-CW for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=R75J3pf9cXFNs6ESiMpqWKuQgrceG7VdVOtBGjF5oLs=; b=U6e4PruOUtd/hIZ GDTqMOXDS5sh+ZSxpmgi9m4WSMNUT/r9wIzaEwsHJSdUwagRbQEjFgVtktmSwzGB8bBfm1waLn6Mz RNabpDoGZfzWsgNFvrJvPsQCfPkulB+VUJJVOWf9+v8NTzcmwGEg5O0+E9o06nawMAeXXBb0QpgbN J8=; Date: Wed, 17 Dec 2025 00:51:17 +0100 Subject: [PATCH 12/14] target/riscv: Stub out kvm functions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-12-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929187728158500 Functions used externally by hw/riscv are stubbed out for non-kvm configurations, allowing a single compilation of hw/riscv. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier --- target/riscv/kvm/kvm-stub.c | 23 +++++++++++++++++++++++ target/riscv/kvm/meson.build | 1 + 2 files changed, 24 insertions(+) diff --git a/target/riscv/kvm/kvm-stub.c b/target/riscv/kvm/kvm-stub.c new file mode 100644 index 0000000000..64e39c96d8 --- /dev/null +++ b/target/riscv/kvm/kvm-stub.c @@ -0,0 +1,23 @@ +/* + * QEMU RISCV specific KVM stubs + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "target/riscv/kvm/kvm_riscv.h" + +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num) +{ + g_assert_not_reached(); +} + +uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) +{ + g_assert_not_reached(); +} diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build index 7e92415091..d3f395f431 100644 --- a/target/riscv/kvm/meson.build +++ b/target/riscv/kvm/meson.build @@ -1 +1,2 @@ +riscv_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c')) --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zohomail.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929069657432.53057215558533; Tue, 16 Dec 2025 15:51:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenG-0001GF-Ot; Tue, 16 Dec 2025 18:49:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen6-0001Ca-LP for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:18 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen4-0006mK-Tg for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=nNu+hhZPCxg3t1C9ePlO/uOhsAN+U4ctEJxn/FIV/o4=; b=qV+pUzzeZWA8/Cn mNhG50JGCbz7n9+mv1C975nB8UNcwnoH24FhhGOqYUMau5p0bsXjf58gjyWSAC3m3kFXRJkq3anl6 d3p1mWLhYN6CPzf0qBRzTg/0lYdNcdpUXjuLEeNqBsPIAvTlaTrVST/4k1YP0Wi8NntOsjRLdRhR9 nc=; Date: Wed, 17 Dec 2025 00:51:18 +0100 Subject: [PATCH 13/14] hw/riscv: Define SiFive E/U CPUs using runtime conditions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-13-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: temperror (zohomail.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929117200154100 Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/riscv/sifive_cpu.h | 26 +++++++++++++++++++------- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 4 ++-- 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h index 136799633a..8391141d5e 100644 --- a/include/hw/riscv/sifive_cpu.h +++ b/include/hw/riscv/sifive_cpu.h @@ -20,12 +20,24 @@ #ifndef HW_SIFIVE_CPU_H #define HW_SIFIVE_CPU_H =20 -#if defined(TARGET_RISCV32) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif +#include "qemu/target-info.h" + +static inline const char *sifive_e_cpu(void) +{ + if (target_riscv64()) { + return TYPE_RISCV_CPU_SIFIVE_E51; + } else { + return TYPE_RISCV_CPU_SIFIVE_E31; + } +} + +static inline const char *sifive_u_cpu(void) +{ + if (target_riscv64()) { + return TYPE_RISCV_CPU_SIFIVE_U54; + } else { + return TYPE_RISCV_CPU_SIFIVE_U34; + } +} =20 #endif /* HW_SIFIVE_CPU_H */ diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 7ed419cf69..458b21b9e3 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -151,7 +151,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc= , const void *data) mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; mc->init =3D sifive_e_machine_init; mc->max_cpus =3D 1; - mc->default_cpu_type =3D SIFIVE_E_CPU; + mc->default_cpu_type =3D sifive_e_cpu(); mc->default_ram_id =3D "riscv.sifive.e.ram"; mc->default_ram_size =3D sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2ff2059bb9..a04481806e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -723,7 +723,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc= , const void *data) mc->init =3D sifive_u_machine_init; mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpu_type =3D SIFIVE_U_CPU; + mc->default_cpu_type =3D sifive_u_cpu(); mc->default_cpus =3D mc->min_cpus; mc->default_ram_id =3D "riscv.sifive.u.ram"; mc->auto_create_sdcard =3D true; @@ -764,7 +764,7 @@ static void sifive_u_soc_instance_init(Object *obj) TYPE_RISCV_HART_ARRAY); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); - qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); + qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", sifive_e_cpu()); qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); =20 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUS= TER); --=20 2.51.0 From nobody Mon Feb 9 18:12:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1765929154; cv=none; d=zohomail.com; s=zohoarc; b=m1kljTczmxw95w1VgKspPuZcq/IKwU8D5o/w2FvuCuQWDCSZH37fGDUYn9Vt6XO/XDQItTquz3mduiR7fBf+ua08cKT6heJJ2/yzemxtffRNK2HWrkRayE2yyOoM0i5ErbY1thWjfl7tl+DZlBlx1wHBf3dNdBv697WeU+Tq8BQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765929154; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ukT0OFFR0/ZGWPyQvLLjAQEhulaNhwiqj8wfkkKlNQg=; b=MhlnAZ4DVgRU9TYjsdpjVZoRBzuo835lKdiv/JzJ6zYl23GiRU2BinWagVA/GNT167yHPkmO7d1pfPhpe8T9TbfrcMcY/Io2aPDNLK24OCg4hxJzksKJsiDU4SkGM8pvDLhvQPGNPWYJFJKdaknoFz7P/+hfG50zqibo7e9XMcM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765929152917346.68323902741724; Tue, 16 Dec 2025 15:52:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vVenK-0001Jn-N6; Tue, 16 Dec 2025 18:49:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen7-0001Cb-1x for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:18 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vVen5-0006mN-0l for qemu-devel@nongnu.org; Tue, 16 Dec 2025 18:49:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=ukT0OFFR0/ZGWPyQvLLjAQEhulaNhwiqj8wfkkKlNQg=; b=KJYTjhLtwr7u09X 9L2nubbkqA3/MR0L1JjD1CzNyz+SFoGWlLv3YtjV7pMH0IdZ2DnoITT4b0NlGioxJ3ELlgxjiicNQ UsHlTEdd8DQwSulszYaFJEz89Oqp8kVF0+heX1ndF2l/oZ7RdLQ5ITQIuNtePdNLFAz2zfZ/bnjOg XE=; Date: Wed, 17 Dec 2025 00:51:19 +0100 Subject: [PATCH 14/14] hw/riscv: Compile once MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251217-hw-riscv-cpu-int-v1-14-d24a4048d3aa@rev.ng> References: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> In-Reply-To: <20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng> To: qemu-devel@nongnu.org Cc: Anton Johansson , philmd@linaro.org, pierrick.bouvier@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1765929156214154100 Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/riscv/meson.build | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 2a8d5b136c..7bb13f7270 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -1,18 +1,18 @@ -riscv_ss =3D ss.source_set() -riscv_ss.add(files('boot.c')) -riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) -riscv_ss.add(files('riscv_hart.c')) -riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) -riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) -riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) -riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( +riscv_common_ss =3D ss.source_set() +riscv_common_ss.add(files('boot.c')) +riscv_common_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) +riscv_common_ss.add(files('riscv_hart.c')) +riscv_common_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'= )) +riscv_common_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_common_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) +riscv_common_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) +riscv_common_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) +riscv_common_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) +riscv_common_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microc= hip_pfsoc.c')) +riscv_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c= ')) +riscv_common_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( 'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-h= pm.c')) -riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-gen= eric.c')) -riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan= _kmh.c')) +riscv_common_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaz= e-v-generic.c')) +riscv_common_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xi= angshan_kmh.c')) =20 -hw_arch +=3D {'riscv': riscv_ss} +hw_common_arch +=3D {'riscv': riscv_common_ss} --=20 2.51.0