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Tue, 16 Dec 2025 16:22:27 -0800 (PST) Date: Wed, 17 Dec 2025 00:22:13 +0000 In-Reply-To: <20251217-aspeed-sgpio-v4-0-28bbb8dcab30@google.com> Mime-Version: 1.0 References: <20251217-aspeed-sgpio-v4-0-28bbb8dcab30@google.com> X-Mailer: b4 0.14.2 Message-ID: <20251217-aspeed-sgpio-v4-3-28bbb8dcab30@google.com> Subject: [PATCH v4 3/6] hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou Content-Type: text/plain; charset="utf-8" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3w_dBaQYKCgwA6nuzBs00sxq.o0y2qy6-pq7qxz0zsz6.03s@flex--yubinz.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1765931033241154100 Content-Transfer-Encoding: quoted-printable The SGPIO controller can generate interrupts based on various pin state changes, such as rising/falling edges or high/low levels. This change adds the necessary logic to detect these events, update the interrupt status registers, and signal the interrupt to the SoC. Signed-off-by: Yubin Zou --- include/hw/gpio/aspeed_sgpio.h | 2 + hw/gpio/aspeed_sgpio.c | 127 +++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 127 insertions(+), 2 deletions(-) diff --git a/include/hw/gpio/aspeed_sgpio.h b/include/hw/gpio/aspeed_sgpio.h index 60279a597c722f94fba406d60cb30a52ef9544bc..8a11a9998c013cb2e4be99690ec= d7bcd9dcb5815 100644 --- a/include/hw/gpio/aspeed_sgpio.h +++ b/include/hw/gpio/aspeed_sgpio.h @@ -58,7 +58,9 @@ struct AspeedSGPIOState { =20 /*< public >*/ MemoryRegion iomem; + int pending; qemu_irq irq; + qemu_irq sgpios[ASPEED_SGPIO_MAX_PIN_PAIR]; uint32_t ctrl_regs[ASPEED_SGPIO_MAX_PIN_PAIR]; uint32_t int_regs[ASPEED_SGPIO_MAX_INT]; }; diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c index dc2df137db247c178adc05807bd0595fc0cb5c52..c6e6b3f52a9a982171a03cda820= a4573674ab67d 100644 --- a/hw/gpio/aspeed_sgpio.c +++ b/hw/gpio/aspeed_sgpio.c @@ -12,9 +12,131 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/gpio/aspeed_sgpio.h" =20 +/* + * For each set of gpios there are three sensitivity registers that contr= ol + * the interrupt trigger mode. + * + * | 2 | 1 | 0 | trigger mode + * ----------------------------- + * | 0 | 0 | 0 | falling-edge + * | 0 | 0 | 1 | rising-edge + * | 0 | 1 | 0 | level-low + * | 0 | 1 | 1 | level-high + * | 1 | X | X | dual-edge + */ + +/* GPIO Interrupt Triggers */ +#define ASPEED_FALLING_EDGE 0 +#define ASPEED_RISING_EDGE 1 +#define ASPEED_LEVEL_LOW 2 +#define ASPEED_LEVEL_HIGH 3 +#define ASPEED_DUAL_EDGE 4 + +static void aspeed_clear_irq(AspeedSGPIOState *s, int idx) +{ + uint32_t reg_index =3D idx / 32; + uint32_t bit_index =3D idx % 32; + uint32_t pending =3D extract32(s->int_regs[reg_index], bit_index, 1); + + assert(s->pending >=3D pending); + + /* No change to s->pending if pending is 0 */ + s->pending -=3D pending; + + /* + * The write acknowledged the interrupt regardless of whether it + * was pending or not. The post-condition is that it mustn't be + * pending. Unconditionally clear the status bit. + */ + s->int_regs[reg_index] =3D deposit32(s->int_regs[reg_index], bit_index= , 1, 0); +} + +static void aspeed_evaluate_irq(AspeedSGPIOState *s, int sgpio_prev_high, + int sgpio_curr_high, int idx) +{ + uint32_t ctrl =3D s->ctrl_regs[idx]; + uint32_t falling_edge =3D 0, rising_edge =3D 0; + uint32_t int_trigger =3D SHARED_FIELD_EX32(ctrl, SGPIO_INT_TYPE); + uint32_t int_enabled =3D SHARED_FIELD_EX32(ctrl, SGPIO_INT_EN); + uint32_t reg_index =3D idx / 32; + uint32_t bit_index =3D idx % 32; + + if (!int_enabled) { + return; + } + + /* Detect edges */ + if (sgpio_curr_high && !sgpio_prev_high) { + rising_edge =3D 1; + } else if (!sgpio_curr_high && sgpio_prev_high) { + falling_edge =3D 1; + } + + if (((int_trigger =3D=3D ASPEED_FALLING_EDGE) && falling_edge) || + ((int_trigger =3D=3D ASPEED_RISING_EDGE) && rising_edge) || + ((int_trigger =3D=3D ASPEED_LEVEL_LOW) && !sgpio_curr_high) || + ((int_trigger =3D=3D ASPEED_LEVEL_HIGH) && sgpio_curr_high) || + ((int_trigger >=3D ASPEED_DUAL_EDGE) && (rising_edge || falling_e= dge))) + { + s->int_regs[reg_index] =3D deposit32(s->int_regs[reg_index], + bit_index, 1, 1); + /* Trigger the VIC IRQ */ + s->pending++; + } +} + +static void aspeed_sgpio_update(AspeedSGPIOState *s, uint32_t idx, + uint32_t value) +{ + uint32_t old =3D s->ctrl_regs[idx]; + uint32_t new =3D value; + uint32_t diff =3D (old ^ new); + if (diff) { + /* If the interrupt clear bit is set */ + if (SHARED_FIELD_EX32(new, SGPIO_INT_STATUS)) { + aspeed_clear_irq(s, idx); + /* Clear the interrupt clear bit */ + new &=3D ~SGPIO_INT_STATUS_MASK; + } + + /* Uppdate the control register. */ + s->ctrl_regs[idx] =3D new; + + /* If the output value is changed */ + if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_OUT_VAL)) { + /* ...trigger the line-state IRQ */ + qemu_set_irq(s->sgpios[idx], 1); + } + + /* If the input value is changed */ + if (SHARED_FIELD_EX32(diff, SGPIO_SERIAL_IN_VAL)) { + aspeed_evaluate_irq(s, + SHARED_FIELD_EX32(old, SGPIO_SERIAL_IN_VAL), + SHARED_FIELD_EX32(new, SGPIO_SERIAL_IN_VAL), + idx); + } + } + qemu_set_irq(s->irq, !!(s->pending)); +} + +static uint64_t aspeed_sgpio_2700_read_int_status_reg(AspeedSGPIOState *s, + uint32_t reg) +{ + uint32_t idx =3D reg - R_SGPIO_INT_STATUS_0; + if (idx >=3D ASPEED_SGPIO_MAX_INT) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: interrupt status index: %d, out of bounds\n", + __func__, idx); + return 0; + } + return s->int_regs[idx]; +} + + static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s, uint32_t reg) { @@ -38,7 +160,7 @@ static void aspeed_sgpio_2700_write_control_reg(AspeedSG= PIOState *s, __func__, idx); return; } - s->ctrl_regs[idx] =3D data; + aspeed_sgpio_update(s, idx, data); } =20 static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset, @@ -52,6 +174,7 @@ static uint64_t aspeed_sgpio_2700_read(void *opaque, hwa= ddr offset, =20 switch (reg) { case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7: + value =3D aspeed_sgpio_2700_read_int_status_reg(s, reg); break; case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL: value =3D aspeed_sgpio_2700_read_control_reg(s, reg); @@ -116,7 +239,7 @@ static void aspeed_sgpio_set_pin_level(AspeedSGPIOState= *s, int pin, bool level) } else { value &=3D ~bit_mask; } - s->ctrl_regs[pin >> 1] =3D value; + aspeed_sgpio_update(s, pin >> 1, value); } =20 static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name, --=20 2.52.0.305.g3fc767764a-goog