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a="90332267" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332267" X-CSE-ConnectionGUID: yJ6xNHsJQbqOyvE6rnALXg== X-CSE-MsgGUID: 64KR+f/gQbCJ8sjR7kEaUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265982" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu , Yu Chen Subject: [PATCH v2 11/11] dosc/cpu-models-x86: Add documentation for DiamondRapids Date: Mon, 15 Dec 2025 15:37:43 +0800 Message-Id: <20251215073743.4055227-12-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782890965158500 Content-Type: text/plain; charset="utf-8" Current DiamondRapids hasn't supported cache model. Instead, document its special CPU & cache topology to allow user emulate with "-smp" & "-machine smp-cache". Reviewed-by: Yu Chen Signed-off-by: Zhao Liu --- docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x8= 6.rst.inc index 6a770ca8351c..c4c8fc67a562 100644 --- a/docs/system/cpu-models-x86.rst.inc +++ b/docs/system/cpu-models-x86.rst.inc @@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live mig= ration compatibility is required, use the newest CPU model that is compatible across all desired hosts. =20 +``DiamondRapids`` + Intel Xeon Processor. + + Diamond Rapids product has a topology which differs from previous Xeon + products. It does not support SMT, but instead features a dual core + module (DCM) architecture. It also has core building blocks (CBB - die + level in CPU topology). The cache hierarchy is organized as follows: + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per + CBB. This cache topology can be emulated for DiamondRapids CPU model + using the smp-cache configuration as shown below: + + Example: + + :: + + -machine smp-cache.0.cache=3Dl1d,smp-cache.0.topology=3Dthread= ,\ + smp-cache.1.cache=3Dl1i,smp-cache.1.topology=3Dthread= ,\ + smp-cache.2.cache=3Dl2,smp-cache.2.topology=3Dmodule,\ + smp-cache.3.cache=3Dl3,smp-cache.3.topology=3Ddie + ``ClearwaterForest`` Intel Xeon Processor (ClearwaterForest, 2025) =20 --=20 2.34.1