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Mon, 15 Dec 2025 02:13:08 -0500 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2025 23:13:04 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 14 Dec 2025 23:13:02 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765782787; x=1797318787; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B5KsWLdeYBGnKB0r8a9UJrHbD4BabWmPHKGbGEUZ0Go=; b=KmSF4lpUGvBs+DV6iDQLcQaGp9hRV8TgGRvzbrghs+zPj4mdihZT3P6T 8HB1NJs7YJszyktfUm5Sbz/0fp+8hIr/jsDdlJ4Rco8i2jiCGNDjPh74H 4t0w7xj1pNHZkgMCDlyL8Ckmbzrf4dGxUnRIQJE4fxQpPVGWHYGutWenl T2dP2wOFWi2qh/kzSfCv7BxeiZwdOoR58bmuUzQGHJU1Y1oRtk4Sgcuuv CvMBVp5OQuEdE6U/L133NQL9yXEN3YpomGo/1bkK8oo45SWgQAG/V9Wyh UiU3tDmbMU3MjFrKXIPNHSawvVCCkC28yYwuHb5RjzEFvc+lv6fYFfslu g==; X-CSE-ConnectionGUID: 9IOrUwxsQpq/51gzCOSHJw== X-CSE-MsgGUID: ac2YUdeBQ7evqiTGxcELDw== X-IronPort-AV: E=McAfee;i="6800,10657,11642"; a="90332235" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332235" X-CSE-ConnectionGUID: SDz5MvHGTQyUzZBI1pDnFw== X-CSE-MsgGUID: tgJoFCkPTFSzBWpmIwqtfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265927" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH v2 01/11] i386/cpu: Add support for MOVRS in CPUID enumeration Date: Mon, 15 Dec 2025 15:37:33 +0800 Message-Id: <20251215073743.4055227-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782827436158500 Content-Type: text/plain; charset="utf-8" MOVRS is a new set of instructions introduced in the Intel platform Diamond Rapids, to load instructions that carry a read-shared hint. Functionally, MOVRS family is equivalent to existing load instructions, but its read-shared hint indicates the source memory location is likely to become read-shared by multiple processors, i.e., read in the future by at least one other processor before it is written (assuming it is ever written in the future). It could optimize the behavior of the caches, especially shared caches, for this data for future reads by multiple processors. Additionally, MOVRS family also includes a software prefetch instruction, PREFETCHRST2, that carries the same read-shared hint. [*] MOVRS family is enumerated by CPUID single-bit (0x7.0x1.EAX[bit 31]). Add its enumeration support. [*]: Intel Architecture Instruction Set Extensions and Future Features (rev.059). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891 --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 64dbef0ee154..7efb628e17a7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1266,7 +1266,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { NULL, "fred", "lkgs", "wrmsrns", NULL, "amx-fp16", NULL, "avx-ifma", NULL, NULL, "lam", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "movrs", }, .cpuid =3D { .eax =3D 7, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e405ec1dbc7e..0edba739c4e2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1045,6 +1045,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) /* Linear Address Masking */ #define CPUID_7_1_EAX_LAM (1U << 26) +/* MOVRS Instructions */ +#define CPUID_7_1_EAX_MOVRS (1U << 31) =20 /* The immediate form of MSR access instructions */ #define CPUID_7_1_ECX_MSR_IMM (1U << 5) --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 15 Dec 2025 02:13:10 -0500 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2025 23:13:06 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 14 Dec 2025 23:13:04 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765782787; x=1797318787; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vit3CDGKgADTcvTJz3NSHDWQVkt2LabKgxDAyaoeYJ4=; b=cf3BD4VgghGlD9mmbotMApbm+jrojzDzNFFRqfQhwO5Sgm00j23FOHEq 8DTC2W4C0WuzbjNymyH5jUQV0GxGKmxx5FnVrTfM3yqu06FD8jQ1hIAgz Z+WJ8utA/sydehouvJX0abHFWdMJxtdvzKqZV0vjsJY5ZmS9lxpK3Ti+X xxmKmjeYUm2mgboylb+/TdvS7K2qRXPevBlHg+HeE1S/2Fe4tjCzFMtTq u5sr7EHvrDrfkRmNC+Gk7bbRHSy0qVCaCfDJpRat9nd2NrS0IUPIjgRmN Sa09xJQV1w5/AXaurTVPrGErv3Isgz5DVF5vhjxvRCyFmVJakOjCoagOc A==; X-CSE-ConnectionGUID: G/qnI6sTTQC0ByfGlyk0gQ== X-CSE-MsgGUID: pStmCdhxRR68DvO/AJrgcw== X-IronPort-AV: E=McAfee;i="6800,10657,11642"; a="90332238" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332238" X-CSE-ConnectionGUID: NRKxrr7JQhiU1UKzHzKXMQ== X-CSE-MsgGUID: e2bXRFQ/Tye/jVk0vwdDrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265933" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH v2 02/11] i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions Date: Mon, 15 Dec 2025 15:37:34 +0800 Message-Id: <20251215073743.4055227-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782882988158500 Content-Type: text/plain; charset="utf-8" Intel Diamond Rapids adds new AMX instructions to support new formats and memory operations [*]. And it introduces the CPUID subleaf 0x1E.0x1 to centralize the discrete AMX feature bits within EAX. For new feature bits (CPUID 0x1E.0x1.EAX[bits 4,6-8]), it's straightforward to add their enurmeration support. In addition to the new features, CPUID 0x1E.0x1.EAX[bits 0-3] are mirrored positions of existing AMX feature bits distributing across the 0x7 leaves. It's not flexible to make these mirror bits have the same names as existing ones, because QEMU would try to set both original bit and mirror bit which would cause warning if host doesn't support 0x1E.0x1 subleaf. Thus, name these mirror bits with "*-mirror" suffix. [*]: Intel Architecture Instruction Set Extensions and Future Features (rev.059). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891 --- target/i386/cpu.c | 25 +++++++++++++++++++++++++ target/i386/cpu.h | 18 ++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7efb628e17a7..7cff00a1b160 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1037,6 +1037,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t ven= dor1, #define TCG_SGX_12_1_EAX_FEATURES 0 #define TCG_24_0_EBX_FEATURES 0 #define TCG_29_0_EBX_FEATURES 0 +#define TCG_1E_1_EAX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1332,6 +1333,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_7_2_EDX_FEATURES, }, + [FEAT_1E_1_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + "amx-int8-mirror", "amx-bf16-mirror", "amx-complex-mirror", "a= mx-fp16-mirror", + "amx-fp8", NULL, "amx-tf32", "amx-avx512", + "amx-movrs", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { + .eax =3D 0x1e, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EAX, + }, + .tcg_features =3D TCG_1E_1_EAX_FEATURES, + }, [FEAT_24_0_EBX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -8412,8 +8432,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } =20 if (count =3D=3D 0) { + uint32_t unused; + x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused, + &unused, &unused); /* Highest numbered palette subleaf */ *ebx =3D INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); + } else if (count =3D=3D 1) { + *eax =3D env->features[FEAT_1E_1_EAX]; } break; } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0edba739c4e2..dd18a33c6275 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -713,6 +713,7 @@ typedef enum FeatureWord { FEAT_7_2_EDX, /* CPUID[EAX=3D7,ECX=3D2].EDX */ FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ FEAT_29_0_EBX, /* CPUID[EAX=3D0x29,ECX=3D0].EBX */ + FEAT_1E_1_EAX, /* CPUID[EAX=3D0x1E,ECX=3D1].EAX */ FEATURE_WORDS, } FeatureWord; =20 @@ -1086,6 +1087,23 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w); /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) =20 +/* AMX_INT8 instruction (mirror of CPUID_7_0_EDX_AMX_INT8) */ +#define CPUID_1E_1_EAX_AMX_INT8_MIRROR (1U << 0) +/* AMX_BF16 instruction (mirror of CPUID_7_0_EDX_AMX_BF16) */ +#define CPUID_1E_1_EAX_AMX_BF16_MIRROR (1U << 1) +/* AMX_COMPLEX instruction (mirror of CPUID_7_1_EDX_AMX_COMPLEX) */ +#define CPUID_1E_1_EAX_AMX_COMPLEX_MIRROR (1U << 2) +/* AMX_FP16 instruction (mirror of CPUID_7_1_EAX_AMX_FP16) */ +#define CPUID_1E_1_EAX_AMX_FP16_MIRROR (1U << 3) +/* AMX_FP8 instruction */ +#define CPUID_1E_1_EAX_AMX_FP8 (1U << 4) +/* AMX_TF32 instruction */ +#define CPUID_1E_1_EAX_AMX_TF32 (1U << 6) +/* AMX_AVX512 instruction */ +#define CPUID_1E_1_EAX_AMX_AVX512 (1U << 7) +/* AMX_MOVRS instruction */ +#define CPUID_1E_1_EAX_AMX_MOVRS (1U << 8) + /* AVX10 128-bit vector support is present */ #define CPUID_24_0_EBX_AVX10_128 (1U << 16) /* AVX10 256-bit vector support is present */ --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 15 Dec 2025 02:13:11 -0500 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2025 23:13:07 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 14 Dec 2025 23:13:05 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765782790; x=1797318790; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Sh3Fg+ZYPcyL2OzkRyiBIJ95xMydGUhZTJlNihUC5Zw=; b=KFkIw3i8gON6z8Eeq3tjdOu02zY0e1BtAwb312YBsEEMczdmTktXWqda NoT0m8ROeTl/REIzVHheLefqNEZNtPhcKlrBlJIrM5KQ+zYBzxy46/37I kuOOfYIC8wV5RFotQ4nEQA3AxWGs0cLaFCL9ZaIn9QgRKWW+kfRj2/Ii2 cWKtNP+bvT6WCGB7RB8YATQIftZ9N9IXeVx8IQccnD80FZoJzCy3rEfW5 fmsCHQi0UuP1QNWSD/3Zzw2TYl5ae7bzKqfBo7S0m6aBcFBSG6guBUzA0 8riq13DEFpqUzjFA9eUlBZP6CI6WRNfw89ElXoWHtJmS1kCvLAnFHuOw1 g==; X-CSE-ConnectionGUID: rut8+5XjQDCE505ZG3KUZQ== X-CSE-MsgGUID: 0/LpYvP7T8+Rz/hMx0wNMg== X-IronPort-AV: E=McAfee;i="6800,10657,11642"; a="90332240" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332240" X-CSE-ConnectionGUID: tiHuj6yCQZygyuC845n+Gw== X-CSE-MsgGUID: YuAKVo5dTZaBaQlZbhc6CQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265940" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH v2 03/11] i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration Date: Mon, 15 Dec 2025 15:37:35 +0800 Message-Id: <20251215073743.4055227-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782879008158500 Content-Type: text/plain; charset="utf-8" AVX10_VNNI_INT (0x24.0x1.ECX[bit 2]) is a discrete feature bit introduced on Intel Diamond Rapids, which enumerates the support for EVEX VPDP* instructions for INT8/INT16 [*]. Although Intel AVX10.2 has already included new VPDP* INT8/INT16 VNNI instructions, a bit - AVX10_VNNI_INT - is still be separated. Relevant new instructions can be checked by either CPUID AVX10.2 OR AVX10_VNNI_INT (e.g., VPDPBSSD). Support CPUID 0x24.0x1 subleaf with AVX10_VNNI_INT enumeration for Guest. [*]: Intel Advanced Vector Extensions 10.2 Architecture Specification (rev 5.0). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721 --- target/i386/cpu.c | 29 ++++++++++++++++++++++++++++- target/i386/cpu.h | 4 ++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7cff00a1b160..068e00a8d466 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1038,6 +1038,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t ven= dor1, #define TCG_24_0_EBX_FEATURES 0 #define TCG_29_0_EBX_FEATURES 0 #define TCG_1E_1_EAX_FEATURES 0 +#define TCG_24_1_ECX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1385,6 +1386,18 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_29_0_EBX_FEATURES, }, + [FEAT_24_1_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + [2] =3D "avx10-vnni-int", + }, + .cpuid =3D { + .eax =3D 0x24, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_ECX, + }, + .tcg_features =3D TCG_24_1_ECX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -2041,6 +2054,11 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_APXF }, .to =3D { FEAT_29_0_EBX, ~0ull }, }, + + { + .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, + .to =3D { FEAT_24_1_ECX, ~0ull }, + }, }; =20 typedef struct X86RegisterInfo32 { @@ -8456,8 +8474,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ebx =3D 0; *ecx =3D 0; *edx =3D 0; - if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count = =3D=3D 0) { + + if (!(env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { + break; + } + if (count =3D=3D 0) { + uint32_t unused; + x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused, + &unused, &unused); *ebx =3D env->features[FEAT_24_0_EBX] | env->avx10_version; + } else if (count =3D=3D 1) { + *ecx =3D env->features[FEAT_24_1_ECX]; } break; } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index dd18a33c6275..749ac8455e18 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -714,6 +714,7 @@ typedef enum FeatureWord { FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ FEAT_29_0_EBX, /* CPUID[EAX=3D0x29,ECX=3D0].EBX */ FEAT_1E_1_EAX, /* CPUID[EAX=3D0x1E,ECX=3D1].EAX */ + FEAT_24_1_ECX, /* CPUID[EAX=3D0x24,ECX=3D0].ECX */ FEATURE_WORDS, } FeatureWord; =20 @@ -1115,6 +1116,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); CPUID_24_0_EBX_AVX10_256 | \ CPUID_24_0_EBX_AVX10_512) =20 +/* AVX10_VNNI_INT instruction */ +#define CPUID_24_1_ECX_AVX10_VNNI_INT (1U << 2) + /* * New Conditional Instructions (NCIs), explicit New Data Destination (NDD) * controls, and explicit Flags Suppression (NF) controls for select sets = of --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1765782842; cv=none; d=zohomail.com; s=zohoarc; b=h4+uH+cMlfbdHR/gJYWScoEBDHfUdjG64XZo+0TF2N58aDWg51KdWm8F9CxyjfPBoQAPbcgy9KGy1yHJgi+S6DKndP09SvnVKNCgUvv3M2XFO15mAQwTWVTHOSVg12SFV+n2clA6e+tg0errfCF24VTfyx4jaOalncRZsJa2tB0= ARC-Message-Signature: i=1; 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bh=YFkCMhjQ00OIu5ehPAgBMOVhRND05I7ydnpLq6fDoRM=; b=VrZJF50DHRp7q8BOnXW00nBQwCCLuZ68sVKi//dAZ/4+AWwac3jhpb6f je8Hgg1WW5CMPZTecMgRn5YuIlepE94Ni4elFXMefL6dFtvmkADPoW01R Q6K6vObnFhZtuZZ843TaZvrj8SLndFQj1yIsFSclo827/9EgneUPP2hts aqBbPkd0toTwI+74tg2dhUu0TCmJTswDBJ0mGsLe7OdaUq10sCmpVjDNc 7UTvvAC0A45aen99xruiPhfNM6ROvewxQA0bo/C2XZJoAHH9/uHGGNTGx Sn70Y1UI6yx3FNaMP2rrj5F+Z+/U4j3F94RvX/p5z76BK3ZpotLniCSj5 Q==; X-CSE-ConnectionGUID: MO76dmgWS0aZFkX0z9y2AQ== X-CSE-MsgGUID: 7eiHX7HZR7GvmbY4KFq5GA== X-IronPort-AV: E=McAfee;i="6800,10657,11642"; a="90332249" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332249" X-CSE-ConnectionGUID: GDs6CbsDRXKUCEc82UtOvw== X-CSE-MsgGUID: ILKgFsrNSJOtJnc0MQKSIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265945" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH v2 04/11] i386/cpu: Support AVX10.2 with AVX10 feature models Date: Mon, 15 Dec 2025 15:37:36 +0800 Message-Id: <20251215073743.4055227-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782844971158500 Content-Type: text/plain; charset="utf-8" Intel AVX10 Version 2 (Intel AVX10.2) includes a suite of new instructions delivering new AI features and performance, accelerated media processing, expanded Web Assembly, and Cryptography support, along with enhancements to existing legacy instructions for completeness and efficiency, and it is enumerated as version 2 in CPUID 0x24.0x0.EBX[bits 0-7] [*]. Considerring "Intel CPUs which support Intel AVX10.2 will include an enumeration for AVX10_VNNI_INT (CPUID.24H.01H:ECX.AVX10_VNNI_INT[2])" [*] and EVEX VPDP* instructions for INT8/INT16 (AVX10_VNNI_INT) are detected by either AVX10.2 OR AVX10_VNNI_INT, AVX10_VNNI_INT is part of AVX10.2, so any Intel AVX10.2 implementation lacking the AVX10_VNNI_INT enumeration should be considered buggy hardware. Therefore, it's necessary to set AVX10_VNNI_INT enumeration for Guest when the user specifies AVX10 version 2. For this, introduce AVX10 models to explicitly define the feature bits included in different AVX10 versions. [*]: Intel Advanced Vector Extensions 10.2 Architecture Specification (rev 5.0). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721 --- target/i386/cpu.c | 120 +++++++++++++++++++++++++++++++++++++++++++--- target/i386/cpu.h | 2 + 2 files changed, 115 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 068e00a8d466..05b001b80cfd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2382,6 +2382,40 @@ x86_cpu_def_get_versions(const X86CPUDefinition *def) return def->versions ?: default_version_list; } =20 +/* CPUID 0x24.0x0 (EAX, EBX, ECX, EDX) and 0x24.0x1 (EAX, EBX, ECX, EDX) */ +#define AVX10_FEATURE_WORDS 8 + +typedef struct AVX10VersionDefinition { + const char *name; + /* AVX10 version */ + uint8_t version; + /* AVX10 (CPUID 0x24) maximum supported sub-leaf. */ + uint8_t max_subleaf; + FeatureMask *features; +} AVX10VersionDefinition; + +static const AVX10VersionDefinition builtin_avx10_defs[] =3D { + { + .name =3D "avx10.1", + .version =3D 1, + .max_subleaf =3D 0, + .features =3D (FeatureMask[]) { + { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, + { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, + { /* end of list */ } + } + }, + { + .name =3D "avx10.2", + .version =3D 2, + .max_subleaf =3D 1, + .features =3D (FeatureMask[]) { + { FEAT_24_1_ECX, CPUID_24_1_ECX_AVX10_VNNI_INT }, + { /* end of list */ } + } + }, +}; + static const CPUCaches epyc_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { .type =3D DATA_CACHE, @@ -7242,6 +7276,65 @@ static void x86_cpuid_set_tsc_freq(Object *obj, Visi= tor *v, const char *name, cpu->env.tsc_khz =3D cpu->env.user_tsc_khz =3D value / 1000; } =20 +static void x86_cpuid_get_avx10_version(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + X86CPU *cpu =3D X86_CPU(obj); + uint8_t value; + + value =3D cpu->env.avx10_version; + visit_type_uint8(v, name, &value, errp); +} + +static bool x86_cpu_apply_avx10_features(X86CPU *cpu, uint8_t version, + Error **errp) +{ + const AVX10VersionDefinition *def; + CPUX86State *env =3D &cpu->env; + + if (!version) { + env->avx10_version =3D 0; + env->avx10_max_subleaf =3D 0; + return true; + } + + for (int i =3D 0; i < ARRAY_SIZE(builtin_avx10_defs); i++) { + FeatureMask *f; + + def =3D &builtin_avx10_defs[i]; + for (f =3D def->features; f && f->mask; f++) { + env->features[f->index] |=3D f->mask; + } + + if (def->version =3D=3D version) { + env->avx10_version =3D version; + env->avx10_max_subleaf =3D def->max_subleaf; + break; + } + } + + if (def->version < version) { + error_setg(errp, "avx10-version can be at most %d", def->version); + return false; + } + return true; +} + +static void x86_cpuid_set_avx10_version(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + X86CPU *cpu =3D X86_CPU(obj); + uint8_t value; + + if (!visit_type_uint8(v, name, &value, errp)) { + return; + } + + x86_cpu_apply_avx10_features(cpu, value, errp); +} + /* Generic getter for "feature-words" and "filtered-features" properties */ static void x86_cpu_get_feature_words(Object *obj, Visitor *v, const char *name, void *opaque, @@ -7932,8 +8025,10 @@ static void x86_cpu_load_model(X86CPU *cpu, const X8= 6CPUModel *model) */ object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abo= rt); =20 - object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_vers= ion, - &error_abort); + if (def->avx10_version) { + object_property_set_uint(OBJECT(cpu), "avx10-version", + def->avx10_version, &error_abort); + } =20 x86_cpu_apply_version_props(cpu, model); =20 @@ -8479,9 +8574,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; } if (count =3D=3D 0) { - uint32_t unused; - x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused, - &unused, &unused); + *eax =3D env->avx10_max_subleaf; *ebx =3D env->features[FEAT_24_0_EBX] | env->avx10_version; } else if (count =3D=3D 1) { *ecx =3D env->features[FEAT_24_1_ECX]; @@ -9174,7 +9267,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->a= vx10_version) { uint32_t eax, ebx, ecx, edx; x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); - env->avx10_version =3D ebx & 0xff; + + if (!object_property_set_uint(OBJECT(cpu), "avx10-version", + ebx & 0xff, errp)) { + return; + } } } =20 @@ -9403,6 +9500,11 @@ static bool x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) warn_report("%s: avx10.%d. Adjust to avx10.%d", prefix, env->avx10_version, version); } + /* + * Discrete feature bits have been checked and filtered based = on + * host support. So it's safe to change version without revert= ing + * other feature bits. + */ env->avx10_version =3D version; have_filtered_features =3D true; } @@ -10239,7 +10341,6 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), - DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_leve= l, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), @@ -10381,6 +10482,11 @@ static void x86_cpu_common_class_init(ObjectClass = *oc, const void *data) x86_cpu_get_unavailable_features, NULL, NULL, NULL); =20 + object_class_property_add(oc, "avx10-version", "uint8", + x86_cpuid_get_avx10_version, + x86_cpuid_set_avx10_version, + NULL, NULL); + #if !defined(CONFIG_USER_ONLY) object_class_property_add(oc, "crash-information", "GuestPanicInformat= ion", x86_cpu_get_crash_info_qom, NULL, NULL, NULL= ); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 749ac8455e18..2546463fd6fe 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2218,6 +2218,8 @@ typedef struct CPUArchState { FeatureWordArray features; /* AVX10 version */ uint8_t avx10_version; + /* AVX10 (CPUID 0x24) maximum supported sub-leaf. */ + uint8_t avx10_max_subleaf; /* Features that were explicitly enabled/disabled */ FeatureWordArray user_features; uint32_t cpuid_model[12]; --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1765782843; cv=none; d=zohomail.com; s=zohoarc; b=O8oBOWnzCGHDmXUbjW6vk66pQKJRWlb6iU6cufqB+iCwQTo/GKpUrECTy2C13jb78A+BWfC13hLVfB0uHS6Msyx6xzcbSdHcV4Z16ZbE0wyIWtHcdvRActwfZCJWdPWdGuUODwe2XuclPUhFmCTQlOAuN/uUGEMZYkBMHIHS47U= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782844891158501 Content-Type: text/plain; charset="utf-8" Factor out a helper to get host avx10 version, to reduce duplicate codes. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 05b001b80cfd..c47e06cb79e7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7757,6 +7757,13 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Err= or **errp) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static uint8_t x86_cpu_get_host_avx10_version(void) +{ + uint32_t eax, ebx, ecx, edx; + x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); + return ebx & 0xff; +} + uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) { FeatureWordInfo *wi =3D &feature_word_info[w]; @@ -9265,11 +9272,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **e= rrp) } =20 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->a= vx10_version) { - uint32_t eax, ebx, ecx, edx; - x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); + uint8_t version =3D x86_cpu_get_host_avx10_version(); =20 if (!object_property_set_uint(OBJECT(cpu), "avx10-version", - ebx & 0xff, errp)) { + version, errp)) { return; } } @@ -9491,9 +9497,7 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bool= verbose) have_filtered_features =3D x86_cpu_have_filtered_features(cpu); =20 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { - x86_cpu_get_supported_cpuid(0x24, 0, - &eax_0, &ebx_0, &ecx_0, &edx_0); - uint8_t version =3D ebx_0 & 0xff; + uint8_t version =3D x86_cpu_get_host_avx10_version(); =20 if (version < env->avx10_version) { if (prefix) { --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1765782825; cv=none; d=zohomail.com; s=zohoarc; b=XYu4BGtpMkSmzVhPwI+iaCzA0sciIft+ZbHQ7EW4aZ/CeGuellz1qvOVVPWYvAJsTgkjylRQcP1JzivWM2SwoPfIARRQkD2HGU4V8OhTg7kyd+MaB0hFpu8jrU1PnxujiVUjbxtCtYG4YKbZ95/5YhBT6B3OYvweHF3r4R4f9I4= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782827432158500 Content-Type: text/plain; charset="utf-8" The "force_features" ("x-force-features" property) forces setting feature even if host doesn't support, but also reports the warning. Given its function, it's useful for debug, so even if the AVX10 version is unsupported by host, force to set this AVX10 version if x-force-features=3Don. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Changes since v1: * New patch. --- target/i386/cpu.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c47e06cb79e7..41ff4058871a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9500,16 +9500,27 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bo= ol verbose) uint8_t version =3D x86_cpu_get_host_avx10_version(); =20 if (version < env->avx10_version) { - if (prefix) { - warn_report("%s: avx10.%d. Adjust to avx10.%d", - prefix, env->avx10_version, version); - } /* - * Discrete feature bits have been checked and filtered based = on - * host support. So it's safe to change version without revert= ing - * other feature bits. + * With x-force-features=3Don, CPUID_7_1_EDX_AVX10 will not be= masked + * off, so there's no need to zero avx10 version. */ - env->avx10_version =3D version; + if (!cpu->force_features) { + if (prefix) { + warn_report("%s: avx10.%d. Adjust to avx10.%d", + prefix, env->avx10_version, version); + } + /* + * Discrete feature bits have been checked and filtered ba= sed + * on host support. So it's safe to change version without + * reverting other feature bits. + */ + env->avx10_version =3D version; + } else { + if (prefix) { + warn_report("%s: avx10.%d.", + prefix, env->avx10_version); + } + } have_filtered_features =3D true; } } else if (env->avx10_version) { --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1765782881; cv=none; d=zohomail.com; s=zohoarc; b=njjVXyc5zXbsF8kKIrQ3WwT/C0Z9UVejKUNSY1zfcvuf3GMeK6+2y8vHipiKv9eMgNGE2PNz7bWn99WDaFVOaI6FxBdFDZpN5XE8LNWptz2Xy2ONOIZvqc9p4+k8glgteiz9NhSi4k0NtjQeiBx8bDCLuNzgHPjrA5cYI6+7zak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765782881; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: T0fyzjupT7yH8wzUwTG86g== X-CSE-MsgGUID: MpwIVsHHRLSNmMa7c1A/aQ== X-IronPort-AV: E=McAfee;i="6800,10657,11642"; a="90332256" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332256" X-CSE-ConnectionGUID: 7KQqUEnTSESt3Q9ULSvq/w== X-CSE-MsgGUID: rVdwKmeHSqqlz09nSNJcrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265959" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH v2 07/11] i386/cpu: Allow cache to be shared at thread level Date: Mon, 15 Dec 2025 15:37:39 +0800 Message-Id: <20251215073743.4055227-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782882966158500 Content-Type: text/plain; charset="utf-8" In CPUID 0x4 leaf, it's possible to make the cache privated at thread level when there's no HT within the core. In this case, while cache per thread and cache per core are essentially identical, their topology information differs in CPUID 0x4. Diamond Rapids assigns the L1 i/d cache at the thread level. To allow accurate emulation of DMR cache topology, remove the cache-per-thread restriction in max_thread_ids_for_cache(), which enables CPUID 0x4 to support cache per thread topology. Given that after adding thread-level support, the topology offset information required by max_thread_ids_for_cache() can be sufficiently provided by apicid_offset_by_topo_level(), so it's straightforward to re-implement max_thread_ids_for_cache() based on apicid_offset_by_topo_level() to reduce redundant duplicate codes. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 53 ++++++++++++++--------------------------------- 1 file changed, 15 insertions(+), 38 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 41ff4058871a..1deed542561c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -304,33 +304,30 @@ static void encode_cache_cpuid2(X86CPU *cpu, ((t) =3D=3D UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 0 /* Invalid value */) =20 -static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, - enum CpuTopologyLevel share_level) +static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, + enum CpuTopologyLevel topo_lev= el) { - uint32_t num_ids =3D 0; - - switch (share_level) { + switch (topo_level) { + case CPU_TOPOLOGY_LEVEL_THREAD: + return 0; case CPU_TOPOLOGY_LEVEL_CORE: - num_ids =3D 1 << apicid_core_offset(topo_info); - break; + return apicid_core_offset(topo_info); case CPU_TOPOLOGY_LEVEL_MODULE: - num_ids =3D 1 << apicid_module_offset(topo_info); - break; + return apicid_module_offset(topo_info); case CPU_TOPOLOGY_LEVEL_DIE: - num_ids =3D 1 << apicid_die_offset(topo_info); - break; + return apicid_die_offset(topo_info); case CPU_TOPOLOGY_LEVEL_SOCKET: - num_ids =3D 1 << apicid_pkg_offset(topo_info); - break; + return apicid_pkg_offset(topo_info); default: - /* - * Currently there is no use case for THREAD, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); } + return 0; +} =20 - return num_ids - 1; +static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, + enum CpuTopologyLevel share_level) +{ + return (1 << apicid_offset_by_topo_level(topo_info, share_level)) - 1; } =20 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) @@ -398,26 +395,6 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoIn= fo *topo_info, return 0; } =20 -static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, - enum CpuTopologyLevel topo_lev= el) -{ - switch (topo_level) { - case CPU_TOPOLOGY_LEVEL_THREAD: - return 0; - case CPU_TOPOLOGY_LEVEL_CORE: - return apicid_core_offset(topo_info); - case CPU_TOPOLOGY_LEVEL_MODULE: - return apicid_module_offset(topo_info); - case CPU_TOPOLOGY_LEVEL_DIE: - return apicid_die_offset(topo_info); - case CPU_TOPOLOGY_LEVEL_SOCKET: - return apicid_pkg_offset(topo_info); - default: - g_assert_not_reached(); - } - return 0; -} - static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) { switch (topo_level) { --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 15 Dec 2025 02:13:17 -0500 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2025 23:13:15 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 14 Dec 2025 23:13:13 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765782796; x=1797318796; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DQKY+pMsXXbbU9Xz9iV7D6PsC8YZn6Qa+YVZAqB1vuU=; b=Q9By7wea7ArqLAlN+11WlDjVTzc6g2YwIO/zZFx4KqDrn7mQXqzCB2ux N0lRhbWB+kns6fPGViGPNu2ic5xXrQoxxiSJfDcrSUO/ko+gBTygbVkQm U5e9SsG1JSfzpBuxHGcfeHWErSA8MvLCTUa1370vv6D56Fn9/rtgCN5/2 s38dtQGK4vQccBA+m53ZFm4Qt65fSTEc3htuu+1gM5ItWPv49rFX+gE5L T6dnry8GdBTRz88D7vw9569lzjYV3U4WvRMmfUJ9j+BROCE2g1L0Wnj4s 9zh0sADHdBApoEUlgPD/0Y7Uzzy58ONfjUPcHTc/IzcXg7/UGfZB027ZA A==; X-CSE-ConnectionGUID: gK2qEReaRPK09De4Wz67yA== X-CSE-MsgGUID: BCB3mejtS+aiWd+a+brb0w== X-IronPort-AV: E=McAfee;i="6800,10657,11642"; a="90332259" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332259" X-CSE-ConnectionGUID: 9bs0c17PTFqjuUWkkFEI9w== X-CSE-MsgGUID: v/Z/DRMxQjqrdzQ+K9ibpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265963" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH v2 08/11] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Date: Mon, 15 Dec 2025 15:37:40 +0800 Message-Id: <20251215073743.4055227-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782905035158500 Content-Type: text/plain; charset="utf-8" Many Intel CPUs enable CPUID 0x1f by default to encode CPU topology information. Add the "cpuid_0x1f" option to X86CPUDefinition to allow named CPU models to configure CPUID 0x1f from the start, thereby forcing 0x1f to be present for guest. With this option, there's no need to explicitly add v1 model to an unversioned CPU model for explicitly enabling the x-force-cpuid-0x1f property. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1deed542561c..6998c900b1dc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2313,6 +2313,12 @@ typedef struct X86CPUDefinition { int model; int stepping; uint8_t avx10_version; + /* + * Whether to present CPUID 0x1f by default. + * If true, encode CPU topology in 0x1f leaf even if there's no + * extended topology levels. + */ + bool cpuid_0x1f; FeatureWordArray features; const char *model_id; const CPUCaches *const cache_info; @@ -8014,6 +8020,10 @@ static void x86_cpu_load_model(X86CPU *cpu, const X8= 6CPUModel *model) def->avx10_version, &error_abort); } =20 + if (def->cpuid_0x1f) { + object_property_set_bool(OBJECT(cpu), "x-force-cpuid-0x1f", + def->cpuid_0x1f, &error_abort); + } x86_cpu_apply_version_props(cpu, model); =20 /* --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 15 Dec 2025 02:13:18 -0500 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2025 23:13:17 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 14 Dec 2025 23:13:15 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765782797; x=1797318797; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Od7MH3p6ChJmtLWUaAsLaiPAZLqzLKYPw3Ayr328ah8=; b=ZzBdHMDD3d0YARqfx22BJOMxLJKzCK+eZ3nRDqzrligcx8hp4I1wZhMA Dxz0z29uDUqisogo/+T9O4DhfFa9t0u0E2VmgORvOp1vnUrRKdqj6SdR5 25oRjqZcxrjfLRdhjDeGJIRItqEaP6xe4LniiXd2gZOXBsOamlPP2sWHE 8w+yldskP2U/W7kFxaMUcNrQGDqg2W5kNeK6qX49mtL33VPMUoFBZqaGb qBX0vWA+/uML+DwXML3L48lhm3/uslVNUyRYAFdE95s497IS4dHXHHOYF SIN9NM3LaZKAr2TZWpoypTPnBVFgYFPbTv4Mqel4dc50uCxXrRUQmatl9 w==; X-CSE-ConnectionGUID: JD+1utEdR5uU+Xvz4tQesg== X-CSE-MsgGUID: +TZO43qAS4WdwkE13HGk8g== X-IronPort-AV: E=McAfee;i="6800,10657,11642"; a="90332262" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332262" X-CSE-ConnectionGUID: 2x8ehcjzTTeBTiiJTHLyeQ== X-CSE-MsgGUID: i42Pdx5xTwq/NAlLeqtxvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265970" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH v2 09/11] i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED Date: Mon, 15 Dec 2025 15:37:41 +0800 Message-Id: <20251215073743.4055227-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782840692158500 Content-Type: text/plain; charset="utf-8" VMX_VM_ENTRY_LOAD_IA32_FRED depends on FRED. Define this dependency relationship. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 4 ++++ target/i386/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6998c900b1dc..07ece8878542 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2036,6 +2036,10 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, .to =3D { FEAT_24_1_ECX, ~0ull }, }, + { + .from =3D { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, + .to =3D { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_IA32_FRED = }, + }, }; =20 typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2546463fd6fe..d341e9835716 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1441,6 +1441,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 #define VMX_VM_ENTRY_LOAD_CET 0x00100000 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 +#define VMX_VM_ENTRY_LOAD_IA32_FRED 0x00800000 =20 /* Supported Hyper-V Enlightenments */ #define HYPERV_FEAT_RELAXED 0 --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="90332265" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332265" X-CSE-ConnectionGUID: SZIwA9fcTy2alVYieE1z5Q== X-CSE-MsgGUID: FZ6kGFEwT2KqEQHAXqDd5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265978" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH v2 10/11] i386/cpu: Add CPU model for Diamond Rapids Date: Mon, 15 Dec 2025 15:37:42 +0800 Message-Id: <20251215073743.4055227-11-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782888997158500 Content-Type: text/plain; charset="utf-8" According to table 1-2 in Intel Architecture Instruction Set Extensions and Future Features (rev 059), Diamond Rapids has the following new features which have already been supported for guest: * SM4 (EVEX) * Intel Advanced Vector Extensions 10 Version 2 (Intel AVX10.2) * MOVRS and the PREFETCHRST2 instruction * AMX-MOVRS, AMX-AVX512, AMX-FP8, AMX-TF32 * Intel Advanced Performance Extensions And FRED - Flexible Return and Event Delivery (FRED) and the LKGS instruction (introduced since Clearwater Forest & Diamond Rapids) - is included in Diamond Rapids CPU model. In addition, the following features are added into Diamond Rapids CPU model: * CET: Control-flow Enforcement Technology (introduced since Sapphire Rapids & Sierra Forest). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891 --- target/i386/cpu.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 192 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 07ece8878542..ab2d23150c86 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5443,6 +5443,198 @@ static const X86CPUDefinition builtin_x86_defs[] = =3D { { /* end of list */ }, }, }, + { + .name =3D "DiamondRapids", + .level =3D 0x29, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 0x13, /* family: 0xf, extended famil: 0x4 */ + .model =3D 0x1, /* model: 0x1, extended model: 0x0 */ + .stepping =3D 0, + .avx10_version =3D 2, /* avx10.2 */ + .cpuid_0x1f =3D true, + /* + * Please keep the ascending order so that we can have a clear vie= w of + * bit position of each feature. + * + * Missing: CPUID_EXT_DTES64, CPUID_EXT_MONITOR, CPUID_EXT_DSCPL, + * CPUID_EXT_VMX, CPUID_EXT_SMX, CPUID_EXT_EST, CPUID_EXT_TM2, + * CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_DCA, CPUID_EXT_OSXSAVE + */ + .features[FEAT_1_ECX] =3D + CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | + CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SS= E41 | + CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | + CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AE= S | + CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_R= DRAND, + /* Missing: CPUID_DTS, CPUID_ACPI, CPUID_HT, CPUID_TM, CPUID_PBE */ + .features[FEAT_1_EDX] =3D + CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | + CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | + CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | + CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FX= SR | + CPUID_SSE | CPUID_SSE2 | CPUID_SS, + .features[FEAT_6_EAX] =3D CPUID_6_EAX_ARAT, + /* + * Missing: CPUID_7_0_EBX_SGX, "cqm" Cache QoS Monitoring, + * "rdt_a" Resource Director Technology Allocation, + * CPUID_7_0_EBX_INTEL_PT, + */ + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | + CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | + CPUID_7_0_EBX_FDP_EXCPTN_ONLY | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_ZERO_FCS_FDS | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | + CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | + CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_AVX512BW | + CPUID_7_0_EBX_AVX512VL, + /* + * Missing: CPUID_7_0_ECX_OSPKE, CPUID_7_0_ECX_WAITPKG, TME, ENQCM= D, + * CPUID_7_0_ECX_SGX_LC, CPUID_7_0_ECX_PKS + */ + .features[FEAT_7_0_ECX] =3D + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | + CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_AVX512_VBMI2 | + CPUID_7_0_ECX_CET_SHSTK | CPUID_7_0_ECX_GFNI | CPUID_7_0_ECX_V= AES | + CPUID_7_0_ECX_VPCLMULQDQ | CPUID_7_0_ECX_AVX512VNNI | + CPUID_7_0_ECX_AVX512BITALG | CPUID_7_0_ECX_AVX512_VPOPCNTDQ | + CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_RDPID | + CPUID_7_0_ECX_BUS_LOCK_DETECT | CPUID_7_0_ECX_CLDEMOTE | + CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_MOVDIR64B, + /* + * Missing: SGX-KEYS, UINTR, PCONFIG, ARCH LBR, + * CPUID_7_0_EDX_CORE_CAPABILITY + */ + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_MD_CLEAR | + CPUID_7_0_EDX_SERIALIZE | CPUID_7_0_EDX_TSX_LDTRK | + CPUID_7_0_EDX_CET_IBT | CPUID_7_0_EDX_AMX_BF16 | + CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | + CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | + CPUID_7_0_EDX_STIBP | CPUID_7_0_EDX_FLUSH_L1D | + CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, + /* Missing: CPUID_7_1_EAX_LASS, ArchPerfmonExt (0x23 leaf), MSRLIS= T */ + .features[FEAT_7_1_EAX] =3D + CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | + CPUID_7_1_EAX_CMPCCXADD | CPUID_7_1_EAX_FZRM | + CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_FRED | + CPUID_7_1_EAX_LKGS | CPUID_7_1_EAX_WRMSRNS | + CPUID_7_1_EAX_AMX_FP16 | CPUID_7_1_EAX_AVX_IFMA | + CPUID_7_1_EAX_LAM | CPUID_7_1_EAX_MOVRS, + /* Missing: CET_SSS */ + .features[FEAT_7_1_EDX] =3D + CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | + CPUID_7_1_EDX_AMX_COMPLEX | CPUID_7_1_EDX_PREFETCHITI | + CPUID_7_1_EDX_AVX10 | CPUID_7_1_EDX_APXF, + /* Missing: UC-lock disable */ + .features[FEAT_7_2_EDX] =3D + CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | + CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | + CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, + .features[FEAT_1E_1_EAX] =3D + CPUID_1E_1_EAX_AMX_INT8_MIRROR | CPUID_1E_1_EAX_AMX_BF16_MIRRO= R | + CPUID_1E_1_EAX_AMX_COMPLEX_MIRROR | + CPUID_1E_1_EAX_AMX_FP16_MIRROR | CPUID_1E_1_EAX_AMX_FP8 | + CPUID_1E_1_EAX_AMX_TF32 | CPUID_1E_1_EAX_AMX_AVX512 | + CPUID_1E_1_EAX_AMX_MOVRS, + .features[FEAT_29_0_EBX] =3D CPUID_29_0_EBX_APX_NCI_NDD_NF, + /* + * Though this bit will be set by avx_version=3D2, it's better to + * explicitly enumerate this feature here. + */ + .features[FEAT_24_1_ECX] =3D CPUID_24_1_ECX_AVX10_VNNI_INT, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, + .features[FEAT_8000_0008_EBX] =3D CPUID_8000_0008_EBX_WBNOINVD, + /* + * Missing: ARCH_CAP_RRSBA (KVM bit 19), ARCH_CAP_RFDS_CLEAR (KVM = bit + * 28), MCU_CONTROL (bit 9), MISC_PACKAGE_CTLS (bit 10), + * ENERGY_FILTERING_CTL (bit 11), DOITM (bit 12), MCU_ENUMERATION = (bit + * 16), RRSBA (bit 19), XAPIC_DISABLE_STATUS (bit 21), + * OVERCLOCKING_STATUS (bit 23). + */ + .features[FEAT_ARCH_CAPABILITIES] =3D + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | + MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | + MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | + MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_BHI_NO | + MSR_ARCH_CAP_PBRSB_NO | MSR_ARCH_CAP_GDS_NO | + MSR_ARCH_CAP_RFDS_NO, + .features[FEAT_VMX_BASIC] =3D + MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS | + MSR_VMX_BASIC_NESTED_EXCEPTION, + .features[FEAT_VMX_ENTRY_CTLS] =3D + VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | + VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER | + VMX_VM_ENTRY_LOAD_CET | VMX_VM_ENTRY_LOAD_IA32_FRED, + .features[FEAT_VMX_EPT_VPID_CAPS] =3D + MSR_VMX_EPT_EXECONLY | + MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_= 5 | + MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | + MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | + MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CON= TEXT | + MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | + MSR_VMX_EPT_INVVPID_ALL_CONTEXT | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, + .features[FEAT_VMX_EXIT_CTLS] =3D + VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_= SIZE, + VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | + VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER | + VMX_VM_EXIT_SAVE_CET | VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS, + .features[FEAT_VMX_MISC] =3D + MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | + MSR_VMX_MISC_ACTIVITY_SHUTDOWN | MSR_VMX_MISC_ACTIVITY_WAIT_SI= PI | + MSR_VMX_MISC_VMWRITE_VMEXIT, + .features[FEAT_VMX_PINBASED_CTLS] =3D + VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | + VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIME= R | + VMX_PIN_BASED_POSTED_INTR, + .features[FEAT_VMX_PROCBASED_CTLS] =3D + VMX_CPU_BASED_VIRTUAL_INTR_PENDING | + VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | + VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | + VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | + VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITI= NG | + VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITI= NG | + VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | + VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING= | + VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG= | + VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | + VMX_CPU_BASED_PAUSE_EXITING | + VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, + .features[FEAT_VMX_SECONDARY_CTLS] =3D + VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | + VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | + VMX_SECONDARY_EXEC_RDTSCP | + VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | + VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXI= TING | + VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | + VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | + VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | + VMX_SECONDARY_EXEC_RDRAND_EXITING | + VMX_SECONDARY_EXEC_ENABLE_INVPCID | + VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_V= MCS | + VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_= PML | + VMX_SECONDARY_EXEC_XSAVES | VMX_SECONDARY_EXEC_TSC_SCALING | + VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE, + .features[FEAT_VMX_VMFUNC] =3D MSR_VMX_VMFUNC_EPT_SWITCHING, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Xeon Processor (DiamondRapids)", + }, { .name =3D "SierraForest", .level =3D 0x23, --=20 2.34.1 From nobody Thu Dec 18 04:17:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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l1vEyTl3TSqB8cVJlAVCNQ== X-IronPort-AV: E=McAfee;i="6800,10657,11642"; a="90332267" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="90332267" X-CSE-ConnectionGUID: yJ6xNHsJQbqOyvE6rnALXg== X-CSE-MsgGUID: 64KR+f/gQbCJ8sjR7kEaUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197265982" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu , Yu Chen Subject: [PATCH v2 11/11] dosc/cpu-models-x86: Add documentation for DiamondRapids Date: Mon, 15 Dec 2025 15:37:43 +0800 Message-Id: <20251215073743.4055227-12-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251215073743.4055227-1-zhao1.liu@intel.com> References: <20251215073743.4055227-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765782890965158500 Content-Type: text/plain; charset="utf-8" Current DiamondRapids hasn't supported cache model. Instead, document its special CPU & cache topology to allow user emulate with "-smp" & "-machine smp-cache". Reviewed-by: Yu Chen Signed-off-by: Zhao Liu --- docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x8= 6.rst.inc index 6a770ca8351c..c4c8fc67a562 100644 --- a/docs/system/cpu-models-x86.rst.inc +++ b/docs/system/cpu-models-x86.rst.inc @@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live mig= ration compatibility is required, use the newest CPU model that is compatible across all desired hosts. =20 +``DiamondRapids`` + Intel Xeon Processor. + + Diamond Rapids product has a topology which differs from previous Xeon + products. It does not support SMT, but instead features a dual core + module (DCM) architecture. It also has core building blocks (CBB - die + level in CPU topology). The cache hierarchy is organized as follows: + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per + CBB. This cache topology can be emulated for DiamondRapids CPU model + using the smp-cache configuration as shown below: + + Example: + + :: + + -machine smp-cache.0.cache=3Dl1d,smp-cache.0.topology=3Dthread= ,\ + smp-cache.1.cache=3Dl1i,smp-cache.1.topology=3Dthread= ,\ + smp-cache.2.cache=3Dl2,smp-cache.2.topology=3Dmodule,\ + smp-cache.3.cache=3Dl3,smp-cache.3.topology=3Ddie + ``ClearwaterForest`` Intel Xeon Processor (ClearwaterForest, 2025) =20 --=20 2.34.1