From nobody Tue Dec 16 03:38:58 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1765781653; cv=none; d=zohomail.com; s=zohoarc; b=NU4EkQbzSleW/bZoddI9lbBbA6JVtcUj59+5za+o4a577MLjMZU8AP1nAfKHkNPzwHg/6VDug9vkw8f9EAorHmmAWfdkJRpqqrttMk7UkLagVNZ3mVGMd1p5zuXYRgkiHlQGYAypfe69zRdZexX+i3tDkWzTvB7Qdd03zr4c4XU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765781653; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2EsUU5KUquJHf3+WrFNYSaX+N8A+Ha8bS6pCd0eiTkY=; b=lCr8B/Hq9nxL5XWlTO+H3R2Pv9HbOGrXQtzcKmn9BrBJiRm8uIAV4DTpMHt2hBprAbE57+A1kb02rTohCuGquqZIT1jP1fYPxkUA8KJQqdwzwXV9hC8SWi3bevSS3GozVV3Ikxr55Psc0CNHRJumtb8RfkNxdk5JLFH/+2bAl0o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176578165391352.114881387174705; Sun, 14 Dec 2025 22:54:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vV2R5-0008BO-Fo; Mon, 15 Dec 2025 01:51:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vV2R3-0008Ax-W0 for qemu-devel@nongnu.org; Mon, 15 Dec 2025 01:51:58 -0500 Received: from mgamail.intel.com ([198.175.65.15]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vV2R2-0000u9-6N for qemu-devel@nongnu.org; Mon, 15 Dec 2025 01:51:57 -0500 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2025 22:51:56 -0800 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2025 22:51:52 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765781517; x=1797317517; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cwZPdK9NC99Ad8Z0dhse6aPJ9AlerzfXjqzYgBa+xp4=; b=i6CB8mCfS71mVtAvir1Vhlk/An+1AMCEDfmKIudifqeDs21apREjOdZz LzMvvEERogRT98FWulcLQzValdj/R6A/5dvHISjbl5cqcC+YJufhDdHey nAooWOvzeX4ArJbKQ5JQseclcJt+fdEo44LDAtgcxnlC0bifhavatDGR7 8Fjs5E83cv7V7Al4mAftpAH/7LKmtvcSYBUStwMvSUTtaAU4Oql+tsrbD GBsoXwiX7KdJL/1sfPTP4hPaOiXYmqiwkTu7Nr7y8zOEKP5VgCDa1NTlv wJRGtl/Ht/NfKA3LkgbZetXkLSArqyAv6E/CeVMnHR1TvVtpY35T0T174 w==; X-CSE-ConnectionGUID: 1UHacdp1QZWKHwPmGr6tvw== X-CSE-MsgGUID: MASAeLbQR9WICwLQ1VZQkg== X-IronPort-AV: E=McAfee;i="6800,10657,11642"; a="71305009" X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="71305009" X-CSE-ConnectionGUID: VflW8yYYSSaQSRvDowmjww== X-CSE-MsgGUID: 2asy4frVRdaiZO0nNUBhbA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,150,1763452800"; d="scan'208";a="197408797" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v9 10/19] intel_iommu_accel: Fail passthrough device under PCI bridge if x-flts=on Date: Mon, 15 Dec 2025 01:50:34 -0500 Message-ID: <20251215065046.86991-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251215065046.86991-1-zhenzhong.duan@intel.com> References: <20251215065046.86991-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1765781655340158500 Content-Type: text/plain; charset="utf-8" Currently we don't support nested translation for passthrough device with emulated device under same PCI bridge, because they require different addre= ss space when x-flts=3Don. In theory, we do support if devices under same PCI bridge are all passthrou= gh devices. But emulated device can be hotplugged under same bridge. To simpli= fy, just forbid passthrough device under PCI bridge no matter if there is, or w= ill be emulated devices under same bridge. This is acceptable because PCIE brid= ge is more popular than PCI bridge now. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu_accel.h | 4 ++-- hw/i386/intel_iommu.c | 7 ++++--- hw/i386/intel_iommu_accel.c | 12 +++++++++++- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 472ae109e2..76e0d26942 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -13,11 +13,11 @@ #include CONFIG_DEVICES =20 #ifdef CONFIG_VTD_ACCEL -bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, +bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, - HostIOMMUDevice *hiod, + VTDHostIOMMUDevice *vtd_hiod, Error **errp) { error_setg(errp, "host IOMMU cannot be checked!"); diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6b86cd5ada..5bf1c0e5a4 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4570,9 +4570,10 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, return vtd_dev_as; } =20 -static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, +static bool vtd_check_hiod(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hio= d, Error **errp) { + HostIOMMUDevice *hiod =3D vtd_hiod->hiod; HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); int ret; =20 @@ -4596,7 +4597,7 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, return true; } =20 - return vtd_check_hiod_accel(s, hiod, errp); + return vtd_check_hiod_accel(s, vtd_hiod, errp); } =20 static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, @@ -4632,7 +4633,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hiod->iommu_state =3D s; vtd_hiod->hiod =3D hiod; =20 - if (!vtd_check_hiod(s, hiod, errp)) { + if (!vtd_check_hiod(s, vtd_hiod, errp)) { g_free(vtd_hiod); vtd_iommu_unlock(s); return false; diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 6846c6ec4d..ead6c42879 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -12,12 +12,16 @@ #include "system/iommufd.h" #include "intel_iommu_internal.h" #include "intel_iommu_accel.h" +#include "hw/pci/pci_bus.h" =20 -bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, +bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp) { + HostIOMMUDevice *hiod =3D vtd_hiod->hiod; struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + PCIBus *bus =3D vtd_hiod->bus; + PCIDevice *pdev =3D bus->devices[vtd_hiod->devfn]; =20 if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { error_setg(errp, "Need IOMMUFD backend when x-flts=3Don"); @@ -36,6 +40,12 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUD= evice *hiod, return false; } =20 + if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) { + error_setg(errp, "Host device downstream to a PCI bridge is " + "unsupported when x-flts=3Don"); + return false; + } + error_setg(errp, "host IOMMU is incompatible with guest first stage translat= ion"); return false; --=20 2.47.1